Atmel QTouch Library User Guide - Farnell Element 14 - Revenir à l'accueil
Farnell Element 14 :
Farnell-CLRC632-NXP-..> 20-Dec-2014 10:22 2.6M
Farnell-7491181012-O..> 20-Dec-2014 10:22 2.6M
Farnell-LPC4350-30-2..> 20-Dec-2014 10:21 1.4M
Farnell-LPC178x-7x-N..> 20-Dec-2014 10:21 1.6M
Farnell-Data-Sheet-J..> 20-Dec-2014 10:21 1.0M
Farnell-LPC81xM-NXP-..> 20-Dec-2014 10:20 1.2M
Farnell-Data-Sheet-J..> 20-Dec-2014 10:20 1.2M
Farnell-SL3S1003_101..> 20-Dec-2014 10:06 2.0M
Farnell-NT3H1101-NT3..> 20-Dec-2014 10:06 2.3M
Farnell-LPC1769-68-6..> 20-Dec-2014 10:06 2.2M
Farnell-SL3S1203_121..> 20-Dec-2014 10:01 2.0M
Farnell-PN512-NXP-Se..> 20-Dec-2014 10:01 1.9M
Farnell-MMBZxVCL-MMB..> 20-Dec-2014 09:53 1.6M
Farnell-Datasheet-NX..> 20-Dec-2014 09:52 1.6M
Farnell-IP4251_52_53..> 20-Dec-2014 09:51 1.6M
Farnell-BC846DS2-NXP..> 20-Dec-2014 09:48 1.2M
Farnell-BAT54J-Schot..> 20-Dec-2014 09:47 1.1M
Farnell-PMEG3010EP-N..> 20-Dec-2014 09:47 1.1M
Farnell-AVR172-Senso..> 20-Dec-2014 09:47 1.2M
Farnell-PBSS5320X-NX..> 20-Dec-2014 09:47 1.6M
Farnell-ATtiny2313-A..> 20-Dec-2014 09:47 1.6M
Farnell-SG2525A-SG35..> 20-Dec-2014 09:39 1.0M
Farnell-PMBT3906-PNP..> 20-Dec-2014 09:39 1.0M
Farnell-PDTB123TT-NX..> 20-Dec-2014 09:39 1.0M
Farnell-PIC12F529T39..> 20-Dec-2014 09:39 1.0M
Farnell-PSMN011-80YS..> 20-Dec-2014 09:39 1.1M
Farnell-PESD5V0F1BL-..> 20-Dec-2014 09:39 1.1M
Farnell-MB85RS128B-F..> 20-Dec-2014 09:38 1.1M
Farnell-SMAJ-STMicro..> 13-Oct-2014 07:07 734K
Farnell-L6562-STMicr..> 13-Oct-2014 07:07 754K
Farnell-LM139-LM239-..> 13-Oct-2014 07:07 771K
Farnell-L4978-STMicr..> 13-Oct-2014 07:07 783K
Farnell-ST1S10PHR-ST..> 13-Oct-2014 07:06 820K
Farnell-TIP41C-TIP42..> 13-Oct-2014 07:06 829K
Farnell-MC34063ABD-T..> 13-Oct-2014 07:06 844K
Farnell-ESM6045DV-ST..> 13-Oct-2014 07:06 850K
Farnell-TIP102-TIP10..> 13-Oct-2014 07:06 853K
Farnell-ST3232B-ST32..> 13-Oct-2014 07:06 867K
Farnell-STM32F030x4-..> 13-Oct-2014 07:06 1.1M
Farnell-STM32F103x8-..> 13-Oct-2014 07:06 1.0M
Farnell-STM32F405xx-..> 13-Oct-2014 07:05 1.4M
Farnell-STM32F205xx-..> 13-Oct-2014 07:05 1.7M
Farnell-STP16NF06L-n..> 13-Oct-2014 07:05 1.7M
Farnell-STP80NF55L-0..> 13-Oct-2014 07:05 1.7M
Farnell-LM217-LM317-..> 13-Oct-2014 07:04 1.7M
Farnell-LM2904-LM290..> 13-Oct-2014 07:04 1.7M
Farnell-L78-Positive..> 13-Oct-2014 07:04 1.8M
Farnell-VND920P-E-ST..> 13-Oct-2014 07:04 1.8M
Farnell-LM350-STMicr..> 13-Oct-2014 07:03 1.8M
Smart_street_lightin..> 13-Oct-2014 07:03 1.6M
Farnell-Smart-street..> 13-Oct-2014 07:02 1.8M
Farnell-ULN2001-ULN2..> 13-Oct-2014 07:02 1.9M
Farnell-ULQ2001-ULQ2..> 13-Oct-2014 07:02 1.9M
Farnell-L6384E-STMic..> 13-Oct-2014 07:02 1.9M
Farnell-AN2794-Appli..> 13-Oct-2014 07:01 1.0M
Farnell-STEVAL-TDR02..> 13-Oct-2014 07:01 960K
Farnell-TL084-TL084A..> 11-Oct-2014 15:54 1.7M
Farnell-TDA7296-STMi..> 11-Oct-2014 15:54 1.7M
Farnell-L78-STMicroe..> 11-Oct-2014 15:49 1.6M
Farnell-LM158-LM258-..> 11-Oct-2014 15:49 1.6M
Farnell-LF351-STMicr..> 11-Oct-2014 15:49 1.7M
Farnell-L293B-STMicr..> 11-Oct-2014 15:49 1.7M
Farnell-NE556-SA556-..> 11-Oct-2014 15:48 1.7M
Farnell-SO967460-PDF..> 11-Oct-2014 12:05 2.9M
Farnell-Everything-Y..> 11-Oct-2014 12:05 1.5M
cookiechoices.js 27-Sep-2014 12:40 6.0K
Farnell-ULN2803A-Rev..> 09-Sep-2014 19:26 2.9M
Analog-Devices-Convo..> 09-Sep-2014 08:26 2.1M
Analog-Devices-Convo..> 09-Sep-2014 08:25 2.2M
Analog-Devices-Convo..> 09-Sep-2014 08:25 2.2M
Analog-Devices-ADMC4..> 09-Sep-2014 08:23 2.3M
Analog-Devices-Wi-Fi..> 09-Sep-2014 08:23 2.3M
Analog-Devices-ADMC2..> 09-Sep-2014 08:21 2.4M
Analog-Devices-ADC-S..> 09-Sep-2014 08:21 2.4M
Analog-Devices-Visua..> 09-Sep-2014 08:18 2.5M
Analog-Devices-ANF32..> 09-Sep-2014 08:18 2.6M
Farnell-Compensating..> 09-Sep-2014 08:16 2.6M
Farnell-Compensating..> 09-Sep-2014 08:16 2.6M
Farnell-LM7805-Fairc..> 09-Sep-2014 08:13 2.7M
Farnell-AD620-Rev-H-..> 09-Sep-2014 08:13 2.6M
Farnell-Datasheet-FT..> 09-Sep-2014 08:10 2.8M
Farnell-MAX4661-MAX4..> 09-Sep-2014 08:10 2.8M
Farnell-OPA627-Texas..> 09-Sep-2014 08:08 2.8M
Farnell-REF19x-Serie..> 09-Sep-2014 08:08 2.8M
Farnell-Data-Sheet-M..> 09-Sep-2014 08:05 2.8M
Analog-Devices-Digit..> 08-Sep-2014 18:03 2.0M
Analog-Devices-Digit..> 08-Sep-2014 18:02 2.1M
Analog-Devices-Basic..> 08-Sep-2014 17:49 1.9M
Farnell-AD9833-Rev-E..> 08-Sep-2014 17:49 1.8M
Farnell-The-Discrete..> 08-Sep-2014 17:44 1.8M
Electronique-Basic-o..> 08-Sep-2014 17:43 1.8M
Analog-Devices-AN300..> 08-Sep-2014 17:42 2.0M
Analog-Devices-The-C..> 08-Sep-2014 17:41 1.9M
Analog-Devices-Intro..> 08-Sep-2014 17:39 1.9M
Analog-Devices-Compl..> 08-Sep-2014 17:38 2.0M
Analog-Devices-Gloss..> 08-Sep-2014 17:36 2.0M
Farnell-ADuM1300-ADu..> 08-Sep-2014 08:11 1.7M
Farnell-AD586BRZ-Ana..> 08-Sep-2014 08:09 1.6M
Farnell-ADuM1200-ADu..> 08-Sep-2014 08:09 1.6M
Farnell-NA555-NE555-..> 08-Sep-2014 07:51 1.5M
Farnell-AD9834-Rev-D..> 08-Sep-2014 07:32 1.2M
Farnell-MSP430F15x-M..> 08-Sep-2014 07:32 1.3M
Farnell-AD736-Rev-I-..> 08-Sep-2014 07:31 1.3M
Farnell-AD8307-Data-..> 08-Sep-2014 07:30 1.3M
Farnell-Single-Chip-..> 08-Sep-2014 07:30 1.5M
Farnell-Quadruple-2-..> 08-Sep-2014 07:29 1.5M
Farnell-ADE7758-Rev-..> 08-Sep-2014 07:28 1.7M
Farnell-MAX3221-Rev-..> 08-Sep-2014 07:28 1.8M
Farnell-USB-to-Seria..> 08-Sep-2014 07:27 2.0M
Farnell-AD8313-Analo..> 08-Sep-2014 07:26 2.0M
Farnell-SN54HC164-SN..> 08-Sep-2014 07:25 2.0M
Farnell-AD8310-Analo..> 08-Sep-2014 07:24 2.1M
Farnell-AD8361-Rev-D..> 08-Sep-2014 07:23 2.1M
Farnell-2N3906-Fairc..> 08-Sep-2014 07:22 2.1M
Farnell-AD584-Rev-C-..> 08-Sep-2014 07:20 2.2M
Farnell-ADE7753-Rev-..> 08-Sep-2014 07:20 2.3M
Farnell-TLV320AIC23B..> 08-Sep-2014 07:18 2.4M
Farnell-STM32F405xxS..> 27-Aug-2014 18:27 1.8M
Farnell-fx-3650P-fx-..> 29-Jul-2014 10:42 1.5M
Farnell-MSP430-Hardw..> 29-Jul-2014 10:36 1.1M
Farnell-LM324-Texas-..> 29-Jul-2014 10:32 1.5M
Farnell-LM386-Low-Vo..> 29-Jul-2014 10:32 1.5M
Farnell-NE5532-Texas..> 29-Jul-2014 10:32 1.5M
Farnell-Hex-Inverter..> 29-Jul-2014 10:31 875K
Farnell-AT90USBKey-H..> 29-Jul-2014 10:31 902K
Farnell-AT89C5131-Ha..> 29-Jul-2014 10:31 1.2M
Farnell-MSP-EXP430F5..> 29-Jul-2014 10:31 1.2M
Farnell-Explorer-16-..> 29-Jul-2014 10:31 1.3M
Farnell-TMP006EVM-Us..> 29-Jul-2014 10:30 1.3M
Farnell-Gertboard-Us..> 29-Jul-2014 10:30 1.4M
Farnell-LMP91051-Use..> 29-Jul-2014 10:30 1.4M
Farnell-Thermometre-..> 29-Jul-2014 10:30 1.4M
Farnell-user-manuel-..> 29-Jul-2014 10:29 1.5M
Farnell-TLV320AIC325..> 28-Jul-2014 17:45 2.9M
Farnell-2-GBPS-Diffe..> 28-Jul-2014 17:42 2.7M
Farnell-LMT88-2.4V-1..> 28-Jul-2014 17:42 2.8M
Farnell-Octal-Genera..> 28-Jul-2014 17:42 2.8M
Farnell-Dual-MOSFET-..> 28-Jul-2014 17:41 2.8M
Farnell-SN54LV4053A-..> 28-Jul-2014 17:20 5.9M
Farnell-TAS1020B-USB..> 28-Jul-2014 17:19 6.2M
Farnell-TPS40060-Wid..> 28-Jul-2014 17:19 6.3M
Farnell-TL082-Wide-B..> 28-Jul-2014 17:16 6.3M
Farnell-RF-short-tra..> 28-Jul-2014 17:16 6.3M
Farnell-maxim-integr..> 28-Jul-2014 17:14 6.4M
Farnell-TSV6390-TSV6..> 28-Jul-2014 17:14 6.4M
Farnell-Fast-Charge-..> 28-Jul-2014 17:12 6.4M
Farnell-NVE-datashee..> 28-Jul-2014 17:12 6.5M
Farnell-Excalibur-Hi..> 28-Jul-2014 17:10 2.4M
Farnell-Excalibur-Hi..> 28-Jul-2014 17:10 2.4M
Farnell-REF102-10V-P..> 28-Jul-2014 17:09 2.4M
Farnell-TMS320F28055..> 28-Jul-2014 17:09 2.7M
Farnell-ULINKpro-Deb..> 25-Jul-2014 12:35 5.9M
Farnell-WIRE-WRAP-50..> 25-Jul-2014 12:34 5.9M
Farnell-MICROCHIP-PI..> 25-Jul-2014 12:34 6.7M
Farnell-OMRON-INDUST..> 25-Jul-2014 12:32 6.9M
Farnell-OMRON-INDUST..> 25-Jul-2014 12:31 6.9M
Farnell-TYCO-ELECTRO..> 25-Jul-2014 12:30 6.9M
Farnell-Power-suppli..> 25-Jul-2014 12:29 7.0M
Farnell-Schroff-A108..> 25-Jul-2014 12:27 2.8M
Farnell-Schroff-Main..> 25-Jul-2014 12:26 2.9M
Farnell-Schroff-mult..> 25-Jul-2014 12:26 2.9M
Farnell-Quick-Start-..> 25-Jul-2014 12:25 3.0M
Farnell-PiFace-Digit..> 25-Jul-2014 12:25 3.0M
Farnell-PicoScope-se..> 25-Jul-2014 12:24 3.0M
Farnell-Trust-Digita..> 25-Jul-2014 12:24 3.0M
Farnell-Jeu-multi-la..> 25-Jul-2014 12:23 3.0M
Farnell-PicoScope-42..> 25-Jul-2014 12:23 3.0M
Farnell-LD-WSECO16-P..> 25-Jul-2014 12:22 3.1M
Farnell-Circuit-Impr..> 25-Jul-2014 12:22 3.1M
Farnell-MULTICOMP-Ra..> 22-Jul-2014 12:57 5.9M
Farnell-RASPBERRY-PI..> 22-Jul-2014 12:35 5.9M
Farnell-Dremel-Exper..> 22-Jul-2014 12:34 1.6M
Farnell-STM32F103x8-..> 22-Jul-2014 12:33 1.6M
Farnell-BD6xxx-PDF.htm 22-Jul-2014 12:33 1.6M
Farnell-L78S-STMicro..> 22-Jul-2014 12:32 1.6M
Farnell-RaspiCam-Doc..> 22-Jul-2014 12:32 1.6M
Farnell-SB520-SB5100..> 22-Jul-2014 12:32 1.6M
Farnell-iServer-Micr..> 22-Jul-2014 12:32 1.6M
Farnell-LUMINARY-MIC..> 22-Jul-2014 12:31 3.6M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:31 2.4M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:30 4.6M
Farnell-CLASS 1-or-2..> 22-Jul-2014 12:30 4.7M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:29 4.8M
Farnell-Evaluating-t..> 22-Jul-2014 12:28 4.9M
Farnell-LM3S6952-Mic..> 22-Jul-2014 12:27 5.9M
Farnell-Keyboard-Mou..> 22-Jul-2014 12:27 5.9M
Farnell-0050375063-D..> 18-Jul-2014 17:03 2.5M
Farnell-Mini-Fit-Jr-..> 18-Jul-2014 17:03 2.5M
Farnell-43031-0002-M..> 18-Jul-2014 17:03 2.5M
Farnell-0433751001-D..> 18-Jul-2014 17:02 2.5M
Farnell-Cube-3D-Prin..> 18-Jul-2014 17:02 2.5M
Farnell-MTX-Compact-..> 18-Jul-2014 17:01 2.5M
Farnell-MTX-3250-MTX..> 18-Jul-2014 17:01 2.5M
Farnell-ATtiny26-L-A..> 18-Jul-2014 17:00 2.6M
Farnell-MCP3421-Micr..> 18-Jul-2014 17:00 1.2M
Farnell-LM19-Texas-I..> 18-Jul-2014 17:00 1.2M
Farnell-Data-Sheet-S..> 18-Jul-2014 17:00 1.2M
Farnell-LMH6518-Texa..> 18-Jul-2014 16:59 1.3M
Farnell-AD7719-Low-V..> 18-Jul-2014 16:59 1.4M
Farnell-DAC8143-Data..> 18-Jul-2014 16:59 1.5M
Farnell-BGA7124-400-..> 18-Jul-2014 16:59 1.5M
Farnell-SICK-OPTIC-E..> 18-Jul-2014 16:58 1.5M
Farnell-LT3757-Linea..> 18-Jul-2014 16:58 1.6M
Farnell-LT1961-Linea..> 18-Jul-2014 16:58 1.6M
Farnell-PIC18F2420-2..> 18-Jul-2014 16:57 2.5M
Farnell-DS3231-DS-PD..> 18-Jul-2014 16:57 2.5M
Farnell-RDS-80-PDF.htm 18-Jul-2014 16:57 1.3M
Farnell-AD8300-Data-..> 18-Jul-2014 16:56 1.3M
Farnell-LT6233-Linea..> 18-Jul-2014 16:56 1.3M
Farnell-MAX1365-MAX1..> 18-Jul-2014 16:56 1.4M
Farnell-XPSAF5130-PD..> 18-Jul-2014 16:56 1.4M
Farnell-DP83846A-DsP..> 18-Jul-2014 16:55 1.5M
Farnell-SL3ICS1002-1..> 16-Jul-2014 09:05 2.5M
Farnell-MCOC1-Farnel..> 16-Jul-2014 09:04 1.0M
Farnell-SL3S1203_121..> 16-Jul-2014 09:04 1.1M
Farnell-PN512-Full-N..> 16-Jul-2014 09:03 1.4M
Farnell-SL3S4011_402..> 16-Jul-2014 09:03 1.1M
Farnell-LPC408x-7x 3..> 16-Jul-2014 09:03 1.6M
Farnell-PCF8574-PCF8..> 16-Jul-2014 09:03 1.7M
Farnell-LPC81xM-32-b..> 16-Jul-2014 09:02 2.0M
Farnell-LPC1769-68-6..> 16-Jul-2014 09:02 1.9M
Farnell-Download-dat..> 16-Jul-2014 09:02 2.2M
Farnell-LPC3220-30-4..> 16-Jul-2014 09:02 2.2M
Farnell-LPC11U3x-32-..> 16-Jul-2014 09:01 2.4M
Farnell-Full-Datashe..> 15-Jul-2014 17:08 951K
Farnell-pmbta13_pmbt..> 15-Jul-2014 17:06 959K
Farnell-EE-SPX303N-4..> 15-Jul-2014 17:06 969K
Farnell-Datasheet-NX..> 15-Jul-2014 17:06 1.0M
Farnell-Datasheet-Fa..> 15-Jul-2014 17:05 1.0M
Farnell-MIDAS-un-tra..> 15-Jul-2014 17:05 1.0M
Farnell-SERIAL-TFT-M..> 15-Jul-2014 17:05 1.0M
Farnell-TMR-2-series..> 15-Jul-2014 16:48 787K
Farnell-DC-DC-Conver..> 15-Jul-2014 16:48 781K
Farnell-Full-Datashe..> 15-Jul-2014 16:47 803K
Farnell-TMLM-Series-..> 15-Jul-2014 16:47 810K
Farnell-TEL-5-Series..> 15-Jul-2014 16:47 814K
Farnell-TXL-series-t..> 15-Jul-2014 16:47 829K
Farnell-TEP-150WI-Se..> 15-Jul-2014 16:47 837K
Farnell-AC-DC-Power-..> 15-Jul-2014 16:47 845K
Farnell-TIS-Instruct..> 15-Jul-2014 16:47 845K
Farnell-TOS-tracopow..> 15-Jul-2014 16:47 852K
Farnell-TCL-DC-traco..> 15-Jul-2014 16:46 858K
Farnell-TIS-series-t..> 15-Jul-2014 16:46 875K
Farnell-TMR-2-Series..> 15-Jul-2014 16:46 897K
Farnell-TMR-3-WI-Ser..> 15-Jul-2014 16:46 939K
Farnell-TEN-8-WI-Ser..> 15-Jul-2014 16:46 939K
Farnell-SOURIAU-Cont..> 08-Jul-2014 19:04 3.0M
Farnell-T672-3000-Se..> 08-Jul-2014 18:59 2.0M
Farnell-tesa®pack63..> 08-Jul-2014 18:56 2.0M
Farnell-Encodeur-USB..> 08-Jul-2014 18:56 2.0M
Farnell-CC2530ZDK-Us..> 08-Jul-2014 18:55 2.1M
Farnell-2020-Manuel-..> 08-Jul-2014 18:55 2.1M
Farnell-Synchronous-..> 08-Jul-2014 18:54 2.1M
Farnell-Arithmetic-L..> 08-Jul-2014 18:54 2.1M
Farnell-NA555-NE555-..> 08-Jul-2014 18:53 2.2M
Farnell-4-Bit-Magnit..> 08-Jul-2014 18:53 2.2M
Farnell-LM555-Timer-..> 08-Jul-2014 18:53 2.2M
Farnell-L293d-Texas-..> 08-Jul-2014 18:53 2.2M
Farnell-SN54HC244-SN..> 08-Jul-2014 18:52 2.3M
Farnell-MAX232-MAX23..> 08-Jul-2014 18:52 2.3M
Farnell-High-precisi..> 08-Jul-2014 18:51 2.3M
Farnell-SMU-Instrume..> 08-Jul-2014 18:51 2.3M
Farnell-900-Series-B..> 08-Jul-2014 18:50 2.3M
Farnell-BA-Series-Oh..> 08-Jul-2014 18:50 2.3M
Farnell-UTS-Series-S..> 08-Jul-2014 18:49 2.5M
Farnell-270-Series-O..> 08-Jul-2014 18:49 2.3M
Farnell-UTS-Series-S..> 08-Jul-2014 18:49 2.8M
Farnell-Tiva-C-Serie..> 08-Jul-2014 18:49 2.6M
Farnell-UTO-Souriau-..> 08-Jul-2014 18:48 2.8M
Farnell-Clipper-Seri..> 08-Jul-2014 18:48 2.8M
Farnell-851-Series-P..> 08-Jul-2014 18:47 3.0M
Farnell-HIP4081A-Int..> 07-Jul-2014 19:47 1.0M
Farnell-ISL6251-ISL6..> 07-Jul-2014 19:47 1.1M
Farnell-DG411-DG412-..> 07-Jul-2014 19:47 1.0M
Farnell-3367-ARALDIT..> 07-Jul-2014 19:46 1.2M
Farnell-ICM7228-Inte..> 07-Jul-2014 19:46 1.1M
Farnell-Data-Sheet-K..> 07-Jul-2014 19:46 1.2M
Farnell-Silica-Gel-M..> 07-Jul-2014 19:46 1.2M
Farnell-TKC2-Dusters..> 07-Jul-2014 19:46 1.2M
Farnell-CRC-HANDCLEA..> 07-Jul-2014 19:46 1.2M
Farnell-760G-French-..> 07-Jul-2014 19:45 1.2M
Farnell-Decapant-KF-..> 07-Jul-2014 19:45 1.2M
Farnell-1734-ARALDIT..> 07-Jul-2014 19:45 1.2M
Farnell-Araldite-Fus..> 07-Jul-2014 19:45 1.2M
Farnell-fiche-de-don..> 07-Jul-2014 19:44 1.4M
Farnell-safety-data-..> 07-Jul-2014 19:44 1.4M
Farnell-A-4-Hardener..> 07-Jul-2014 19:44 1.4M
Farnell-CC-Debugger-..> 07-Jul-2014 19:44 1.5M
Farnell-SmartRF06-Ev..> 07-Jul-2014 19:43 1.6M
Farnell-CC2531-USB-H..> 07-Jul-2014 19:43 1.8M
Farnell-Alimentation..> 07-Jul-2014 19:43 1.8M
Farnell-BK889B-PONT-..> 07-Jul-2014 19:42 1.8M
Farnell-User-Guide-M..> 07-Jul-2014 19:41 2.0M
Farnell-SL59830-Inte..> 06-Jul-2014 10:11 1.0M
Farnell-ALF1210-PDF.htm 06-Jul-2014 10:06 4.0M
Farnell-AD7171-16-Bi..> 06-Jul-2014 10:06 1.0M
Farnell-Low-Noise-24..> 06-Jul-2014 10:05 1.0M
Farnell-ESCON-Featur..> 06-Jul-2014 10:05 938K
Farnell-74LCX573-Fai..> 06-Jul-2014 10:05 1.9M
Farnell-1N4148WS-Fai..> 06-Jul-2014 10:04 1.9M
Farnell-FAN6756-Fair..> 06-Jul-2014 10:04 850K
Farnell-Datasheet-Fa..> 06-Jul-2014 10:04 861K
Farnell-ES1F-ES1J-fi..> 06-Jul-2014 10:04 867K
Farnell-QRE1113-Fair..> 06-Jul-2014 10:03 879K
Farnell-2N7002DW-Fai..> 06-Jul-2014 10:03 886K
Farnell-FDC2512-Fair..> 06-Jul-2014 10:03 886K
Farnell-FDV301N-Digi..> 06-Jul-2014 10:03 886K
Farnell-S1A-Fairchil..> 06-Jul-2014 10:03 896K
Farnell-BAV99-Fairch..> 06-Jul-2014 10:03 896K
Farnell-74AC00-74ACT..> 06-Jul-2014 10:03 911K
Farnell-NaPiOn-Panas..> 06-Jul-2014 10:02 911K
Farnell-LQ-RELAYS-AL..> 06-Jul-2014 10:02 924K
Farnell-ev-relays-ae..> 06-Jul-2014 10:02 926K
Farnell-ESCON-Featur..> 06-Jul-2014 10:02 931K
Farnell-Amplifier-In..> 06-Jul-2014 10:02 940K
Farnell-Serial-File-..> 06-Jul-2014 10:02 941K
Farnell-Both-the-Del..> 06-Jul-2014 10:01 948K
Farnell-Videk-PDF.htm 06-Jul-2014 10:01 948K
Farnell-EPCOS-173438..> 04-Jul-2014 10:43 3.3M
Farnell-Sensorless-C..> 04-Jul-2014 10:42 3.3M
Farnell-197.31-KB-Te..> 04-Jul-2014 10:42 3.3M
Farnell-PIC12F609-61..> 04-Jul-2014 10:41 3.7M
Farnell-PADO-semi-au..> 04-Jul-2014 10:41 3.7M
Farnell-03-iec-runds..> 04-Jul-2014 10:40 3.7M
Farnell-ACC-Silicone..> 04-Jul-2014 10:40 3.7M
Farnell-Series-TDS10..> 04-Jul-2014 10:39 4.0M
Farnell-Q48-PDF.htm 23-Jun-2014 10:29 2.1M
Farnell-Panasonic-15..> 23-Jun-2014 10:29 2.1M
Farnell-BZX384-serie..> 23-Jun-2014 10:29 2.1M
Farnell-AN10361-Phil..> 23-Jun-2014 10:29 2.1M
Farnell-KSZ8851SNL-S..> 23-Jun-2014 10:28 2.1M
Farnell-BF545A-BF545..> 23-Jun-2014 10:28 2.1M
Farnell-PIC18F2455-2..> 23-Jun-2014 10:27 3.1M
Farnell-PMBT4403-PNP..> 23-Jun-2014 10:27 3.1M
Farnell-24AA024-24LC..> 23-Jun-2014 10:26 3.1M
Farnell-Leaded-Trans..> 23-Jun-2014 10:26 3.2M
Farnell-SSC7102-Micr..> 23-Jun-2014 10:25 3.2M
Farnell-Fastrack-Sup..> 23-Jun-2014 10:25 3.3M
Farnell-BC847DS-NXP-..> 23-Jun-2014 10:24 3.3M
Farnell-HI-70300-Sol..> 14-Jun-2014 18:27 2.4M
Farnell-Davum-TMC-PD..> 14-Jun-2014 18:27 2.4M
Farnell-Repartiteurs..> 14-Jun-2014 18:26 2.5M
Farnell-Documentatio..> 14-Jun-2014 18:26 2.5M
Farnell-Fiche-de-don..> 14-Jun-2014 18:26 2.5M
Farnell-SPLC780A1-16..> 14-Jun-2014 18:25 2.5M
Farnell-Construction..> 14-Jun-2014 18:25 2.5M
Farnell-Alimentation..> 14-Jun-2014 18:24 2.5M
Farnell-C.A-6150-C.A..> 14-Jun-2014 18:24 2.5M
Farnell-Fluke-1730-E..> 14-Jun-2014 18:23 2.5M
Farnell-Ponts-RLC-po..> 14-Jun-2014 18:23 3.3M
Farnell-Serie-Standa..> 14-Jun-2014 18:23 3.3M
Farnell-FDS-ITW-Spra..> 14-Jun-2014 18:22 3.3M
Farnell-HFE1600-Data..> 14-Jun-2014 18:22 3.3M
Farnell-TDK-Lambda-H..> 14-Jun-2014 18:21 3.3M
Farnell-HC49-4H-Crys..> 14-Jun-2014 18:20 3.3M
Farnell-Avvertenze-e..> 14-Jun-2014 18:20 3.3M
Farnell-Ceramic-tran..> 14-Jun-2014 18:19 3.4M
Farnell-ADL6507-PDF.htm 14-Jun-2014 18:19 3.4M
Farnell-PMEG4002EL-N..> 14-Jun-2014 18:18 3.4M
Farnell-Midas-Active..> 14-Jun-2014 18:17 3.4M
Farnell-Molex-83421-..> 14-Jun-2014 18:17 3.4M
Farnell-Molex-COMMER..> 14-Jun-2014 18:16 3.4M
Farnell-10TPB47M-End..> 14-Jun-2014 18:16 3.4M
Farnell-U2270B-PDF.htm 14-Jun-2014 18:15 3.4M
Farnell-SVPE-series-..> 14-Jun-2014 18:15 2.0M
Farnell-F28069-Picco..> 14-Jun-2014 18:14 2.0M
Farnell-Termometros-..> 14-Jun-2014 18:14 2.0M
Farnell-Cordless-dri..> 14-Jun-2014 18:13 2.0M
Farnell-Battery-GBA-..> 14-Jun-2014 18:13 2.0M
Farnell-CD4536B-Type..> 14-Jun-2014 18:13 2.0M
Farnell-0430300011-D..> 14-Jun-2014 18:13 2.0M
Farnell-Mistral-PDF.htm 14-Jun-2014 18:12 2.1M
Farnell-Connectors-N..> 14-Jun-2014 18:12 2.1M
Farnell-XPS-AC-Octop..> 14-Jun-2014 18:11 2.1M
Farnell-Midas-MCCOG4..> 14-Jun-2014 18:11 2.1M
Farnell-V4N-PDF.htm 14-Jun-2014 18:11 2.1M
Farnell-Signal-PCB-R..> 14-Jun-2014 18:11 2.1M
Farnell-PIC24FJ256GB..> 14-Jun-2014 09:51 2.4M
Farnell-DC-Fan-type-..> 14-Jun-2014 09:51 1.8M
Farnell-12mm-Size-In..> 14-Jun-2014 09:50 2.4M
Farnell-10BQ060-PDF.htm 14-Jun-2014 09:50 2.4M
Farnell-An-Improved-..> 14-Jun-2014 09:49 2.5M
Farnell-ATmega640-VA..> 14-Jun-2014 09:49 2.5M
Farnell-LME49725-Pow..> 14-Jun-2014 09:49 2.5M
Farnell-Produit-3430..> 14-Jun-2014 09:48 2.5M
Farnell-USB-Buccanee..> 14-Jun-2014 09:48 2.5M
Farnell-DC-Fan-type-..> 14-Jun-2014 09:48 2.5M
Farnell-Fiche-de-don..> 14-Jun-2014 09:47 2.5M
Farnell-Nilï¬-sk-E-..> 14-Jun-2014 09:47 2.5M
Farnell-MX670-MX675-..> 14-Jun-2014 09:46 2.5M
Farnell-Tektronix-AC..> 13-Jun-2014 18:44 1.5M
Farnell-PMBT3906-PNP..> 13-Jun-2014 18:44 1.5M
Farnell-PESD5V0F1BL-..> 13-Jun-2014 18:43 1.5M
Farnell-PMEG4010CEH-..> 13-Jun-2014 18:43 1.6M
Farnell-PESD9X5.0L-P..> 13-Jun-2014 18:43 1.6M
Farnell-BTA204-800C-..> 13-Jun-2014 18:42 1.6M
Farnell-BYV29F-600-N..> 13-Jun-2014 18:42 1.6M
Farnell-Low-cost-Enc..> 13-Jun-2014 18:42 1.7M
Farnell-BC846DS-NXP-..> 13-Jun-2014 18:42 1.6M
Farnell-IP4252CZ16-8..> 13-Jun-2014 18:41 1.7M
Farnell-BUJD203AX-NX..> 13-Jun-2014 18:41 1.7M
Farnell-Download-dat..> 13-Jun-2014 18:40 1.8M
Farnell-BT151-650R-N..> 13-Jun-2014 18:40 1.7M
Farnell-OXPCIE958-FB..> 13-Jun-2014 18:40 1.8M
Farnell-ATtiny26-L-A..> 13-Jun-2014 18:40 1.8M
Farnell-Microchip-MC..> 13-Jun-2014 18:27 1.8M
Farnell-Pompes-Charg..> 24-Apr-2014 20:23 3.3M
Farnell-Alimentation..> 01-Apr-2014 07:42 3.4M
Farnell-C.A 8332B-C...> 01-Apr-2014 07:40 3.4M
Farnell-ALF1225-12-V..> 01-Apr-2014 07:40 3.4M
Farnell-CS5532-34-BS..> 01-Apr-2014 07:39 3.5M
Farnell-ALF2412-24-V..> 01-Apr-2014 07:39 3.4M
Sefram-GUIDE_SIMPLIF..> 29-Mar-2014 11:46 422K
Sefram-CAT_ENREGISTR..> 29-Mar-2014 11:46 461K
Sefram-SP270.pdf-PDF..> 29-Mar-2014 11:46 464K
Sefram-7866HD.pdf-PD..> 29-Mar-2014 11:46 472K
Sefram-GUIDE_SIMPLIF..> 29-Mar-2014 11:46 481K
Sefram-CAT_MESUREURS..> 29-Mar-2014 11:46 435K
Sefram-GUIDE_SIMPLIF..> 29-Mar-2014 11:46 442K
Farnell-Portable-Ana..> 29-Mar-2014 11:16 2.8M
Farnell-CC2560-Bluet..> 29-Mar-2014 11:14 2.8M
Farnell-Ferric-Chlor..> 29-Mar-2014 11:14 2.8M
Farnell-MCF532x-7x-E..> 29-Mar-2014 11:14 2.8M
Farnell-A-True-Syste..> 29-Mar-2014 11:13 3.3M
Farnell-ELMA-PDF.htm 29-Mar-2014 11:13 3.3M
Farnell-SMBJ-Transil..> 29-Mar-2014 11:12 3.3M
Farnell-6517b-Electr..> 29-Mar-2014 11:12 3.3M
Farnell-Amplificateu..> 29-Mar-2014 11:11 3.3M
Farnell-ir1150s_fr.p..> 29-Mar-2014 11:11 3.3M
Farnell-De-la-puissa..> 29-Mar-2014 11:10 3.3M
Farnell-BK2650A-BK26..> 29-Mar-2014 11:10 3.3M
Farnell-Lubrifiant-a..> 26-Mar-2014 18:00 2.7M
Farnell-Circuit-Note..> 26-Mar-2014 18:00 2.8M
Farnell-Circuit-Note..> 26-Mar-2014 18:00 2.8M
Farnell-Current-Tran..> 26-Mar-2014 17:59 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:59 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:58 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:58 2.7M
Farnell-Supercapacit..> 26-Mar-2014 17:57 2.7M
Farnell-GALVA-MAT-Re..> 26-Mar-2014 17:57 2.7M
Farnell-GALVA-A-FROI..> 26-Mar-2014 17:56 2.7M
Farnell-1907-2006-PD..> 26-Mar-2014 17:56 2.7M
Farnell-ARALDITE-CW-..> 26-Mar-2014 17:56 2.7M
Farnell-06-6544-8-PD..> 26-Mar-2014 17:56 2.7M
Farnell-Miniature-Ci..> 26-Mar-2014 17:55 2.8M
Farnell-ARADUR-HY-13..> 26-Mar-2014 17:55 2.8M
Farnell-LOCTITE-3463..> 25-Mar-2014 08:19 3.0M
Farnell-LCW-CQ7P.CC-..> 25-Mar-2014 08:19 3.2M
Farnell-ATtiny20-PDF..> 25-Mar-2014 08:19 3.6M
Farnell-3M-VolitionT..> 25-Mar-2014 08:18 3.3M
Farnell-EMC1182-PDF.htm 25-Mar-2014 08:17 3.0M
Farnell-MC3510-PDF.htm 25-Mar-2014 08:17 3.0M
Farnell-Directive-re..> 25-Mar-2014 08:16 3.0M
Farnell-Loctite3455-..> 25-Mar-2014 08:16 3.0M
Farnell-LOCTITE-542-..> 25-Mar-2014 08:15 3.0M
Farnell-5910-PDF.htm 25-Mar-2014 08:15 3.0M
Farnell-china_rohs_o..> 21-Mar-2014 10:04 3.9M
Farnell-Cles-electro..> 21-Mar-2014 08:13 3.9M
Farnell-ARALDITE-201..> 21-Mar-2014 08:12 3.7M
Farnell-Premier-Farn..> 21-Mar-2014 08:11 3.8M
Farnell-celpac-SUL84..> 21-Mar-2014 08:11 3.8M
Farnell-S-TRI-SWT860..> 21-Mar-2014 08:11 3.8M
Farnell-3M-Polyimide..> 21-Mar-2014 08:09 3.9M
Farnell-Strangkuhlko..> 21-Mar-2014 08:09 3.9M
Farnell-Reglement-RE..> 21-Mar-2014 08:08 3.9M
Farnell-techfirst_se..> 21-Mar-2014 08:08 3.9M
Farnell-Septembre-20..> 20-Mar-2014 17:46 3.7M
Farnell-Telemetres-l..> 20-Mar-2014 17:46 3.7M
Farnell-Multi-Functi..> 20-Mar-2014 17:38 3.0M
Farnell-testo-470-Fo..> 20-Mar-2014 17:38 3.0M
Farnell-Novembre-201..> 20-Mar-2014 17:38 3.3M
Farnell-testo-205-20..> 20-Mar-2014 17:37 3.0M
Farnell-Panasonic-Ra..> 20-Mar-2014 17:37 2.6M
Farnell-Panasonic-Ne..> 20-Mar-2014 17:36 2.6M
Farnell-Panasonic-EC..> 20-Mar-2014 17:36 2.6M
Farnell-Panasonic-Id..> 20-Mar-2014 17:35 2.6M
Farnell-cree-Xlamp-X..> 20-Mar-2014 17:35 2.7M
Farnell-cree-Xlamp-X..> 20-Mar-2014 17:34 2.8M
Farnell-ADSP-21362-A..> 20-Mar-2014 17:34 2.8M
Farnell-AD524-PDF.htm 20-Mar-2014 17:33 2.8M
Farnell-MPXV7002-Rev..> 20-Mar-2014 17:33 2.8M
Farnell-cree-Xlamp-m..> 20-Mar-2014 17:32 2.9M
Farnell-cree-Xlamp-m..> 20-Mar-2014 17:32 2.9M
Farnell-50A-High-Pow..> 20-Mar-2014 17:31 2.9M
Farnell-cree-Xlamp-X..> 20-Mar-2014 17:31 2.9M
Farnell-Series-2600B..> 20-Mar-2014 17:30 3.0M
Farnell-ECO-Series-T..> 20-Mar-2014 08:14 2.5M
Farnell-PDTA143X-ser..> 20-Mar-2014 08:12 2.6M
Farnell-Panasonic-TS..> 20-Mar-2014 08:12 2.6M
Farnell-Radial-Lead-..> 20-Mar-2014 08:12 2.6M
Farnell-GN-RELAYS-AG..> 20-Mar-2014 08:11 2.6M
Farnell-Panasonic-Y3..> 20-Mar-2014 08:11 2.6M
Farnell-Panasonic-EZ..> 20-Mar-2014 08:10 2.6M
Farnell-ATMEL-8-bit-..> 19-Mar-2014 18:04 2.1M
Farnell-USB1T11A-PDF..> 19-Mar-2014 18:03 2.1M
Farnell-OSLON-SSL-Ce..> 19-Mar-2014 18:03 2.1M
Farnell-Atmel-ATmega..> 19-Mar-2014 18:03 2.2M
Farnell-PBSS5160T-60..> 19-Mar-2014 18:03 2.1M
Farnell-MICROCHIP-PI..> 19-Mar-2014 18:02 2.5M
Farnell-Ed.081002-DA..> 19-Mar-2014 18:02 2.5M
Farnell-Instructions..> 19-Mar-2014 18:01 2.5M
Farnell-Serie-PicoSc..> 19-Mar-2014 18:01 2.5M
Farnell-F42202-PDF.htm 19-Mar-2014 18:00 2.5M
Farnell-propose-plus..> 11-Mar-2014 08:19 2.8M
Farnell-Haute-vitess..> 11-Mar-2014 08:17 2.4M
Farnell-Controle-de-..> 11-Mar-2014 08:16 2.8M
Farnell-NXP-TEA1703T..> 11-Mar-2014 08:15 2.8M
Farnell-XPS-MC16-XPS..> 11-Mar-2014 08:15 2.8M
Farnell-MC21605-PDF.htm 11-Mar-2014 08:14 2.8M
Farnell-WetTantalum-..> 11-Mar-2014 08:14 2.8M
Farnell-ES2333-PDF.htm 11-Mar-2014 08:14 2.8M
Farnell-SB175-Connec..> 11-Mar-2014 08:14 2.8M
Farnell-Cannon-ZD-PD..> 11-Mar-2014 08:13 2.8M
Farnell-YAGEO-DATA-S..> 11-Mar-2014 08:13 2.8M
Farnell-ATMEL-8-bit-..> 11-Mar-2014 07:55 2.1M
Farnell-NXP-PCA9555 ..> 11-Mar-2014 07:54 2.2M
Farnell-MICREL-KSZ88..> 11-Mar-2014 07:54 2.2M
Farnell-Microship-PI..> 11-Mar-2014 07:53 2.2M
Farnell-EPCOS-Sample..> 11-Mar-2014 07:53 2.2M
Farnell-NXP-BT136-60..> 11-Mar-2014 07:52 2.3M
Farnell-NTE_SEMICOND..> 11-Mar-2014 07:52 2.3M
Farnell-L-efficacite..> 11-Mar-2014 07:52 2.3M
Farnell-LUXEON-Guide..> 11-Mar-2014 07:52 2.3M
Farnell-Realiser-un-..> 11-Mar-2014 07:51 2.3M
Farnell-SOT-23-Multi..> 11-Mar-2014 07:51 2.3M
Farnell-ZigBee-ou-le..> 11-Mar-2014 07:50 2.4M
Farnell-Les-derniers..> 11-Mar-2014 07:50 2.3M
Farnell-Conception-d..> 11-Mar-2014 07:49 2.4M
Farnell-Puissance-ut..> 11-Mar-2014 07:49 2.4M
Farnell-MOLEX-43160-..> 10-Mar-2014 17:21 1.9M
Farnell-MOLEX-87439-..> 10-Mar-2014 17:21 1.9M
Farnell-MOLEX-43020-..> 10-Mar-2014 17:21 1.9M
Farnell-NXP-PBSS9110..> 10-Mar-2014 17:21 1.9M
Farnell-TEKTRONIX-DP..> 10-Mar-2014 17:20 2.0M
Farnell-uC-OS-III-Br..> 10-Mar-2014 17:20 2.0M
Farnell-CIRRUS-LOGIC..> 10-Mar-2014 17:20 2.1M
Farnell-NXP-PSMN7R0-..> 10-Mar-2014 17:19 2.1M
Farnell-MOLEX-39-00-..> 10-Mar-2014 17:19 1.9M
Farnell-manual-bus-p..> 10-Mar-2014 16:29 1.9M
Farnell-Molex-Crimp-..> 10-Mar-2014 16:27 1.7M
Farnell-The-essentia..> 10-Mar-2014 16:27 1.7M
Farnell-OMRON-Master..> 10-Mar-2014 16:26 1.8M
Farnell-Proskit-SS-3..> 10-Mar-2014 16:26 1.8M
Farnell-BYV79E-serie..> 10-Mar-2014 16:19 1.6M
Farnell-NXP-74VHC126..> 10-Mar-2014 16:17 1.6M
Farnell-NXP-PSMN1R7-..> 10-Mar-2014 16:17 1.6M
Farnell-FICHE-DE-DON..> 10-Mar-2014 16:17 1.6M
Farnell-HUNTSMAN-Adv..> 10-Mar-2014 16:17 1.7M
Farnell-NXP-PMBFJ620..> 10-Mar-2014 16:16 1.7M
Farnell-Pico-Spox-Wi..> 10-Mar-2014 16:16 1.7MRev. 8207L-AT42-05/12 Atmel QTouch Library User Guide Supports QTouch® and QMatrix® acquisition for Keys, Sliders and Rotors 2 8207L-AT42-05/12 Rev. 8207L-AT42-05/12 Table of Contents TABLE OF CONTENTS ..............................................................................................................................2 1 PREFACE..............................................................................................................................................8 2 INTRODUCTION .................................................................................................................................9 3 OVERVIEW ........................................................................................................................................10 4 ABBREVIATIONS AND DEFINITIONS.........................................................................................11 4.1 DEFINITIONS...................................................................................................................................11 5 GENERIC QTOUCH LIBRARIES...................................................................................................12 5.1 INTRODUCTION...............................................................................................................................12 5.2 ACQUISITION METHODS .................................................................................................................13 5.2.1 QTouch acquisition method...................................................................................................13 5.2.1.1 Sensor schematics for a QTouch acquisition method design............................................................ 14 5.2.2 QMatrix acquisition method ..................................................................................................14 5.2.3 Sensor schematics for a QMatrix acquisition method design................................................15 5.3 GLOBAL SETTINGS COMMON TO ALL SENSORS OF A SPECIFIC ACQUISITION METHOD......................15 5.3.1 Recalibration Threshold ........................................................................................................16 5.3.2 Detect Integration..................................................................................................................16 5.3.3 Drift Hold Time .....................................................................................................................16 5.3.4 Maximum ON Duration .........................................................................................................17 5.3.5 Positive / Negative Drift ........................................................................................................17 5.3.6 Positive Recalibration Delay .................................................................................................18 5.4 SENSOR SPECIFIC SETTINGS ............................................................................................................18 5.4.1 Detect threshold.....................................................................................................................18 5.4.2 Hysteresis...............................................................................................................................18 5.4.3 Position Resolution................................................................................................................19 5.4.4 Position Hysteresis ................................................................................................................19 5.4.5 Adjacent Key Suppression (AKS)...........................................................................................20 5.5 USING THE SENSORS.......................................................................................................................20 5.5.1 Avoiding Cross-talk ...............................................................................................................20 5.5.2 Multiple measurements..........................................................................................................20 5.5.3 Guard Channel ......................................................................................................................21 5.6 QTOUCH API AND USAGE..............................................................................................................22 5.6.1 QTouch Library API..............................................................................................................22 5.6.2 touch_api.h - public header file.............................................................................................22 5.6.3 Type Definitions and enumerations used in the library.........................................................22 5.6.3.1 Typedefs........................................................................................................................................... 22 5.6.3.2 Enumerations ................................................................................................................................... 22 5.6.3.2.1 sensor_type_t.............................................................................................................................. 22 5.6.3.2.2 aks_group_t................................................................................................................................ 23 5.6.3.2.3 channel_t.................................................................................................................................... 23 5.6.3.2.4 hysteresis_t................................................................................................................................. 23 5.6.3.2.5 resolution_t................................................................................................................................. 24 5.6.3.2.6 recal_threshold_t........................................................................................................................ 24 5.6.4 Data structures......................................................................................................................25 5.6.4.1 qt_touch_status_t.............................................................................................................................. 25 5.6.4.2 qt_touch_lib_config_data_t.............................................................................................................. 25 5.6.4.3 qt_touch_lib_measure_data_t........................................................................................................... 26 5.6.4.4 qt_burst_lengths............................................................................................................................... 26 5.6.4.5 tag_sensor_t ..................................................................................................................................... 27 5.6.4.6 qt_lib_siginfo_t ................................................................................................................................ 27 5.6.5 Public Functions....................................................................................................................283 5.6.5.1 qt_set_parameters............................................................................................................................. 28 5.6.5.2 qt_enable_key .................................................................................................................................. 29 5.6.5.3 qt_enable_rotor ................................................................................................................................ 29 5.6.5.4 qt_enable_slider ............................................................................................................................... 30 5.6.5.5 qt_init_sensing ................................................................................................................................. 30 5.6.5.6 qt_measure_sensors.......................................................................................................................... 31 5.6.5.7 qt_calibrate_sensing......................................................................................................................... 31 5.6.5.8 qt_reset_sensing ............................................................................................................................... 32 5.6.5.9 qt_get_sensor_delta.......................................................................................................................... 32 5.6.5.10 qt_get_library_sig ........................................................................................................................ 32 5.6.6 Sequence of Operations and Using the API...........................................................................33 5.6.6.1 Channel Numbering ......................................................................................................................... 33 5.6.6.1.1 Channel numbering when using QTouch acquisition method .................................................... 33 5.6.6.1.2 Channel numbering when using QMatrix acquisition method ................................................... 39 5.6.6.2 Sensor Numbering............................................................................................................................ 41 5.6.6.3 Filtering Signal Measurements......................................................................................................... 42 5.6.6.4 Allocating unused Port Pins for User Application............................................................................ 43 5.6.6.5 Disabling and Enabling of Pull-up for AVR devices........................................................................ 44 5.6.7 Constraints.............................................................................................................................44 5.6.7.1 QTouch acquisition method constraints........................................................................................... 44 5.6.7.2 QMatrix acquisition method constraints........................................................................................... 45 5.6.7.3 Design Guidelines for QMatrix acquisition method systems ........................................................... 46 5.6.8 Frequency of operation (Vs) Charge cycle/dwell cycle times: ..............................................46 5.6.9 Interrupts...............................................................................................................................47 5.6.10 Integrating QTouch libraries in your application .................................................................48 5.6.10.1 Directory structure of the library files.......................................................................................... 48 5.6.10.2 Integrating QTouch acquisition method libraries in your application.......................................... 50 5.6.10.2.1 Example for 8bit AVR ............................................................................................................. 52 5.6.10.2.2 Example for ATSAM ............................................................................................................... 54 5.6.10.2.3 Checklist of items for integrating QTouch acquisition method libraries.................................. 55 5.6.10.3 Integrating QMatrix acquisition method libraries in your application ......................................... 55 5.6.10.3.1 Example for 8bit AVR ............................................................................................................. 55 5.6.10.3.2 Example for 32bit AVR ........................................................................................................... 62 5.6.10.3.3 Checklist of items for integrating QMatrix Capacitive sensing libraries.................................. 66 5.6.10.4 Common checklist items.............................................................................................................. 66 5.6.10.4.1 Configuring the stack size for the application .......................................................................... 66 5.6.11 Example project files .............................................................................................................67 5.6.11.1 Using the Sample projects ........................................................................................................... 68 5.6.11.2 Example applications for QTouch acquisition method libraries.................................................. 68 5.6.11.2.1 Selecting the right configuration .............................................................................................. 68 5.6.11.2.2 Changing the settings to match your device ............................................................................. 69 5.6.11.2.3 Changing the library configuration parameters ........................................................................ 70 5.6.11.2.4 Using the example projects ...................................................................................................... 72 5.6.11.3 Example applications for QMatrix acquisition method libraries.................................................. 73 5.6.11.3.1 Selecting the right configuration .............................................................................................. 73 5.6.11.3.2 Changing the library configuration parameters ........................................................................ 74 5.6.11.3.3 Using the example projects ...................................................................................................... 75 5.6.11.4 Adjusting the Stack size when using IAR IDE ............................................................................ 76 5.6.11.5 Optimization levels...................................................................................................................... 76 5.6.11.6 Debug Support in Example applications...................................................................................... 77 5.6.11.6.1 Debug Support in the sample applications for EVK2080 and QT600 boards .......................... 77 5.6.11.6.2 How to turn on the debug option.............................................................................................. 77 5.6.11.6.3 Debug Interface if USB Bridge board is not available ............................................................. 78 5.7 LIBRARY VARIANTS .......................................................................................................................79 5.7.1 QTouch Acquisition method library variants.........................................................................79 5.7.1.1 Introduction...................................................................................................................................... 79 5.7.1.2 Support for different compiler tool chains........................................................................................ 79 5.7.1.3 QTouch Acquisition method library naming conventions................................................................ 79 5.7.1.3.1 Naming convention for libraries to be used with GCC tool chain.............................................. 79 5.7.1.3.2 Naming convention for libraries to be used with IAR Embedded Workbench........................... 80 5.7.1.4 QTouch acquisition method library variants .................................................................................... 804 8207L-AT42-05/12 5.7.1.5 Port combinations supported for SNS and SNSK pin configurations............................................... 81 5.7.1.5.1 Tips on pin assignments for the sensor design using one pair of SNS/SNSK ports ................... 81 5.7.1.5.2 Port combinations supported for two port pair SNS and SNSK pin configurations................... 83 5.7.1.6 Sample applications and Memory requirements for QTouch acquisition method libraries.............. 84 5.7.2 QMatrix acquisition method library variants........................................................................84 5.7.2.1 Introduction...................................................................................................................................... 84 5.7.2.2 Support for different compiler tool chains........................................................................................ 84 5.7.2.3 QMatrix Acquisition method library naming conventions............................................................... 84 5.7.2.4 QMatrix acquisition method library variants.................................................................................... 87 5.7.2.4.1 Devices supported for QMatrix Acquisition............................................................................... 87 5.8 PIN CONFIGURATION FOR QTOUCH LIBRARIES .............................................................................87 5.8.1 Pin Configuration for QTouch Acquisition Method ..............................................................87 5.8.1.1 Rules for configurable SNS-SNSK Mask Generation...................................................................... 88 5.8.1.1.1 Example for 8 channel interport mask Calculation with one port pair ....................................... 89 5.8.1.1.2 Example for 8 channel intraport mask Calculation with two port pairs...................................... 90 5.8.1.1.3 Example for 12 channel intraport-interport mask Calculation with two port pairs.................... 91 5.8.1.1.4 Example for 16 channel intreport-interport mask Calculation with two port pairs.................... 92 5.8.1.2 How to Use QTouch Studio For Pin Configurability ....................................................................... 93 5.8.2 Pin Configuration for QMatrix Acquisition Method............................................................101 5.8.2.1 Configuration Rules: ...................................................................................................................... 101 5.8.2.2 How to use QTouch Studio for Pin Configurability:...................................................................... 102 5.9 MISRA COMPLIANCE REPORT.....................................................................................................109 5.9.1 What is covered ...................................................................................................................110 5.9.2 Target Environment.............................................................................................................110 5.9.3 Deviations from MISRA C Standards..................................................................................110 5.9.3.1 QTouch acquisition method libraries ............................................................................................. 110 5.9.3.2 QMatrix acquisition method libraries............................................................................................. 111 5.10 KNOWN ISSUES.............................................................................................................................111 5.11 CHECKLIST...................................................................................................................................112 6 DEVICE SPECIFIC LIBRARIES ...................................................................................................113 6.1 INTRODUCTION.............................................................................................................................113 6.2 DEVICES SUPPORTED ....................................................................................................................113 6.3 QTOUCH LIBRARY FOR AT32UC3L DEVICES ..............................................................................113 6.3.1 Salient Features of QTouch Library for UC3L....................................................................113 6.3.1.1 QMatrix method sensor.................................................................................................................. 113 6.3.1.2 QTouch method sensor................................................................................................................... 113 6.3.1.3 Autonomous QTouch sensor.......................................................................................................... 114 6.3.1.4 Additional Features........................................................................................................................ 114 6.3.2 Device variants supported for UC3L...................................................................................114 6.3.3 Development tool support for UC3L ...................................................................................114 Table 8 Development tool support for UC3L QTouch Library ................................................................... 114 6.3.4 Overview of QTouch Library API for UC3L .......................................................................115 Figure 35 Overview diagram of QTouch Library for UC3L ....................................................................... 115 6.3.5 Acquisition method support for UC3L.................................................................................116 Table 9 Acquisition method specific API.................................................................................................... 116 6.3.6 API State machine for UC3L ...............................................................................................116 Figure 36 State Diagram of QTouch Library for UC3L .............................................................................. 117 6.3.7 QMatrix method sensor operation for UC3L.......................................................................117 6.3.7.1 QMatrix method pin selection for UC3L........................................................................................ 117 Table 10 QMatrix Resistive drive pin option .............................................................................................. 118 6.3.7.2 QMatrix method Schematic for UC3L........................................................................................... 118 6.3.7.2.1 Internal Discharge mode .......................................................................................................... 118 6.3.7.2.2 External Discharge mode ......................................................................................................... 119 6.3.7.2.3 SMP Discharge Mode .............................................................................................................. 119 6.3.7.2.4 VDIVEN Voltage Divider Enable option................................................................................. 119 6.3.7.2.5 SYNC pin option...................................................................................................................... 119 Figure 37 QMatrix method schematic ......................................................................................................... 120 6.3.7.3 QMatrix method hardware resource requirement for UC3L .......................................................... 121 6.3.7.4 QMatrix method Channel and Sensor numbering for UC3L.......................................................... 1215 Figure 38 QMatrix channel numbering for UC3L....................................................................................... 121 6.3.7.5 QMatrix method API Flow for UC3L............................................................................................ 121 Figure 39 QMatrix API Flow diagram for UC3L........................................................................................ 122 6.3.7.6 QMatrix method Disable and Re-enable Sensor for UC3L............................................................ 124 6.3.8 QTouch Group A/B method sensor operation for UC3L .....................................................124 6.3.8.1 QTouch Group A/B method pin selection for UC3L...................................................................... 124 Table 11 QTouch Resistive drive pin option ............................................................................................... 125 6.3.8.2 QTouch Group A/B method Schematic for UC3L ......................................................................... 125 6.3.8.2.1 Resistive Drive option.............................................................................................................. 125 6.3.8.2.2 SYNC pin option...................................................................................................................... 125 Figure 40 QTouch Group A/B and Autonomous QTouch schematic arrangement ..................................... 126 6.3.8.3 QTouch Group A/B method hardware resource requirement for UC3L ........................................ 126 6.3.8.4 QTouch Group A/B method Channel and Sensor numbering for UC3L........................................ 127 Figure 41 QTouch method Channel/Sensor numbering............................................................................... 127 Figure 42 QTouch method Channel/Sensor numbering when Group A and B are used together................ 127 6.3.8.5 QTouch Group A/B method API Flow for UC3L.......................................................................... 128 Figure 43 QTouch method API Flow diagram ............................................................................................ 129 6.3.8.6 QTouch Group A/B method Disable and Re-enable Sensor for UC3L.......................................... 130 6.3.9 Autonomous QTouch sensor operation for UC3L ...............................................................130 6.3.9.1 Autonomous QTouch Sensor pin selection for UC3L.................................................................... 130 6.3.9.2 Autonomous QTouch sensor Schematic for UC3L........................................................................ 130 6.3.9.3 Autonomous QTouch method hardware resource requirement for UC3L...................................... 130 Table 12 Sleep mode support for Autonomous QTouch ............................................................................. 130 6.3.9.4 Autonomous QTouch Sensor API Flow for UC3L ........................................................................ 131 Figure 44 Autonomous QTouch API Flow diagram.................................................................................... 131 6.3.9.5 Autonomous QTouch method Enable and Disable Sensor for UC3L ............................................ 131 6.3.10 Raw acquisition mode support for UC3L ............................................................................132 Figure 45 Raw acquisition mode API Flow diagram................................................................................... 132 6.3.11 Library Configuration parameters for UC3L ......................................................................133 Table 13 QTouch Library for UC3L Configuration parameters.................................................................. 133 6.3.12 Example projects for QTouch Library for UC3L.................................................................134 6.3.12.1 Example Project usage............................................................................................................... 134 Figure 46 GNU Example project usage with AVR32 Studio ...................................................................... 134 Figure 47 IAR Example project usage with IAR Embedded Workbench for AVR32................................. 134 6.3.12.2 QMatrix Example Project .......................................................................................................... 135 6.3.12.3 QTouch Group A Example Project............................................................................................ 135 6.3.12.4 Autonomous QTouch Example Project ..................................................................................... 135 6.3.13 Code and Data Memory requirements for UC3L ................................................................136 6.3.13.1 QMatrix method memory requirement ...................................................................................... 136 Table 14 Typical Code and Data memory for Standalone QMatrix operation ........................................... 136 6.3.13.2 QTouch Group A/B method memory requirement .................................................................... 136 Table 15 Typical Code and Data memory for Standalone QTouch Group A/B operation .......................... 137 6.3.13.3 Autonomous QTouch memory requirement .............................................................................. 137 Table 16 Minimum Code and Data for Standalone Autonomous QTouch sensor....................................... 137 6.3.14 Public header files of QTouch Library for UC3L................................................................137 6.3.15 Type Definitions and enumerations used in the library.......................................................137 6.3.15.1 Typedefs .................................................................................................................................... 137 6.3.15.1.1 touch_acq_status_t ................................................................................................................. 138 6.3.15.1.2 touch_qt_grp_t ....................................................................................................................... 138 6.3.15.2 Enumerations............................................................................................................................. 138 6.3.15.2.1 touch_ret_t.............................................................................................................................. 139 6.3.15.2.2 touch_lib_state_t .................................................................................................................... 139 6.3.15.2.3 touch_acq_mode_t ................................................................................................................. 140 6.3.15.2.4 sensor_type_t.......................................................................................................................... 140 6.3.15.2.5 aks_group_t............................................................................................................................ 140 6.3.15.2.6 hysteresis_t............................................................................................................................. 140 6.3.15.2.7 recal_threshold_t.................................................................................................................... 141 6.3.15.2.8 resolution_t............................................................................................................................. 141 6.3.15.2.9 at_status_change_t ................................................................................................................. 142 6.3.15.2.10 x_pin_options_t.................................................................................................................... 142 6.3.15.2.11 y_pin_options_t.................................................................................................................... 1426 8207L-AT42-05/12 6.3.15.2.12 qt_pin_options_t................................................................................................................... 142 6.3.15.2.13 general_pin_options_t .......................................................................................................... 142 6.3.16 Data structures....................................................................................................................143 6.3.16.1 sensor_t...................................................................................................................................... 143 6.3.16.2 touch_global_param_t ............................................................................................................... 143 6.3.16.3 touch_filter_data_t..................................................................................................................... 144 6.3.16.4 touch_measure_data_t ............................................................................................................... 144 6.3.16.5 touch_qm_param_t .................................................................................................................... 144 6.3.16.6 touch_at_param_t ...................................................................................................................... 145 6.3.16.7 touch_qt_param_t ...................................................................................................................... 146 6.3.16.8 touch_at_status .......................................................................................................................... 146 6.3.16.9 touch_qm_dma_t ....................................................................................................................... 146 6.3.16.10 touch_qm_pin_t......................................................................................................................... 146 6.3.16.11 touch_at_pin_t ........................................................................................................................... 147 6.3.16.12 touch_qt_pin_t........................................................................................................................... 147 6.3.16.13 touch_qm_reg_t ......................................................................................................................... 148 6.3.16.14 touch_at_reg_t ........................................................................................................................... 149 6.3.16.15 touch_qt_reg_t........................................................................................................................... 149 6.3.16.16 touch_qm_config_t.................................................................................................................... 149 6.3.16.17 touch_at_config_t ...................................................................................................................... 150 6.3.16.18 touch_qt_config_t...................................................................................................................... 151 6.3.16.19 touch_general_config_t.............................................................................................................. 151 6.3.16.20 touch_config_t ........................................................................................................................... 152 6.3.16.21 touch_info_t............................................................................................................................... 152 6.3.17 Public Functions of QTouch Library for UC3L...................................................................152 6.3.17.1 QMatrix API.............................................................................................................................. 152 6.3.17.1.1 touch_qm_sensors_init........................................................................................................... 152 6.3.17.1.2 touch_qm_sensor_config........................................................................................................ 153 6.3.17.1.3 touch_qm_sensor_update_config ........................................................................................... 154 6.3.17.1.4 touch_qm_sensor_get_config................................................................................................. 154 6.3.17.1.5 touch_qm_channel_udpate_burstlen ...................................................................................... 154 6.3.17.1.6 touch_qm_update_global_param............................................................................................ 155 6.3.17.1.7 touch_qm_get_global_param ................................................................................................. 155 6.3.17.1.8 touch_qm_sensors_calibrate................................................................................................... 155 6.3.17.1.9 touch_qm_sensors_start_acquisition...................................................................................... 156 6.3.17.1.10 touch_qm_get_libinfo .......................................................................................................... 156 6.3.17.1.11 touch_qm_sensor_get_delta ................................................................................................. 157 6.3.17.2 QTouch Group A and QTouch Group B API ............................................................................ 157 6.3.17.2.1 touch_qt_sensors_init............................................................................................................. 157 6.3.17.2.2 touch_qt_sensor_config.......................................................................................................... 158 6.3.17.2.3 touch_qt_sensor_update_config ............................................................................................. 158 6.3.17.2.4 touch_qt_sensor_get_config................................................................................................... 159 6.3.17.2.5 touch_qt_update_global_param.............................................................................................. 159 6.3.17.2.6 touch_qt_get_global_param ................................................................................................... 159 6.3.17.2.7 touch_qt_sensors_calibrate..................................................................................................... 160 6.3.17.2.8 touch_qt_sensors_start_acquisition ........................................................................................ 160 6.3.17.2.9 touch_qt _sensor_ disable....................................................................................................... 161 6.3.17.2.10 touch_qt _sensor_ reenable .................................................................................................. 161 6.3.17.2.11 touch_qt_get_libinfo ............................................................................................................ 162 6.3.17.2.12 touch_qt_sensor_get_delta ................................................................................................... 162 6.3.18 Autonomous touch API ........................................................................................................162 6.3.18.1.1 touch_at_sensor_init............................................................................................................... 162 6.3.18.1.2 touch_at_sensor_enable.......................................................................................................... 163 6.3.18.1.3 touch_at_sensor_disable......................................................................................................... 163 6.3.18.1.4 touch_at_sensor_update_config ............................................................................................. 163 6.3.18.1.5 touch_at_sensor_get_config ................................................................................................... 164 6.3.18.1.6 touch_at_get_libinfo............................................................................................................... 164 6.3.18.2 Common API............................................................................................................................. 164 6.3.18.2.1 touch_event_dispatcher.......................................................................................................... 164 6.3.18.2.2 touch_deinit............................................................................................................................ 164 6.3.19 Integrating QTouch libraries for AT32UC3L in your application ......................................165 6.3.20 MISRA Compliance Report of QTouch Library for UC3L ..................................................1657 6.3.21 What is covered ...................................................................................................................165 6.3.22 Target Environment.............................................................................................................165 6.3.23 Deviations from MISRA C Standards..................................................................................165 6.3.24 Known Issues with QTouch Library for UC3L ....................................................................166 6.4 QTOUCH LIBRARY FOR ATTINY20 DEVICE ..................................................................................167 6.4.1 Salient Features of QTouch Library for ATtiny20...............................................................167 6.4.1.1 QTouch method sensor................................................................................................................... 167 6.4.2 Compiler tool chain support for ATtiny20...........................................................................167 Table 17 Compiler tool chains support for ATtiny20 QTouch Library....................................................... 167 6.4.3 Overview of QTouch Library for ATtiny20..........................................................................167 Figure 48 Schematic overview of QTouch on Tiny20................................................................................. 168 6.4.4 API Flow diagram for ATtiny20 ..........................................................................................168 Figure 49 Linker configuration options for Tiny20 ..................................................................................... 168 Figure 50 QTouch method for Tiny20 API Flow diagram .......................................................................... 169 6.4.5 QTouch Library configuration parameters for ATtiny20 ....................................................169 Table 18 QTouch Library for ATtiny20 Configuration parameters............................................................. 170 6.4.6 QTouch Library ATtiny20 Example projects.......................................................................171 6.4.7 QTouch Library ATtiny20 code and data memory requirements ........................................171 Table 19 QTouch Library for ATtiny20 Memory requirements.................................................................. 171 6.5 QTOUCH LIBRARY FOR ATTINY40 DEVICE ..................................................................................172 6.5.1 Salient Features of QTouch Library for ATtiny40...............................................................172 6.5.1.1 QTouch method sensor................................................................................................................... 172 6.5.2 Compiler tool chain support for ATtiny40...........................................................................173 Table 20 Compiler tool chains support for ATtiny40 QTouch Library....................................................... 173 6.5.3 Overview of QTouch Library for ATtiny40..........................................................................173 Figure 51 Schematic overview of QTouch on Tiny40................................................................................. 173 6.5.4 API Flow diagram for ATtiny40 ..........................................................................................174 Figure 52 QTouch method for Tiny40 API Flow diagram .......................................................................... 175 6.5.5 QTouch Library configuration parameters for ATtiny40 ....................................................175 Table 21 QTouch Library for ATtiny40 Configuration parameters............................................................. 176 6.5.6 QTouch Library ATtiny40 Example projects.......................................................................177 6.5.7 QTouch Library ATtiny40 code and data memory requirements ........................................177 Table 22 QTouch Library for ATtiny40 Memory requirements.................................................................. 177 6.5.8 Interrupt Handling in QTouch ADC....................................................................................177 7 GENERIC QTOUCH LIBRARIES FOR 2K DEVICES...............................................................178 7.1 INTRODUCTION.............................................................................................................................178 7.2 DEVICES SUPPORTED ....................................................................................................................178 7.3 SALIENT FEATURES OF QTOUCH LIBRARY FOR 2K DEVICES........................................................178 7.4 LIBRARY VARIANTS .....................................................................................................................178 7.5 QTOUCH API FOR 2K DEVICES AND USAGE.................................................................................178 7.5.1 touch_api_2kdevice.h - public header file ...........................................................................178 7.5.2 Sequence of Operations and Using the API.........................................................................179 7.5.2.1 Channel Numbering ....................................................................................................................... 179 7.5.2.1.1 Channel numbering when routing SNS and SNSK pins to different ports............................... 179 7.5.2.1.2 Channel numbering when routing SNS and SNSK pins to the same port ................................ 180 7.5.2.2 Rules For Configuring SNS and SNSK masks for 2K Devices...................................................... 180 7.5.2.2.1 Configuring SNS and SNSK masks in case of Interport: ......................................................... 180 7.5.2.2.2 Configuring SNS and SNSK masks in case of Intraport: ......................................................... 181 7.5.3 Integrating QTouch libraries for 2K Devices in your application.......................................181 7.6 MISRA COMPLIANCE REPORT.....................................................................................................182 7.6.1 What is covered ...................................................................................................................182 7.6.2 Target Environment.............................................................................................................182 7.6.3 Deviations from MISRA C Standards..................................................................................182 7.6.3.1 QTouch acquisition method libraries for 2K devices..................................................................... 182 8 REVISION HISTORY......................................................................................................................183 DISCLAIMER ...........................................................................................................................................1858 8207L-AT42-05/12 1 Preface This manual contains information that enables customers to implement capacitive touch solutions on ATMEL AVR® microcontrollers and ARM® -based AT91SAM microcontrollers using ATMEL QTouch libraries. This guide is a functional description of the library software, its programming interface and it also describes its use on the supported reference systems. Use of this software is bound by the Software License Agreement included with the Library. This user guide is applicable for Atmel QTouch® Library 5.0 . Related documents from ATMEL Documents related to QTouch capacitive sensing solutions from ATMEL are • TS2080A/B data sheet. • QT600 users guide • Release Notes for ATMEL QTouch libraries. • A library selection excel workbook that is used for the selection of the appropriate library variant from the package available under in the install directory. The default location is C:\Program Files\Atmel\Atmel_QTouch_Libraries_5.x\ • Capacitive touch sensor design guide http://www.atmel.com/dyn/resources/prod_documents/doc10620.pdf . If you need Assistance For assistance with QTouch capacitive sensing software libraries and related issues, contact your local ATMEL sales representative or send an email to touch@atmel.com for AVR libraries and at91support@atmel.com for SAM libraries.9 2 Introduction ATMEL QTouch Library is a royalty free software library (available for GCC and IAR compiler tool chains) for developing touch applications on standard AVR and SAM microcontrollers. Customers can link the library into their applications in order to provide touch sensing capability in their projects. The Library can be used to develop single chip solutions for control applications which have touch sensing capabilities, or to develop standalone touch sensing solutions which interface with other host or control devices. Features of ATMEL QTouch Library include • Capacitive touch sensing using patented charge-transfer signal acquisition for robust sensing. • Support for a wide range of 8- and 32-bit AVRs. • Support for 32-bit ARM microcontrollers. • Support for 8-bit tiny AVRs having flash of 2K bytes. • Support both QTouch and QMatrix acquisition methods and autonomous touch for UC3L. • Support up to 64 touch sense channels for generic libraries and up to 136 channels for UC3L libraries. • Flexible choice of touch sensing functionality (keys, sliders, wheels) in a variety of combinations. • Includes Adjacent Key Suppression® (AKS® ) technology for the unambiguous detection of key events. • Support for both IAR and GCC compiler tool chains. • A comparison of various features and parameters between QTouch Libraries for Generic 8-bit and 32-bit AVRs as well as Device Specific Libraries is provided in the table below. Feature Comparison between Generic QTouch Libraries and Device Specific Libraries Parameter/Func tionality Generic Libraries, Tiny_Meg a_Xmega Tiny 2K Libraries Tiny20 Libraries Tiny40 Libraries Generic Libraries, 32 Bit AVR UC3L Libraries ATSAM Libraries Technology QTouch, QMatrix QTouch QTouchADC QTouchADC QTouch, QMatrix QTouch, QMatrix QTouch Rotors/Sliders Support Yes No No No Yes Yes Yes Filter Callback Yes Yes No Yes Yes Yes Yes Library Status Flags Yes Yes No Yes(Only Burst Again Flag) Yes Yes Yes Library Signature Yes No No No Yes Yes Yes Calibrate Sensing Yes Yes (Only burst_again flag) No Yes Yes Yes Yes Reset Sensing Yes Yes No Yes Yes Yes Yes Sensor Deltas Yes Yes No Yes Yes Yes Yes Maximum AKS Groups 7 7 1 7 7 7 710 8207L-AT42-05/12 Maximum Channels, QT 16 4 5 12 32 17 32 Maximum Rotors/Sliders, QT 4 0 0 0 8 8 Maximum Channels, QM 64 0 0 0 64 64 0 Maximum Rotors/Sliders, QM 8 0 0 0 8 0 Autonomous Touch No No No No No Yes No Sensor Reconfiguratio n Yes Yes No No Yes Yes Yes Frequency Hopping SS Enabled Always If _POWER_ OPTIMIZA TION = 0 Never Never Always Programma ble Always Delay Cycles Parameter QT_DELAY _CLCYES (QT Values: 1 to 255 QM Values: 1,2,3,4,5,10 ,25,50) QT_DELAY _CLCYES (Value: 1 to 255) DEF_CHA RGE_SHA RE_DELAY (Value: 1 to 255) DEF_QT_C HARGE_S HARE_DEL AY (Value: 1 to 255) QT_DELAY _CYCLES (QT Values : 1 to 255 QM Values: 1,2,3,4,5,10 ,25,50) xx_CHLEN, xx_SELEN (QT/QM Value: 3 to 255) QT_DELAY _CLCYES (Value: 3 to 255) Debug Interface Enable Macro _DEBUG_I NTERFAC E_ None NDEBUG _DEBUG_ QTOUCH_ STUDIO_ _DEBUG_I NTERFAC E_ DEF_TOU CH_QDEB UG_ENAB LE _DEBUG_I NTERFAC E_ This user guide describes the content, design and use of the QTouch Libraries. This should be read in conjunction with all of the applicable documents listed below • Device datasheet for the selected ATMEL device used for touch sensing. • Data sheet for the selected evaluation board. • A library selection guide that is used for the selection of the appropriate library from the released package. Default path: C:\ Program Files\Atmel\Atmel_QTouch_Libaries_5.x\Library_Selection_Guide.xls The intended readers of this document are engineers, who use the QTouch Library on ATMEL microcontrollers to realize capacitive touch sensing solutions. 3 Overview This chapter gives a brief introduction to each of the chapters that make up this document 1. Preface 2. Introduction: Provides an introduction to the scope and use of the QTouch Library. 3. Overview: This chapter 4. Abbreviations and Definitions: Provides a description of the abbreviations and definitions used in this document 5. Generic QTouch Libraries: Provides an overview of the QTouch libraries and the different acquisition methods for generic ATMEL devices. 6. Device Specific Libraries: Provides an overview of the QTouch libraries and the different acquisition methods for ATMEL devices specific for touch sensing. 7. Revision History: Provides a revision history of this document11 4 Abbreviations and Definitions 4.1 Definitions • AVR: refers to a device(s) in the tinyAVR®, megaAVR®, XMEGA™ and UC3 microcontroller family. • ARM: refers to a device in the ATSAM ARM® basedmicrocontroller family. • ATMEL QTouch Library: The combination of libraries for both touch sensing acquisition methods (QTouch and QMatrix). • QTouch Technology: A type of capacitive touch sensing technology using self capacitance - each channel has only one electrode. • QMatrix Technology: A type of capacitive touch sensing technology using mutual capacitance – each channel has an drive electrode (X) and an receive electrode (Y). • Sensor: A channel or group of channels used to form a touch sensor. Sensors are of 3 types (keys, rotors or sliders). • KEY: a single channel forms a single KEY type sensor, also known as a BUTTON • ROTOR, also known as a WHEEL, a group of channels forms a ROTOR sensor to detect angular position of touch. o A Rotor is composed of 3 channels for a QTouch acquisition method. o A Rotor can be composed of 3 to 8 channels for QMatrix acquisition method. • SLIDER, a group of channels forms a SLIDER sensor to detect the linear position of touch. o A Slider is composed of 3 channels for a QTouch acquisition method. o A Slider can be composed of 3 to 8 channels for QMatrix acquisition method. • AKS: Adjacent Key Suppression. See Section 5.4.5 • SNS PIN: Sense line for capacitive measurement using the QTouch Technology - connected to Cs. • SNSK PIN: Sense Key line for capacitive measurement using the QTouch Technology - connected to channel electrode through Rs. • X Line: The drive electrode (or drive line) used for QMatrix Technology. • Y Line: The receive electrode (or receive line) used for QMatrix Technology. • Port Pair: A combination of SNS port and SNSK port to which sensors are connected for QTouch technology. The SNS and SNSK ports used in a port pair can be located in the same AVR Port (8 pins for 4 sensors), or they may be in different 2 different AVR Ports (8+8 pins for 8 sensors). • Charge Cycle Period: It is the width of the charging pulse applied to the channel capacitor. • Dwell Cycle: In a QMatrix acquisition method, the duration in which charge coupled from X to Y is captured. • Acquisition: A single capacitive measurement process. • Electrode: Electrodes are typically areas of copper on a printed circuit board but can also be areas of clear conductive indium tin oxide (ITO) on a glass or plastic touch screen.12 8207L-AT42-05/12 • Intra-port: A configuration for QTouch acquisition method libraries, when the sensor SNS and SNSK pins are available on the same port. • Inter-port: A configuration for QTouch acquisition method libraries, when the sensor SNS and SNSK pins are available on distinct ports. 5 Generic QTouch Libraries 5.1 Introduction ATMEL QTouch provides a simple to use solution to realize touch sensing solutions on a range of supported ATMEL AVR Microcontrollers. The QTouch libraries provide support for both QTouch and QMatrix acquisition methods. Touch sensing using QMatrix or QTouch acquisition methods can be added to an application by linking the appropriate ATMEL QTouch Library for the AVR Microcontroller and using a simple set of API to define the touch channels and sensors and then calling the touch sensing API’s periodically (or based on application needs) to retrieve the channel information and determine touch sensor states. Figure 5-1 shows a typical configuration of channels when using an AVR and using the ATMEL QTouch Library. The ATMEL QTouch Library has been added to a host application running on an AVR microcontroller. The sample configuration illustrates using the library that supports eight touch channels numbered 0 to 7. The sensors are configured in the following order, • Sensor 0 on channels 0 to 2 have been configured as a rotor sensor. • Sensor 1 on channels 3 to 5 have been configured as a slider sensor. • Sensor 2 on channel 6 is configured as key sensor. • Sensor 3 on channel 7 is configured as key sensor. The host application uses the QTouch Library API’s to configure these channels and sensors, and to initiate detection of a touch using capacitive measurements. channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 Atmel QTouch Library Host Application sensor0 sensor1 sensor2 sensor3 Figure 5-1 : Typical interface of the ATMEL QTouch library with the host application. The QTouch libraries use minimal resources of the microcontroller. The sampling of the sensors is controlled by the QTouch library, while the sampling period is controlled by the application (possibly using timers, sleep periods, varying the CPU clock, external events like interrupts or communications, etc).13 5.2 Acquisition Methods There are two methods available for touch acquisition namely 1. QTouch acquisition method. 2. QMatrix acquisition method. Libraries for AVR microcontrollers include both acquisition methods. Libraries for ATSAM microcontrollers include only QTouch acquisition method. 5.2.1 QTouch acquisition method The QTouch acquisition method charges an electrode of unknown capacitance to a known potential. The resulting charge is transferred into a measurement capacitor (Cs). The cycle is repeated until the voltage across Cs reaches a voltage Vih. The signal level is the number of charge transfer cycles it took to reach that voltage. Placing a finger on the touch surface introduces external capacitance that increases the amount of charge transferred each cycle, reducing the total number of cycles required for Cs to reach the voltage. When the signal level (number of cycles) goes below the present threshold, then the sensor is reported to be in detected. QTouch acquisition method sensors can drive single or multiple keys. Where multiple keys are used, each key can be set for an individual sensitivity level. Keys of different sizes and shapes can be used to meet both functional and aesthetic requirements. NOTE: It is recommended to keep the size of the keys larger than 6mmx6mm to ensure reliable and robust measurements, although actual key design requirements also depend on panel thickness and material. Refer to the ATMEL Capacitive touch sensor design guide for details. QTouch acquisition method can be used in two ways • normal touch contact (i.e. when pressing buttons on a panel), and • high sensitivity proximity mode (i.e. when a panel lights up before you actually contact it). Figure 5-2 : QTouch Acquisition QTouch circuits offers high signal-to-noise ratio, very good low power performance, and the easiest sensor layout.14 8207L-AT42-05/12 5.2.1.1 Sensor schematics for a QTouch acquisition method design Electrode Microcontroller Used for touch application PB1 PC1 SNSK SNS Sampling capacitor Rs Cs Rs- 1k Cs- 22nF ---------------- Port requirements: SNS: generic I/O pin SNSK: generic I/O pin Rs- Series resistor, Cs – Sample capacitor, PB1- PortB bit1, and PC1- PortC bit1 Typical values: Figure 5-3 : Schematics for a QTouch acquisition method design 5.2.2 QMatrix acquisition method QMatrix devices detect touch using a scanned passive matrix of electrode sets. A single QMatrix device can drive a large number of keys, enabling a very low cost-per-key to be achieved. Figure 5-4 : QMatrix Acquisition method15 QMatrix uses a pair of sensing electrodes for each channel. One is an emitting electrode into which a charge consisting of logic pulses is driven in burst mode. The other is a receive electrode that couples to the emitter via the overlying panel dielectric. When a finger touches the panel the field coupling is changed, and touch is detected. The drive electrode (or drive line) used for QMatrix charge transfer is labeled as the X line. The receiver electrode (or receive line) used for QMatrix charge transfer is labeled as the Y line. QMatrix circuits offer good immunity to moisture films, extreme levels of temperature stability, superb low power characteristics, and small IC package sizes for a given key count. 5.2.3 Sensor schematics for a QMatrix acquisition method design Atmel MCU X0 ... Xn Y0A ... YmA ... Y0B YmB SMP Vref RX0 RXn RY0 RYm CS0 CSm RYB0 RYBm Sensor 0,0 Sensor n,0 Sensor n,m Sensor 0,m Sensors, X,Y Typical values: RX: 1k RY: 1k CS: 4.7nF RYB: 470k ---------------------------------- Port-pin count = n + (2 * m) + 2 n – number of X lines m – number of Y lines ---------------------------------- Port requirements: X: Configurable I/O pin YA:Configurable I/O pin (*) YB: ADC port (*) SMP: Configurable I/O pin Vref: AIN0 (Comparator) (*): The port I/O pin should be in consecutive order Figure 5-5 : Schematics for a QMatrix acquisition method design 5.3 Global settings common to all sensors of a specific acquisition method The touch sensing using QTouch library could be fine tuned by using a number of configurable settings. This section explains the settings that are common to all sensors of a specific acquisition method like QMatrix or QTouch.16 8207L-AT42-05/12 For example, if recalibration threshold (one of the global settings) of QMatrix acquisition method is set as 1, all QMatrix sensors will have recalibration threshold of 1. 5.3.1 Recalibration Threshold Recalibration threshold is the level above which automatic recalibration occurs. Recalibration threshold is expressed as a percentage of the detection threshold setting. This setting is an enumerated value and its settings are as follows: • Setting of 0 = 100% of detect threshold (RECAL_100) • Setting of 1 = 50% of detect threshold (RECAL_50) • Setting of 2 = 25% of detect threshold (RECAL_25) • Setting of 3 = 12.5% of detect threshold (RECAL_12_5) • Setting of 4 = 6.25% of detect threshold (RECAL_6_25) However, an absolute value of 4 is the hard limit for this setting. For example, if the detection threshold is say, 40 and the Recalibration threshold value is set to 4. This implies an absolute value of 2 (40 * 6.25% = 2.5), but this is hard limited to 4. Setting Variable name Data Type Unit Min Max Typical Recalibration threshold qt_recal_threshold uint8_t Enum 4 Detect threshold 1 5.3.2 Detect Integration The QTouch Library features a detect integration mechanism, which acts to confirm detection in a robust fashion. The detect integrator (DI) acts as a simple signal filter to suppress false detections caused by spurious events like electrical noise. A counter is incremented each time the sensor delta has exceeded its threshold and stayed there for a specific number of acquisitions, without going below the threshold levels. When this counter reaches a preset limit (the DI value) the sensor is finally declared to be touched. If on any acquisition the delta is not seen to exceed the threshold level, the counter is cleared and the process has to start from the beginning. The DI process is applicable to a ‘release’ (going out of detect) event as well. For example, if the DI value is 10, then the device has to exceed its threshold and stay there for 10 acquisitions in succession without going below the threshold level, before the sensor is declared to be touched. Setting Variable name Data Type Unit Min Max Typical D I qt_ di uint8_ t Cycle s 0 25 5 4 5.3.3 Drift Hold Time Drift Hold Time (DHT) is used to restrict drift on all sensors while one or more sensors are activated. It defines the length of time the drift is halted after a key detection.17 This feature is useful in cases of high density keypads where touching a key or floating a finger over the keypad would cause untouched keys to drift, and therefore create a sensitivity shift, and ultimately inhibit any touch detection. Setting Variable name Data Type Unit Min Max Typical Drift hold time qt_drift_hold_time uint8_t 200 ms 1 255 20 (4s) 5.3.4 Maximum ON Duration If an object unintentionally contacts a sensor resulting in a touch detection for a prolonged interval it is usually desirable to recalibrate the sensor in order to restore its function, perhaps after a time delay of some seconds. The Maximum on Duration timer monitors such detections; if detection exceeds the timer’s settings, the sensor is automatically recalibrated. After a recalibration has taken place, the affected sensor once again functions normally even if it still in contact with the foreign object. Max on duration can be disabled by setting it to zero (infinite timeout) in which case the channel never recalibrates during a continuous detection (but the host could still command it). Setting Variable name Data Type Unit Min Max Typical Maximum ON Duration qt_max_on_duration uint8_t 200 ms 0 255 30 (6s) 5.3.5 Positive / Negative Drift Drift in a general sense means adjusting reference level (of a sensor) to allow compensation for temperature (or other factor) effect on physical sensor characteristics. Decreasing reference level for such compensation is called Negative drift & increasing reference level is called Positive drift. Specifically, the drift compensation should be set to compensate faster for increasing signals than for decreasing signals. Signals can drift because of changes in physical sensor characteristics over time and temperature. It is crucial that such drift be compensated for; otherwise false detections and sensitivity shifts can occur. Drift compensation occurs only while there is no detection in effect. Once a finger is sensed, the drift compensation mechanism ceases since the signal is legitimately detecting an object. Drift compensation works only when the signal in question has not crossed the ‘Detect threshold’ level. The drift compensation mechanism can be asymmetric; it can be made to occur in one direction faster than it does in the other simply by changing the appropriate setup parameters. Signal values of a sensor tend to decrease when an object (touch) is approaching it or a characteristic change of sensor over time and temperature. Decreasing signals should not be compensated for quickly, as an approaching finger could be compensated for partially or entirely before even touching the channel (negative drift). However, an object over the channel which does not cause detection, and for which the sensor has already made full allowance (over some period of time), could suddenly be removed leaving the sensor with an artificially suppressed reference level and thus become insensitive to touch. In the latter case, the sensor should compensate for the object’s removal by raising the reference level relatively quickly (positive drift).18 8207L-AT42-05/12 Setting Variable name Data Type Unit Min Max Typical Negative Drift qt_neg_drift_rate uint8_t 200 ms 1 127 20 (4s) Positive Drift qt_pos_drift_rate uint8_t 200 ms 1 127 5 (1s) 5.3.6 Positive Recalibration Delay If any key is found to have a significant drop in signal delta, (on the negative side), it is deemed to be an error condition. If this condition persists for more than the positive recalibration delay, i.e., qt_pos_recal_delay period, then an automatic recalibration is carried out. A counter is incremented each time the sensor delta is equal to the positive recalibration threshold and stayed there for a specific number of acquisitions. When this counter reaches a preset limit (the PRD value) the sensor is finally recalibrated. If on any acquisition the delta is seen to be greater than the positive recalibration threshold level, the counter is cleared and the positive drifting is performed. For example, if the PRD value is 10, then the delta has to drop below the recalibration threshold and stay there for 10 acquisitions in succession without going below the threshold level, before the sensor is declared to be recalibrated. Setting Variable name Data Type Unit Min Max Typical Positive Recalibration Delay qt_pos_recal_delay uint8_t cycles 1 255 3 5.4 Sensor specific settings Apart from global settings as mentioned in the section above, touch sensing using QTouch library could also be fine tuned by more number of configurable settings. This section explains the settings that are specific to each sensor. For example, sensor 0 can have a detect threshold (one of the sensor specific setting) that is different from sensor 1. 5.4.1 Detect threshold A sensor’s negative (detect) threshold defines how much its signal must drop below its reference level to qualify as a potential touch detect. The final detection confirmation must however satisfy the Detect Integrator (DI) limit. Larger threshold values desensitize sensors since the signal must change more (i.e. requires larger touch) in order to exceed the threshold level. Conversely, lower threshold levels make sensors more sensitive. Threshold setting depends on the amount of signal swing that occurs when a sensor is touched. Thicker front panels or smaller electrodes usually have smaller signal swing on touch, thus require lower threshold levels. Setting Variable name Data Type Unit Min Max Typical Threshold threshold uint8_t counts 3 255 10 – 20 5.4.2 Hysteresis This setting is sensor detection hysteresis value. It is expressed as a percentage of the sensor detection threshold setting. Once a sensor goes into detect its threshold level is reduced (by the 19 hysteresis value) in order to avoid the sensor dither in and out of detect if the signal level is close to original threshold level. • Setting of 0 = 50% of detect threshold value (HYST_50) • Setting of 1 = 25% of detect threshold value (HYST_25) • Setting of 2 = 12.5% of detect threshold value (HYST_12_5) • Setting of 3 = 6.25% of detect threshold value (HYST_6_25) Setting Variable name Data Type Unit Min Max Typical Hysteresis detect_hysteresis uint8_t (2 bits) Enum HYST_6_25 HYST_50 HYST_6_25 5.4.3 Position Resolution The rotor or slider needs the position resolution (angle resolution in case of rotor and linear resolution in case of slider) to be set. Resolution is the number of bits needed to report the position of rotor or slider. It can have values from 2bits to 8 bits. Setting Variable name Data Type Unit Min Reported position Max Reported position Typica l Position Resoluti on position_ resolution uint8_t (3 bits) - 2 bits 0 – 3 8 bits 0-255 8 5.4.4 Position Hysteresis In case of QMatrix, the rotor or slider needs the position hysteresis (angle hysteresis in case of rotor and linear hysteresis in case of slider) to be set. It is the number of positions the user has to move back, before touch position is reported when the direction of scrolling is changed and during the first scrolling after the touch down. Hysteresis can range from 0 (1 position) to 7 ( 8 positions). The hysteresis is carried out at 8 bits resolution internally and scaled to desired resolution; therefore at resolutions lower than 8 bits there might be a difference of 1 reported position from the hysteresis setting, depending on where the touch is detected. At lower resolutions, where skipping of the reported positions is observed, hysteresis can be set to 0 (1 position). At Higher resolutions (6 ..8bits) , it would be recommended to have a hysteresis of at least 2 positions or more. NOTE: It is not valid to have a hysteresis value more than the available bit positions in the resolution. Ex: do not have a hysteresis value of 5 positions with a resolution of 2 bits (4 positions). Setting Variable name Data Type Unit Min Max Typical Position Hysteresis position_hysteresis uint8_t (3 bits) - 0 7 3 NOTE: Position hysteresis is not valid (unused) in case of QTouch acquisition method libraries.20 8207L-AT42-05/12 5.4.5 Adjacent Key Suppression (AKS) In designs where the sensors are close together or set for high sensitivity, multiple sensors might report detect simultaneously if touch is near them. To allow applications to determine the intended single touch, the touch library provides the user the ability to configure a certain number of sensors in an AKS group. When a group of sensors are in the same AKS group, then only the first strongest sensor will report detection. The sensor reporting detection will continue to report detection even if another sensor’s delta becomes stronger. The sensor stays in detect until its delta falls below its detection threshold, and then if any more sensors in the AKS group are still in detect then the strongest will report detection. So at any given time only one sensor from each AKS group will be reported to be in detect. The library provides the ability to configure any sensor to be included in any one of the Adjacent Key Suppression Groups (AKS Group). Setting Variable name Data Type Unit Min Max Typical AKS Group aks_group uint8_t (3 bits) Enum 0 (off) 7 0 (off) 5.5 Using the Sensors 5.5.1 Avoiding Cross-talk In ATMEL QTouch library variants that use QTouch acquisition technology, adjacent sensors are not measured at the same time. This prevents interference due to cross-talk between adjacent channels, but at the same time some sensor configurations take longer to measure than others. For example, if an 8-channel device is configured to support 8 keys, then the library will measure the keys on channels 0, 2, 4, and 6 parallely, followed by keys on channels 1, 3, 5, and 7. If the same device is configured, say, to support 4 keys, putting them either on all the odd channels or on all the even channels means that they can all be measured simultaneously. This means the library calls are faster, and the device can use less power. So, it is recommended that the appropriate channel numbers are used when using less than the maximum number of channels available for the device to ensure optimum performance. In a similar sense for faster execution and reduced power consumption, it is also advisable to use intra-port sensor configuration instead of inter-port sensor configuration while using 4 channels on the same port. 5.5.2 Multiple measurements The library will not automatically perform multiple measurements on a sensor (Ex: To resolve for instance Detect Integration or recalibration.). The user is given the option to perform the measurement multiple times if certain conditions are met. This will enable the user to implement the time critical code thereby making the qt_measure_sensors() a non-blocking API .The host application has to perform multiple measurements, based on the need. The global flag QTLIB_BURST_AGAIN indicating that multiple measurements are needed is passed to the user. This is BIT8 of the return value from the qt_measure_sensors( ) API. The main_
_qt_k_ rs Field Name Values Comments vP v1, v3, xmega, uc3a, uc3b, uc3c VersionP of the core AVR device supported by this library variant Q 1 to 6 GroupQ of the core AVR device supported by this library variant CH 4, 8, 12, 16, 32 Total number of channels supported by each library. RS 1, 2, 3, 4, 8 Total number of rotors / sliders supported for the respective channel counts mentioned in previous row. The configuration sets for AVR Studio IDE are named according to the convention listed below Configuration set for AVR Studio IDE g _qt_k_ rs Field Name Values Comments avrP avr25, avr4, avr 51, avr5, xmega, uc3a, uc3b, uc3c VersionP of the core AVR device supported by this library variant Q 1 to 6 GroupQ of the core AVR device supported by this library variant CH 4, 8, 12, 16, 32 Total number of channels supported by each library. RS 1, 2, 3, 4, 8 Total number of rotors / sliders supported for the respective channel counts mentioned in previous row. Depending on your need, you need to select the right configuration required and build the project.69 Figure 5-11: Selecting the right configuration in the QTouch acquisition method example applications in IAR –IDE Figure 5-12 : Selecting the right configuration in QTouch acquisition method example applications in AVR-6 IDE 5.6.11.2.2 Changing the settings to match your device 5.6.11.2.2.1 Processor settings Once you have selected the appropriate example project and the configuration, you need to ensure that the settings in the project are configured to reflect the correct device. The settings include • Device type ( CPU type ) for the project70 8207L-AT42-05/12 Figure 5-13 : Changing the processor settings for the examples in IAR IDE Figure 5-14 : Changing the processor settings for the examples in AVR-Studio 6 5.6.11.2.3 Changing the library configuration parameters The configuration parameters required for the library are specified in the touch_config.h file of the examples under the custom user configuration section. Please refer to the example projects provided with the QTouch libraries release for more information. The mandatory constants to be defined are as listed below.71 Symbol / Constant name Range of values Comments _QTOUCH_ This macro has to be defined in order to use QTouch libraries. SNS & SNSK Section 5.7.1.5 provides details on the range of values allowed. To be used if only single port pair is needed for the design SNS1 – SNSK1 & SNS2 – SNSK2 Section 5.7.1.5.2 has details on the range of values allowed To be used if two port pairs are needed for the design QT_NUM_CHANNELS 4, 8, 12, 16 for tinyAVR, megaAVR and XMEGA device libraries and 8, 16, 32 for UC3 device libraries. _ROTOR_SLIDER_ Rotor / slider can be added to the design, if this symbol is defined A library with rotor / slider functionality already available needs to be selected if this macro is to be enabled _DEBUG_INTERFACE_ The debug interface code in the example application will be enabled if this macro is enabled. This will enable the application to output QTouch measurement values to GPIO pins, which can be used by a USB bridge to view the output on Hawkeye or QTouch Studio. This feature is currently supported by EVK/TS 2080A and QT600 boards. QT_DELAY_CYCLES 1 to 255 Please refer to section QTOUCH_STUDIO_MASKS This macro needs to be defined if QTouch Studio Pin Configurator Wizard.is used to generate the SNS and SNSK masks. Please refer to section 5.8.1 _STATIC_PORT_PIN_CONF_ This macro needs to be defined only in case of 4 and 8 channel libraries with interport configuration and pin configurability. Please refer to section 5.8.172 8207L-AT42-05/12 Figure 5-15 : Specifying the QTouch acquisition method library configuration parameters for QTouch example projects 5.6.11.2.4 Using the example projects The sample applications are shipped with the complete set of files required to configure, build, execute and test the application for both IAR-workbench and AVR Studio IDEs. The sample applications are provided for the evaluation kits and a few configurations for select devices. The user can use the sample applications as a reference or baseline to configure different configurations. Please ensure to change the configuration settings in the project options to match the device selected. To change the configuration settings of the sample applications, 1. Select the configuration from the list of configurations available. 2. If the user wishes to have a new name for the configuration to be used, a new configuration can be added to the project. 3. If a different variant of the library needs to be used, remove the existing library in that particular configuration and add the library variant that you require. Please refer to 5.7.1.4 for details on the different library variants. Update the linker options to specify the library to be linked. 4. Specify the tunable configuration parameters for the project as illustrated in sections 5.6.11.2.2 and 5.6.11.2.3.73 5.6.11.3 Example applications for QMatrix acquisition method libraries The QMatrix acquisition method libraries include example projects for some of the supported devices. Example projects for both IAR IDE and AVR Studio IDE along with example applications are provided for select devices using the QMatrix acquisition libraries. These sample applications demonstrate the usage of the touch API’s to add touch sensing to an application. Refer to the library selection guide for details on the example projects and sample applications supported for the release. 5.6.11.3.1 Selecting the right configuration The sample applications are built to support a maximum channel support configuration available for that particular device for both IAR & AVR IDEs. Internally there are two configurations for each device. • ALL KEYS configuration : Supports only keys • KEYS/ROTORS/SLIDERS configuration : Supports keys or rotors or sliders concurrently These configurations enable a set of stored options and a specific library to be selected in order to build application using the specific library. Figure 5-16 : Selecting the right configuration in the QMatrix acquisition method example applications in IAR –IDE74 8207L-AT42-05/12 Figure 5-17 : Selecting the right configuration in the QMatrix acquisition method example applications in AVR Studio IDE 5.6.11.3.2 Changing the library configuration parameters The configuration parameters required for the library are specified in the touch_config.h file of the examples. Please refer to the example projects provided with the QTouch libraries release for more information. 75 Figure 5-18 : Specifying QMatrix acquisition library parameters in touch_config.h for QMatrix projects 5.6.11.3.3 Using the example projects The sample applications are shipped with the complete set of files required to configure, build, execute and test the application for both IAR-workbench and AVR Studio IDEs. The sample applications are provided for the evaluation kits and a few configurations for select devices. The user can use the sample applications as a reference or baseline to configure different configurations. Please ensure to change the configuration settings in the project options to match the device selected To change the configuration settings of the sample applications, 1) Select the configuration from the list of configurations available as shown in section 5.6.11.3.1 2) If the user wishes to have a new name for the configuration to be used, a new configuration can be added to the project 3) If a different variant of the library needs to be used, remove the existing library in that particular configuration and add the library variant that you require. Please refer to library 76 8207L-AT42-05/12 selection guide for details on the different library variants. Update the linker options to specify the library to be linked 4) Specify the tunable configuration parameters for the project as illustrated in 5.6.11.3.2 5) For QMatrix on XMEGA devices, please check if the pre-processor symbol _ATXMEGA_ is added in the project space or not. 5.6.11.4 Adjusting the Stack size when using IAR IDE The example projects for IAR IDE, the CSTACK and RSTACK values are configured to account for the requirements of the QTouch libraries and the included main.c file which illustrates the usage of the touch API. • Adjust the CSTACK and RSTACK values appropriately based on additional software integrated or added to the examples. Figure 5-19 : Modifying the stack size in IAR IDE 5.6.11.5 Optimization levels The default configuration settings in sample projects which ship with the library are set to the highest level of optimization for IAR and GCC variants of the libraries. The user might be required to change this setting for debugging purposes • In case of IAR, The optimizations tab in project configuration options specifies High. • In case of GCC, the libraries are compiled with the –Os which signifies that the Optimization for generating the library is maximum.77 Figure 5-20 : Specifying the optimization level in IAR IDE 5.6.11.6 Debug Support in Example applications The EVK2080 and QT600 applications provide output debug information on standard GPIO pins through the USB Bridge IC to PC software for display by AVR QTouch Studio. Similarly for ATMEL devices that are not supported through EVK or QT600 kits, the output measurement values can be viewed through AVR QTouch Studio using the same QDebug protocol and QT600 USB bridge. If a QT600 bridge is not available, please refer to section 5.6.11.6.3 for more information on observing the output touch measurement data without the use of a USB bridge or AVR QTouch Studio. 5.6.11.6.1 Debug Support in the sample applications for EVK2080 and QT600 boards The sample applications provided for the EVK2080 boards, QT600 boards and the other example projects output debug information which is captured by a USB bridge chip and then routed to the QTouch Studio for display. Note: The port and pins assigned for the QDebug protocol with the example projects are arbitrary and have to be changed based on the project configuration chosen and pin availability. A separate App note is available on the Atmel website (in QTouch libraries webpage) explaining the QT600 debug protocol. 5.6.11.6.2 How to turn on the debug option In the project options, the symbol definition _DEBUG_INTERFACE_ is used to enable reporting the debug data. You can enable the debug interface by enabling the debug macro in touch_config.h file.78 8207L-AT42-05/12 Figure 5-21 : Enabling and configuring the Debug Support 5.6.11.6.3 Debug Interface if USB Bridge board is not available For the sample applications using the devices that are not supported on EVK2080 and QT600 the debug interface code is not provided. This is because a separate USB bridge board is required to read the data and display it on QTouch studio. However in this case the output touch measurement data can still be viewed using the IAR or AVR Studio IDE when running the code in debug mode using debug wire or emulator. extern qt_touch_lib_measure_data_t qt_measure_data; The qt_measure_data global variable contains the output touch measurement data. Refer to section 5.6.4.3 for more information on the data type. For GCC generated libraries the output touch measurement data can be observed on the watch window through the pointer pqt_measure_data. qt_touch_lib_measure_data_t *pqt_measure_data = &qt_measure_data;79 5.7 Library Variants 5.7.1 QTouch Acquisition method library variants 5.7.1.1 Introduction Variants of the ATMEL QTouch Library based on QTouch Technology are available for a range of ATMEL Microcontrollers. This section lists the different variants available. By following a simple series of steps, the user can identify the right library variant to use in his application. 5.7.1.2 Support for different compiler tool chains The QTouch acquisition method libraries are supported for the following compiler tool chains. Table 7 Compiler tool chains supported for QTouch acquisition method libraries Tool Version IAR Compiler for 8bit AVR 6.10.0 IAR Embedded Workbench for AVR 6.10 Atmel Studio 6.0.x IAR Compiler 32bit AVR 4.10.1 GCC – GNU Toolchain for AVR 8bit 3.4.0.1028 GCC – GCC Toolchain AVR 32bit 3.4.0.1028 IAR Embedded Workbench for ARM 6.30 GCC for ARM Sourcery G++ Lite for ARM EABI V 2011.3.0.42 5.7.1.3 QTouch Acquisition method library naming conventions The libraries are named according the convention listed below 5.7.1.3.1 Naming convention for libraries to be used with GCC tool chain lib g1_ qt_k_ rs.a Field name Possible values Comments coreP avr25 avr 35 avr 4 avr 51 avr 5 avrxmega2 avrxmega3 avrxmega4 avrxmega5 avrxmega6 avrxmega7 uc3a uc3b uc3c sam3s sam3u VersionP of the core for AVR/ATSAM devices supported by this library variant for tinyAVR and megaAVR devices. 80 8207L-AT42-05/12 sam3n sam4s CH 4, 8, 12, 16, 32 Total number of channels supported by each library. RS 1, 2, 3, 4, 8 Total number of rotors / sliders supported for the respective channel counts mentioned in previous row. For example, the library variant “libavr25g1_8qt_k_2rs.a” supports the following configuration • Device : tinyAVR or megaAVR device belonging to core version avr25 • Belongs to a set of devices of group 1 supported by this library • Support a maximum of 8 channels • Supports a maximum of up to 2 rotors / sliders. 5.7.1.3.2 Naming convention for libraries to be used with IAR Embedded Workbench The libraries are named according the naming convention listed below lib g _qt_k_ rs.r90 Field name Possible values Comments coreP v1 v3 v3xmsf v3xm v4xm v5xm v6xm uc3a uc3b uc3c sam3s sam3u sam3n VersionP of the for AVR/ATSAM devices supported by this library variant variant for tinyAVR and megaAVR devices. Q 1 to 3 GroupQ of the core AVR device supported by this library variant CH 4, 8, 12, 16, 32 Total number of channels supported by each library. RS 1, 2, 3, 4, 8 Total number of rotors / sliders supported for the respective channel counts mentioned in previous row. For example, the library variant “libv3g2_4qt_k_1rs.r90” supports the following configuration • Device : tinyAVR or megaAVR device belonging to core version v3 • Belongs to a set of devices of group 2 supported by this library • Supports a maximum of 4 channels • Supports 1 rotor/slider 5.7.1.4 QTouch acquisition method library variants lists the different QTouch acquisition method library variants supported for AVRs. Use this table to select the correct library variant to be used in your application. Each row in the table below indicates • the corresponding Ports available for SNS and SNSK pins • Compilers used for generating the libraries • The library names to be selected for the requirements Note: The libraries that are supported as listed in the table are only supported provided the device memory requirements are also satisfied.81 Naming convention of the library Maximum channels supported by the library. Device Range tinyAVR, megaAVR, XMEGA 4,8,12,16 UC3 8,16,32 ATSAM 32 Maximum number of rotor / sliders supported NOTE: • For 8-bit devices, ports which have less than 8 pins cannot be used by the QTouch acquisition method libraries. Check the data sheet to determine the number of pins supported for each port 5.7.1.5 Port combinations supported for SNS and SNSK pin configurations For the list of all ports supported for each device please refer to the library selection guide. There are no limitations for AVR devices (8bit and 32 bit) on the combination of SNS and SNSK port to be used from QTouch libraries 4.0 release onwards. For ATSAM devices the one port pair combinations supported are given below in the table. One port pair supported combinations for ATSAM AA, BB, CC, AB, BA, AC, CA, BC, CB 5.7.1.5.1 Tips on pin assignments for the sensor design using one pair of SNS/SNSK ports This section lists tips on selecting the pin assignments when using a single port pair for the SNS and SNSK Pins. Design choice for the sensor Example Port configuration with pin assignments SNSK & SNS pins are on different ports, number of channels = 4 • If the SNS1(C) and SNSK1(B) pins are on two different ports, the user should mount the sensors onto the corresponding pins such as (PC0,PB0), (PC1,PB1), (PC2,PB2) and (PC3,PB3), when pin configurability is not used. • In case of pin configurability, sensors should be mounted on the pins as selected based on rules illustrated in section 5.8.1 SNSK & SNS pins are on different ports, number of channels = 8 • If the SNS1(C) and SNSK1(B) pins are on two different ports, the user should mount the sensors onto the corresponding pins such as (PC0,PB0), (PC1,PB1), (PC2,PB2) and so on, When pin configurability is not used. • When using pin configurability, sensors should be mounted on the pins as selected based on rules illustrated in section 5.8.1 • When pin configurability is not used, channel 0 will be on (PC0, PB0) pins, channel 1 will be on (PC1, PB1) pins and so on up to channel 7 will be on (PC7, PB7) pins. • When using pin configurability, channel should be assigned as given in section 5.6.6.1.1.282 8207L-AT42-05/12 • SNSK & SNS pins are on different ports, number of channels = 32 when using UC3 device • If the SNS1(B) and SNSK1(A) pins are on two different ports, the user should mount the sensors onto the corresponding pins such as (PB0,PA0), (PB1,PA1), (PB2,PA2).. • In this case channel 0 will be on (PB0, PA0) pins, channel 1 will be on (PB1, PA1) pins and so on up to channel 31 will be on (PB31, PA31) pins. SNSK & SNS pins are on the same port, number of channels = 2 • If the use of SNS1(A) and SNSK1(A) pins are on the same port, the user should always have the configuration (PA0, PA1) & (PA2, PA3). In this case channel 0 will be on (PA0, PA1) pins; channel 1 will be on (PA2, PA3) pins. The even pins of the port are used as SNS1 pins and odd pins of the port are used as SNSK1 pins • When pin configurability is used, sensors should be mounted on the pins as selected as per the rules illustrated in section 5.8.1 and channels should be assigned as given in section 5.6.6.1.1.4 SNSK & SNS pins are on the same port, number of channels = 4 • If the use of SNS1(A) and SNSK1(A) pins are on the same port, the user should always have the configuration (PA0, PA1), (PA2, PA3), (PA4, PA5) & (PA6, PA7). In this case channel 0 will be on (PA0, PA1) pins, channel 1 will be on (PA2, PA3) pins and so on up to channel 4 will be on (PA6, PA7) pins. The even pins of the port are used as SNS1 pins and odd pins of the port are used as SNSK1 pins, when pin configurability is not being used. • When using pin configurability, sensors should be mounted on the pins as selected as per the rules illustrated in section 5.8.1 and channels should be assigned as given in section 5.6.6.1.1.4 SNSK & SNS pins are on the same port, number of channels = 16 ( Available only for UC3 devices if more than 4 channels are to be used on a single port. For tinyAVR, megaAVR, XMEGA devices up to 8 channels with SNS and SNSK on same ports refer to section 5.7.1.5.2 ) • This configuration is available only for UC3 library variants. • In the use of SNS(A) and SNSK(A) pins are on the same port, the user should always have the configuration (PA0, PA1), (PA2, PA3), (PA4, PA5) & so on. In this case channel 0 will be on (PA0, PA1) pins, channel 1 will be on (PA2, PA3) pins and so on up to channel 15 will be on (PA30, PA31) pins. The even pins of the port are used as SNS pins and odd pins of the port are used as SNSK pins SNSK & SNS pins are on the same port, number of channels = 16 ( Available only for SAM devices) • If the use of SNS(A) and SNSK(A) pins are on the same port, the user should always have the configuration (PA0, PA1), (PA2, PA3), (PA4, PA5), (PA6, PA7) and so on. • In this case channel 0 will be on (PA0, PA1) pins, channel 1 will be on (PA2, PA3) pins and so on up to channel 15 will be on (PA30, PA31) pins. • The even pins of the port are used as SNS pins and odd pins of the port are used as SNSK pins83 5.7.1.5.2 Port combinations supported for two port pair SNS and SNSK pin configurations For the list of all ports supported for each device please refer to the library selection guide. There are no limitations on the combination of SNS and SNSK port to be used from QTouch libraries 4.0 release onwards. For ATSAM devices the total two port pairs supported combinations are given below in the table. Two port pairs supported combinations for ATSAM AA_BB, BB_AA, AA_CC, CC_AA, BB_CC, CC_BB, AA_BC, AA_CB, BB_AC, BB_CA, CC_BA, CC_AB 5.7.1.5.2.1 Tips on pin assignments for the sensor design using two pairs of SNS / SNSK ports This section lists tips on selecting the pin assignments when using a single port pair for the SNS and SNSK Pins. Design choice for the sensor Example Port configuration with pin assignments SNSK1-SNS1 & SNSK2-SNS2 pins are all on different ports, number of channels = 16 (Use the 16channel library in this case. Ensure the port definitions for SNS1,SNSK1,SNS2,SNSK2 are all in place) • E. g. SNS1(D), SNSK1(B) & SNS2(C), SNSK2(A) • Recommended configuration: (PD0, PB0), (PD1, PB1),..(PD7, PB7), (PC0,PA0).. to (PC7, PA7). In this case channel 0 will be on (PD0, PB0) pins, channel 1 will be on (PD1, PB1) pins, channel 8 will be on (PC0, PA0), channel 9 will be on (PC1, PA1) and so on up to channel 15 will be on (PC7, PA7) pins. • However, the user can mount the sensors on pins as selected as per the rules illustrated in section 5.8.1 and channels should be assigned as given in section 5.6.6.1.1.2 SNSK1-SNS1 are on same port & SNSK2-SNS2 pins are on same port, number of channels = 8 (Use the 8channel library in this case. Ensure the port definitions for SNS1,SNSK1,SNS2,SNSK2 are all in place) • E.g. SNS1(K), SNSK1(K) & SNS2(H), SNSK2(H) on same ports, • Recommended configuration: In case Pin configurability is not used, (PK0, PK1), (PK2, PK3),..(PK6, PK7), (PH0,PH1).. to (PH6, PH7).In this case channel 0 will be on (PK0, PK1) pins, channel 1 will be on (PK2, PK3) pins, channel 4 will be on (PH0, PH1), channel 5 will be on (PH2, PH3) and so on up to channel 7 will be on (PH6, PH7) pins. The even pins of the port are used as SNS pins and odd pins of the port are used as SNSK pins. • When pin configurability is used, sensors should be mounted on the pins as selected as per the rules illustrated in section 5.8.1 and channels should be assigned as given in section 5.6.6.1.1.2 SNSK1-SNS1 are on different ports & SNSK2-SNS2 pins are on same port, number of channels = 12 (Use the 12channel library in this case. Ensure the port definitions for SNS1,SNSK1,SNS2,SNSK2 are all in place) • E.g. SNS1(H), SNSK1(F) on different ports & SNS2(E), SNSK2(E) on same ports. • Recommended configuration : In case Pin configurability is not used, (PH0, PF0), (PH1, PF1),..(PH7, PF7), (PE0,PE1).. to (PE6, PE7). In this case channel 0 will be on (PH0, PF0) pins, channel 1 will be on (PH1, PF1) pins... channel 8 will be on (PE0,PE1), channel 9 will be on (PE2,PE3) and so on up to channel 11 will be on (PH6, PH7) pins. The even pins of the port E are used as SNS pins and odd pins of the port E are used as SNSK pins. • When pin configurability is used, sensors should be mounted on the pins as selected as per rules illustrated in section 5.8.1 and channels should be assigned as given in section 84 8207L-AT42-05/12 5.6.6.1.1.2 and section 5.6.6.1.1.4 SNSK1-SNS1 are on same port & SNSK2-SNS2 pins are on different ports, number of channels = 12 (Use the 12channel library in this case. Ensure the port definitions for SNS1,SNSK1,SNS2,SNSK2 are all in place) • E.g. SNS1(G), SNSK1(G) on different ports & SNS2(B), SNSK2(D) on same ports • Recommended configuration: In case Pin configurability is not used, (PG0, PG1), (PG2, PG3),..(PG6, PG7), (PB0,PD0)... to (PB7, PD7). In this case channel 0 will be on (PG0, PG1) pins, channel 1 will be on (PG2, PG3) pins... channel 3 will be on (PG6, PG7), channel 4 will be on (PB0,PD0) and so on up to channel 11 will be on (PB7, PD7) pins. The even pins of the port G are used as SNS pins and odd pins of the port G are used as SNSK pins • When pin configurability is used, sensors should be mounted on the pins as selected as per rules illustrated in section 5.8.1 and channels should be assigned as given in section 5.6.6.1.1.2 and section 5.6.6.1.1.4 5.7.1.6 Sample applications and Memory requirements for QTouch acquisition method libraries Refer to the library selection guide for memory requirements for each of the libraries supported in the release. 5.7.2 QMatrix acquisition method library variants 5.7.2.1 Introduction Variants of the ATMEL QTouch Library based on Matrix™ acquisition technology are available for a range of ATMEL Microcontrollers. Refer to the library selection guide (C:\ Program Files\Atmel\ Atmel_QTouch_Libaries_5.x\Library_Selection_Guide.xls) for the list of devices currently supported for QMatrix. 5.7.2.2 Support for different compiler tool chains The QMatrix acquisition method libraries are supported for the following compiler tool chains. Tool Version IAR Compiler 6.10 IAR Embedded Workbench 6.10 Atmel Studio 6 6.0.x GCC – GNU Toolchain for AVR 3.4.0.1028 IAR Compiler 32bit AVR 4.10.1 GCC – GNU Toolchain for AVR32 3.4.0.1028 5.7.2.3 QMatrix Acquisition method library naming conventions The libraries are named according the naming convention listed below Tool Chain Naming convention GCC Tool Chain lib _ qm_ x_ y_ _ rs.a IAR –EWAR lib _ qm_ x_ y_ _ rs.r9085 Field name Possible values Comments D Common for IAR & GCC: ATtiny167, ATmega128rfa1, ATmega8535 Specific to IAR: v1g1s0 (ATtiny44, ATtiny84) v1g1s1 (ATtiny48, ATtiny88) v1g1s2(ATtiny461, ATtiny861) ATmega16a v1g2s1 (ATmega48PA, ATmega88PA) v3xmsf (ATxmega16A4, ATxmega16D4, ATxmega32A4, ATxmega32D4) v3xm (ATxmega64A3) v4xm(ATxmega64A1) v5xm(ATxmega128A3, ATxmega192A3, ATxmega256A3, ATxmega256A3B) v6xm(ATxmega128A1) v3g3 (ATmega165P, ATmega325P, ATmega645, ATmega164p, ATmega324p, ATmega324pa, ATmega644p, ATmega168p, ATmega328p, AT90CAN32, AT90CAN64 ) v3g5 ( AT90CAN128, AT90USB1286, AT90USB1287, ATmega1280, ATmega1281 ) v3g6 ( AT90USB162 ) v3g7 ( AT90USB646, Indicates the device / core group name in short form. For XMEGA Devices, Core groups are taken which follows As below for both GCC and IAR Supported XMEGA Devices ATxmega16A4, ATxmega16D4, ATxmega32A4, ATxmega32D4, ATxmega64A1 ATxmega128A1 ATxmega64A3 ATxmega128A3, ATxmega192A3, ATxmega256A3, ATxmega256A3B)86 8207L-AT42-05/12 AT90USB647 ) Specific to GCC: avr25g1s0 (ATtiny44, ATtiny84) avr25g1s1 (ATtiny48, ATtiny88) avr25g1s2(ATtiny461, ATtiny861) ATmega16 avr4g1s1 (ATmega48P, ATmega88P) avr5g4 ( AT90USB646, AT90USB647 ) avr5g6 ( AT90USB162 ) avrxmega2 (ATxmega16A4, ATxmega16D4, ATxmega32D4) avrxmega3 (ATxmega32A4) avrxmega4 (ATxmega64A3) avrxmega5(ATxmega64A1) avrxmega6(ATxmega128A3, ATxmega192A3, ATxmega256A3, ATxmega256A3B) avrxmega7(ATxmega128A1) avr5g3 (ATmega165P, ATmega325P, ATmega645, ATmega164p, ATmega324p, ATmega324p, ATmega644p, ATmega168p, ATmega328p, AT90CAN32, AT90CAN64 ) avr51g2 ( AT90CAN128, AT90USB1286, AT90USB1287, ATmega1280, ATmega1281 ) AT32UC3C0512 NC 4,8,16,24,32,56,64 Indicates the maximum number of channels that the 87 library supports 56 (8 x 7) support only for ATXmega Devices. 24((8 x 3) support only for 32 Bit Devices. NX 4,8 Indicates the number of X-Lines that the library needs for supporting the listed number of channels. The X lines on a PORT always start with Least Significant Bit of the PORT. Ex: #define PORT_X_1 B in case of a 4x2 QMatrix library means X0,X1,X2,X3 are on PB0,PB1,PB2,PB3 NY 1,2,3,4,7,8 Indicates the number of Y-Lines that the library needs for supporting the listed number of channels NY=7 support only for ATXmega Devices NY=3 support only for 32Bit Devices CFG k krs k – library variant supports only keys krs – library variant supports keys, Rotors and Sliders NRS 0,1,2,3,4,8 Maximum number of rotor sliders that the library supports. NRS=3 support only for 32Bit Devices The table below provides a few examples of the naming convention. Example Library name Configuration supported libavr51g2_8qm_4x_2y_krs_2rs.a • Compiler tool chain : GCC • Device : ATMega164P • 8 Channels • 4 X lines • 2 Y lines • Supports Keys, Rotors and Sliders ( krs ) • 2 Rotors and Sliders libavr25g1s1_16qm_8x_2y_k_0rs.r90 • Compiler tool chain : IAR • Device : ATTiny88 • 16 Channels • 8 X lines • 2 Y lines • Supports only keys ( k) • 0 Rotors and Sliders 5.7.2.4 QMatrix acquisition method library variants 5.7.2.4.1 Devices supported for QMatrix Acquisition Refer to the Library_selection_guide.xls for the list of devices supported for QMatrix for this release. 5.8 PIN Configuration for QTouch Libraries 5.8.1 Pin Configuration for QTouch Acquisition Method Pin configurability for QTouch acquisition method is provided for 8Bit AVR’s. QTouch acquisition method libraries can be used to configure SNS and SNSK on any pins of the port. But few rules should be followed while assigning the SNS and SNSK on particular pins. These rules are internal to the library. But QTouch Studio –Pin Configuration Wizard 88 8207L-AT42-05/12 can be used to assign SNS and SNSK on the pins and rules are internally taken care in the QTouch Studio Pin Configuration Wizard. By default, for 4 and 8 channel QTouch acquisition libraries, the channel numbering follows the pin number of the port. To use the pin configurability, enable the macro _STATIC_PORT_PIN_CONF_ in the project options or define the macro in the touch_config.h file. To use the pin configurability feature, the SNS_array and SNSK_array masks are exported for the user, which needs to be initialized. These SNS_array and SNSK_array masks can be taken from the QTouch Studio Pin Configuration Wizard and can be copied at appropriate place in the main.c file as explained in the example projects provided. QTOUCH_STUDIO_MASKS macro is used for providing pin configurability feature for QTouch Acquisition method libraries. In case the macro QTOUCH_STUDIO_MASKS enabled in project space, SNS_array and SNSK_array takes values that are supplied by the user in main.c files. This will reduce the code memory foot print of the library. In case the macro QTOUCH_STUDIO_MASKS is not enabled in project space, SNS_array and SNSK_array are calculated internal to the library according to the configured sensors. Note: 1. Port pin configurability is enabled for the following configurations, 4- channel intraport configuration 8-channel intraport configuration 12-channel configuration 16- channel configuration 2. In case, the user wants to use the pin configurability for the other supported configurations, (4- channel interport and 8-channel interport), the user has to enable the macro _STATIC_PORT_PIN_CONF_ in his project space. 5.8.1.1 Rules for configurable SNS-SNSK Mask Generation X X X SNS1=PORTA PORT PAIR 1 Ch2 Ch1 Ch0 X X X SNSK1=PORTB89 X X X SNS2=PORTC PORT PAIR 2 Ch5 Ch4 Ch3 X X X SNSK2=PORTD 1. The channel numbers are allocated based on enabled SNS pins starting from LSBit of port 1(SNS1) and ending with MSBit of port 2(SNS2). 2. The number of SNS pins in a port pair should be equal to the SNSK pins in the same port pair so it can form a pair. 3. The first SNS port pin should always be mapped to the first SNSK port pin in any port pair. Similarly the second SNS port pin should always be mapped to second SNSK pin and so on. 4. Even sensors with in a port pair should be placed in one mask and odd sensors with-in a port pair should be placed in the second mask. In case of interport, first channel should always start with odd masks and then even masks is filled . 5. All the three channels for ROTORS and SLIDERS should be placed within the same mask. And should be in the same port pair. 6. Keys on adjacent channels should be placed on different masks. 7. For 8 channel case when 2 ports are enabled, the pins for the 8 channels can be spread on the 2 ports. The pin configuration is done based on the rules mentioned above. 8. For 16 channel case when 2 ports are enabled, all the pins for the 16 channels are allocated among the pins of the 2 ports. 5.8.1.1.1 Example for 8 channel interport mask Calculation with one port pair X X X SNS1=PORTA Ch2 Ch1 Ch0 X X X SNSK1=PORTB This example is for interport 8 channel library with only one port pair used. Channel0 is A0B2,Channel1 is A3B5 and Channel2 is A6B7 are enabled for the 8 channel library. The SNS_array and SNSK_array masks are calculated by the Qtouch Studio with rules mentioned above. In this case, the SNS_array and SNSK_array values will be as mentioned below:90 8207L-AT42-05/12 SNS_array[0][0]=0x41; (SNS even mask for port pair 1) SNS_array[0][1]=0x08; (SNS odd mask for port pair 1) SNS_array[1][0]=0x00; (SNS even mask for port pair 2) SNS_array[1][1]=0x00; (SNS odd mask for port pair 2) SNSK_array[0][0]=0x84; (SNSK even mask for port pair 1) SNSK_array[0][1]=0x20; (SNSK odd mask for port pair 1) SNSK_array[1][0]=0x00; (SNSK even mask for port pair 2) SNSK_array[1][1]=0x00; (SNSK odd mask for port pair 2) As there is no second port pair used for this, so that’s why SNS_array[1][0], SNS_array[1][1], SNSK_array[0][1] and SNSK_array[1][1] are having value zero. 5.8.1.1.2 Example for 8 channel intraport mask Calculation with two port pairs X X X SNS1=PORTA Ch2 Ch1 Ch0 X X X SNSK1=PORTA X X X SNS2=PORTB Ch5 Ch4 Ch3 X X X SNSK2=PORTB This example is for intraport 8 channel library with two port pair used. Channel0 is A1A3,Channel1 is A4A5 and Channel2 is A6A7 are enabled in the first port pair. Channel3 is B1B2,Channel4 is B3B4 and Channel5 is B5B6 are enabled in the second port pair. The SNS_array and SNSK_array masks are calculated by the Qtouch Studio with rules mentioned above. In this case, the SNS_array and SNSK_array values will be as mentioned below:91 SNS_array[0][0]=0x52; (SNS even mask for port pair 1) SNS_array[0][1]=0x00; (SNS odd mask for port pair 1) SNS_array[1][0]=0x2a; (SNS even mask for port pair 2) SNS_array[1][1]=0x00; (SNS odd mask for port pair 2) SNSK_array[0][0]=0xa8; (SNSK even mask for port pair 1) SNSK_array[0][1]=0x00; (SNSK odd mask for port pair 1) SNSK_array[1][0]=0x54; (SNSK even mask for port pair 2) SNSK_array[1][1]=0x00; (SNSK odd mask for port pair 2) In case of Intraport, odd SNS_array and SNSK_array masks are always zero.So that’s why SNS_array[0][1] ,SNS_array[1][1], SNSK_array[0][1] and SNSK_array[1][1] are zero for both the port pairs. 5.8.1.1.3 Example for 12 channel intraport-interport mask Calculation with two port pairs X X X SNS1=PORTA Ch2 Ch1 Ch0 X X X SNSK1=PORTA X X X SNS2=PORTB Ch5 Ch4 Ch3 X X X SNSK2=PORTD This example is for intraport-interport 12 channel library with two port pair used. Channel0 is A1A3,Channel1 is A4A5 and Channel2 is A6A7 are enabled in the first port pair. Channel3 is B1D2,Channel4 is B3D4 and Channel5 is B5D6 are enabled in the second port pair. The SNS_array and SNSK_array masks are calculated by the Qtouch Studio with rules mentioned above. In this case, the SNS_array and SNSK_array values will be as mentioned below:92 8207L-AT42-05/12 SNS_array[0][0]=0x52; (SNS even mask for port pair 1) SNS_array[0][1]=0x00; (SNS odd mask for port pair 1) SNS_array[1][0]=0x22; (SNS even mask for port pair 2) SNS_array[1][1]=0x08; (SNS odd mask for port pair 2) SNSK_array[0][0]=0xa8; (SNSK even mask for port pair 1) SNSK_array[0][1]=0x00; (SNSK odd mask for port pair 1) SNSK_array[1][0]=0x44; (SNSK even mask for port pair 2) SNSK_array[1][1]=0x10; (SNSK odd mask for port pair 2) As the first port pair is intraport, so that’s why SNS_array[0][1] and SNSK_array[0][1] are zero as odd masks are always zero in case of Intraport. 5.8.1.1.4 Example for 16 channel intreport-interport mask Calculation with two port pairs X X X SNS1=PORTA PORT PAIR 1 Ch2 Ch1 Ch0 X X X SNSK1=PORTB X X X SNS2=PORTC PORT PAIR 2 Ch5 Ch4 Ch3 X X X SNSK2=PORTD This example is for interport-interport 16 channel library with two port pair used. Channel0 is A2B0,Channel1 is A4B3 and Channel2 is A5B6 are enabled in the first port pair. Channel3 is C1D2,Channel4 is C3D3 and Channel5 is C5D4 are enabled in the second port pair. The SNS_array and SNSK_array masks are calculated by the Qtouch Studio with rules mentioned above.93 In this case, the SNS_array and SNSK_array values will be as mentioned below: SNS_array[0][0]=0x24; (SNS even mask for port pair 1) SNS_array[0][1]=0x10; (SNS odd mask for port pair 1) SNS_array[1][0]=0x22; (SNS even mask for port pair 2) SNS_array[1][1]=0x08; (SNS odd mask for port pair 2) SNSK_array[0][0]=0x41; (SNSK even mask for port pair 1) SNSK_array[0][1]=0x08; (SNSK odd mask for port pair 1) SNSK_array[1][0]=0x14; (SNSK even mask for port pair 2) SNSK_array[1][1]=0x08; (SNSK odd mask for port pair 2) 5.8.1.2 How to Use QTouch Studio For Pin Configurability Note: The Qtouch Composer is available for few select set of devices.But user can use Qtouch Studio 4.4 for the devices which are not supported in Qtouch Composer. The following steps describe the details on how to use pin configurability for QTouch Acquisition method: 1. Open AVR QTouch Studio .Enable the Design Mode Radio button on the left hand side of the screen. Figure 5-22 Selecting the Design mode in the AVR QTouch Studio 1. Go to File Menu option and click New Design.94 8207L-AT42-05/12 Figure 5-23 Selecting the New Design in the AVR QTouch Studio 2. In the Create New Design Window, give the Project name and Kit Technology (QTouch in this case) and and Number of sensors (Keys/Rotors/Sliders) and click Create Design. Figure 5-24: Creating New Design in the AVR QTouch Studio 3. After Creating Design, the new screen pops up which shows all the sensors which have been created.95 Figure 5-25: New Design Sensors in the AVR QTouch Studio virtual kit 4. Now Go to Tools->Pin Configuration Wizard.Pin configuration Figure 5-26: Selecting the pin configuration wizard for theDesign 5. Pin configuration Window will pop up with the information on the usage of the tool. Click Next to proceed to the configuration.96 8207L-AT42-05/12 Figure 5-27: : Start page of the wizard 6. Select the MCU and click Next as shown below.97 Figure 5-28: Selecting the MCU for the New Design 7. Select the SNS and SNSK ports needs for the design and click Next. Figure 5-29: Selecting SNS and SNSK ports in the New Design98 8207L-AT42-05/12 8. Select the pins used for the design and click Next If there is error in the selection of the pins (Ex: conflictin pins used), a red marker will be appear and the user cannot proceed to next step in configuration until the user has done the correct pin selection. Now once the selection is done without errors, Click Next Figure 5-30: Selecting the SNS and SNSK Port Pins in the new Design( With Error)99 Figure 5-31: Selecting the SNS and SNSK Port Pins in the new Design( Without Error) Once the pins are selected, Pin Wizard will provide the summary report .Check whether details are correct as specified.Click Next Figure 5-32: Summary report100 8207L-AT42-05/12 Figure 5-33: Code Generation tab in Pin Configuration wizard 9. In the New Window Screen, the code is shown on the screen.QTOUCH_STUDIO_MASKS needs to be enabled in the project option or in touch_ config.h file. And in the main.c file, this code SNS_array and SNSK_array needs to be copied from here and put under QTOUCH_STUDIO_MASKS macro as shown below in the main.c file: #ifdef QTOUCH_STUDIO_MASKS SNS_array[0][0]=0x09; SNS_array[0][1]=0x22; SNS_array[1][0]=0x00; SNS_array[1][1]=0x00; SNSK_array[0][0]=0x14; SNSK_array[0][1]=0x88; SNSK_array[1][0]=0x00; SNSK_array[1][1]=0x00; #endif Note: 1. To use 4 and 8 channel libraries(interport case) for pin configurability , _STATIC_PORT_PIN_CONF_ macro needs to be enabled in the touch_config.h file.101 2. QTOUCH_STUDIO_MASKS needs to be enabled if using pin configurability .If not enabled then, static pin mapping will work same as in the earlier versions of the libraries 5.8.2 Pin Configuration for QMatrix Acquisition Method The QMatrix acquisition method libraries needs to be used after configuring X and YA and YB lines on IO pins of the port as described in the configuration rules described in the section below. The QTouch Studio Pin Configurator Wizard can be used to assign X, YA, YB, SMP lines on the pins and rules are internally taken care in the Qtouch Studio Pin Configurator Wizard. The snippets can be taken from the QTouch Studio Pin Configurator Wizard and copied to appropriate places in the main.c and touch_ config.h files in the example projects provided. 5.8.2.1 Configuration Rules: 1. The X lines can be configured on different ports up to a maximum of 3 ports Ex: NUM_X_PORTS = 3 (maximum value supported). However the possible values are NUM_X_PORTS = 1 or NUM_X_PORTS = 2 or NUM_X_PORTS = 3 2. The X lines can be configured on the three different ports. 3. The X lines can be configured on any pins of the ports selected above Ex: X0 on PB2, X1 on PD5, X2 on PE0, X3 on PD1( when NUM_X_LINES= 4), Provided that these pins do not conflict with the other pins for touch sensing or with the host application usage. 4. The Y lines can be configured on the any of the pins of the ports selected Ex: Any pins on the PORT_YA and PORT_YB selected. Suppose, PORT_YA is D, and PORT_YB is C Since, pin 5 and pin 1 PORTD are already used for X lines(X1, X3), the user can select any of the remaining pins for Y0A lines. Suppose that Y0 is on pin2 and Y1 is on pin6 Hence, Y0A – PD2, Y0B – PC2, Y1A – PD6, Y1B – PC6, 5. All the Qmatrix usage Pins X lines,YA lines, YB lines and SMP line can be on same port.Both YA and YB lines can share the same port. And the YA and YB need not be on same corresponding pins of the ports.The Macro SHARED_YAYB should be defined as 1 if YA and YB are on same port else should be defined as 0. 6. The PORT_YB is fixed for each device and should be same as the PORT on which the ADC input pins are available. 7. The SMP pin can be configured on any of the IO PORT pins available. Ex: PORT_SMP = D SMP_PIN = 7 as this pin is not being used by touch sensing. Note: Please take care that the touch sensing pins do not conflict with other IO pins used by host application 102 8207L-AT42-05/12 5.8.2.2 How to use QTouch Studio for Pin Configurability: Note: The Qtouch Composer is available for few select set of devices.But user can use Qtouch Studio 4.4 for the devices which are not supported in Qtouch Composer. Also YA,YB shared on same port feature is available in Qtouch Composer and not available in Qtouch Studio 4.4.Please refer section 5.6.10.3 The following steps describe the details on how to use pin configurability for QMatix Acquisition method: 1. Open AVR Qtouch Studio .Enable the Design Mode Radio button on the left hand side of the screen.. Figure 5-34: Selecting the Design mode in the AVR QTouch Studio 2. Go to File Menu option and click New Design103 Figure 5-35: Selecting New Design 3. In the Create New Design Window, give the Project name and Kit Technology (QMatrix in this case) and Number of sensors (Keys/Rotors/Sliders) and click Create Design. Figure 5-36 Creating New Design in the AVR QTouch Studio104 8207L-AT42-05/12 After Creating Design , the new design mode shows the virtual kit view with sensors that have been created in some order. Figure 5-37: New Design Sensors in the AVR QTouch Studio 4. Now Go to Tools->Pin Configuration Wizard as shown below. Figure 5-38: Selecting the pin configuration wizard 5. Pin configuration Window will pop up with the information on the usage of the tool. Click Next to proceed.105 Figure 5-39: Start window of the configuration wizard 6. .Select the MCU and click Next as shown below. Figure 5-40: MCU selection window from the configuration wizard. 7. Select the Channels needed for the design from the list provided and click Next.106 8207L-AT42-05/12 If 6 channels are needed, the next immediate value that suits the design needs to be selected. Ie., 8 channels (4 x 2 ) configuration. Figure 5-41: Selecting channels and configuration in the New Design 8. Select the pins used for the design and click Next. If there is error in the selection of the pins (Ex: conflictin pins used), a red marker will be appear and the user cannot proceed to next step in configuration until the user has done the correct pin selection. Now once the selection is done without errors, Click Next.107 Figure 5-42: Selecting the X,YA,YB,SMP Pins in the new Design with errors. Figure 5-43: Selecting the X,YA,YB,SMP Pins in the new Design without errors. Once the pins are selected, Pin Wizard will provide the summary report .Check whether details are correct as specified.Click Next.108 8207L-AT42-05/12 If there are some errors that are found in the summary report, the user can click “back” button and modify the changes needed. Figure 5-44: Summary report Figure 5-45: Code Generation tab in Pin Configuration wizard 9. The code is shown in the New Window Screen. Note: Use FILL_OUT_YA_LINE_INFO and FILL_OUT_YB_LINE_INFO code instead of 109 FILL_OUT_Y_LINE_INFO as now YA and YB can be shared on same port. The code can be copied using the “copy code” and pasted in the main.c and touch_config .h file, a. In touch _config.h, Copy the following header definitions as part of the preprocessor directives in the project space or in the beginning of the file #define NUM_X_PORTS 2 #define PORT_X_1 B #define PORT_X_2 D #define PORT_YA D #define PORT_YB C #define SMP_PORT D #define SMP_PIN 7 #define SHARED_YAYB 0 b. In main.c , Copy the code as below x_line_info_t x_line_info[NUM_X_LINES]= { FILL_OUT_X_LINE_INFO(1,1); FILL_OUT_X_LINE_INFO(2,2); FILL_OUT_X_LINE_INFO(1,3); FILL_OUT_X_LINE_INFO(2,0); }; y_line_info_t ya_line_info[NUM_Y_LINES]= { FILL_OUT_YA_LINE_INFO(1); FILL_OUT_YA_LINE_INFO(3); }; y_line_info_t yb_line_info[NUM_Y_LINES]= { FILL_OUT_YB_LINE_INFO(1); FILL_OUT_YB_LINE_INFO(3); }; Note: If YA,YB shared on same port feature is needed , then apart from the above Macros #define SHARED_YAYB needs to be enabled as 1. 5.9 MISRA Compliance Report This section lists the compliance and deviations for MISRA standards of coding practice for the QTouch and QMatrix acquisition method libraries.110 8207L-AT42-05/12 5.9.1 What is covered The QTouch and QMatrix acquisition method libraries adhere to the MISRA standards. The additional reference code provided in the form of sample applications is not guaranteed to be MISRA compliant. 5.9.2 Target Environment Development Environment IAR Embedded Workbench MISRA Checking software The MISRA C Compliance has been performed for the library using MISRA C 2004 Rules in IAR Workbench development environment. MISRA Rule set applied MISRAC 2004 Rule Set 5.9.3 Deviations from MISRA C Standards 5.9.3.1 QTouch acquisition method libraries The QTouch acquisition method libraries were subject to the above mentioned MISRA compliance rules. The following exceptions have not been fixed as they are required for the implementation of the library. Applicable Release QTouch libraries version 5.0 Rule No Rule Description Exception noted / How it is addressed 1.1 Rule states that all code shall conform to ISO 9899 standard C, with no extensions permitted. This Rule is not supported as the library implementation requires IAR extensions like __interrupt. These intrinsic functions relate to device hardware functionality, and cannot practically be avoided. 10.1 Rule states that implicit conversion from Underlying long to unsigned long The library uses macros to combine symbol definitions to form a unique expanded symbol name and in this, the usage of unsigned qualifiers for numeric constants (e.g. 98u) causes name mangling. This is the only occurrence of this error in the library. 10.6 This Rule says that a 'U' suffix shall be applied to all constants of 'unsigned' type The library uses macros to combine symbol definitions to form a unique expanded symbol name and in this, the usage of unsigned qualifiers for numeric constants (e.g. 98u) causes name mangling. This is the only occurrence of this error in the library. 14.4 Rule states that go-to statement should not be used. The library uses conditional jump instructions to reduce the code footprint at a few locations and this is localized to small snippets of code. Hence this rule is not supported. 19.10 Rule states that In the definition of a function-like macro, each instance of a parameter shall be enclosed in parenthesis There is one instance where the library breaks this rule where two macro definitions are combined to form a different symbol name. Usage of parenthesis cannot be used in this scenario. 19.12 Rule states that there shall be at most one occurrence of the # or ## preprocessor operator in a single macro definition There is one instance in the library where this rule is violated where the library concatenates two macro definitions to arrive at a different definition. 111 5.9.3.2 QMatrix acquisition method libraries The QMatrix acquisition method software was subject to the above mentioned MISRA compliance rules. The following exceptions have not been fixed as they are required for the implementation of the library. Applicable release QTouch libraries ver 5.0 Rule No Rule Description Exceptions Reason 1.1 Rule states that all code shall conform to ISO 9899 standard C, with no extensions permitted. This Rule is not supported as the library implementation requires IAR extensions like __interrupt. These intrinsic functions relates to device hardware functionality, and cannot practically be avoided 10.1 Rule states that Illegal implicit conversion from Underlying long to unsigned long The library uses macros to combine symbol definitions to form a unique expanded symbol name and in this, the usage of unsigned qualifiers for numeric constants (e.g. 98u) causes name mangling. This is the only occurrence of this error in the library. 10.6 This Rule says that a 'U' suffix shall be applied to all constants of 'unsigned' type The library uses macros to combine symbol definitions to form a unique expanded symbol name and in this, the usage of unsigned qualifiers for numeric constants (e.g. 98u) causes name mangling. This is the only occurrence of this error in the library. 19.10 Rule states that In the definition of a function-like macro, each instance of a parameter shall be enclosed in parenthesis There is one instance where the library breaks this rule where two macro definitions are combined to form a different symbol name. Usage of parenthesis cannot be used in this scenario. 19.12 Rule states that there shall be at most one occurrence of the # or ## preprocessor operator in a single macro definition There is one instance in the library where this rule is violated where the library concatenates two macro definitions to arrive at a different definition. 5.10Known Issues Issue Cause Remedy / workaround Buiding QTouch Libraries Release 5.0 with WinAVR Compiler results in Linker Error. (Skipping Library libavrxxx.a, File not found). QTouch Libraries Release 5.0 are build with Atmel Studio6 Native Toolchain Flavor. Always use Native Toolchain Flavor (Advanced Tab in Project properties) setting in Atmel Studio6 for Building QTouch Library Release. The GCC example projects for QMatrix does not compile the delay cycles (QT_DELAY_CYCLES) above a value of 5 because of the preprocessor expansions. Recommended to remove UL from the preprocessor constants and in the chain of macros used for QT_DELAY_CYCLES. Valid for QT_DELAY_CYCLES = 5,10,25,50. Compiling QT600 project files throws These variables are available in 112 8207L-AT42-05/12 unused variable warning. the debug protocol for future use. When using IAR workbench for ATSAM to integrate the touch libraries, the linker would generate a warning indicating: Warning[Lp005]: placement includes a mix of sections with content (example "ro data section .data_init in xfiles.o(dl7M_tl_if.a)") and sections without content (example "rw data section .data in xfiles.o(dl7M_tl_if.a)") Warning[Lp006]: placement includes a mix of writable sections (example "rw data section .data in xfiles.o(dl7M_tl_if.a)") and non-writable sections (example "ro data section .data_init in xfiles.o(dl7M_tl_if.a)") This is because we link the library in RW data section. 5.11Checklist This section lists troubleshooting tips and common configuration tips. Symptom Cause Action Sensors do not go into detect or have unknown results Multiplexing pins used by QTouch libraries in your design Check the Pins used for QTouch or QMatrix acquisition methods do not overlap with the applications usage of the ports Signal values report arbitrary values Stray capacitance Check the sensor design and minimize stray capacitance interference in your design Waveforms of charging / discharging of channels do not show up properly in oscilloscopes JTAG ICE connected to the board Try disconnecting the JTAG ICE completely from the kit When using the example applications, the debug values for some of the channels does not display appropriate values JTAG Pins are enabled in the target. JTAG Pins are explicitly needs to be disabled in the main.c file /* disable JTAG pins */ MCUCR |= (1u << JTD); MCUCR |= (1u << JTD)113 6 Device Specific Libraries 6.1 Introduction This section provides an overview of the usage of Device specific QTouch Libraries. Device Specific Libraries have been provided for special devices, which are not covered as part of Generic Libraries. 6.2 Devices supported The following devices are covered by the Device Specific QTouch Libraries. 1. AT32UC3L0, AT32UCL3U/L4U family devices. 2. ATtiny10, ATtiny20 and ATtiny40 devices. 6.3 QTouch Library for AT32UC3L devices ATMEL QTouch Library for UC3L can be used for embedding capacitive touch buttons, sliders and wheels functionality into UC3L application. The QTouch Library for UC3L uses the Capacitive Touch Module (CAT) that senses touch on external capacitive touch sensors. This Section describes the QTouch Library Application Programming Interface (API) for QMatrix and QTouch method acquisition using the AT32UC3L devices. 6.3.1 Salient Features of QTouch Library for UC3L 6.3.1.1 QMatrix method sensor • N Touch Channels formed by an X by Y matrix require (X+2Y+1) physical pins (when using internal discharge mode), N=X*Y. Please refer Figure 37 for pin requirements in different modes. • 1 to 136 Touch Channels can be configured. • Max X Lines = 17, Max Y Lines = 8. • Button is formed using 1 Touch Channel. • Slider is formed using 3 to 8 Touch Channels. • Wheel is formed using 3 to 8 Touch Channels. 6.3.1.2 QTouch method sensor • 2 Physical pins per Touch Channel. • QTouch Sensors can be divided into two groups Group A and Group B. • Each QTouch group can be configured with different properties. • 1 to 17 Touch Channels can be configured. • Button is formed using 1 Touch Channel. • Slider is formed using 3 Touch Channels.114 8207L-AT42-05/12 • Wheel is formed using 3 Touch Channels. 6.3.1.3 Autonomous QTouch sensor • A Single QTouch sensor that is capable of detecting touch or proximity without CPU intervention. • Allows proximity or activation detection in low-power sleep modes. 6.3.1.4 Additional Features • Standalone QMatrix, QTouch Group A/B or Autonomous QTouch operation. • Support for operation of two or more methods at the same time. o Scenario 1: QMatrix and Autonomous QTouch method at the same time. o Scenario 2: QTouch Group A, QTouch Group B & Autonomous QTouch at the same time. o Scenario 3: QMatrix, QTouch Group A/B and Autonomous QTouch at the same time. • Disable/Re-enable Sensors at any given time for reduced power consumption. • Raw data acquisition mode without any post-processing of data. • External synchronization to reduce 50 or 60 Hz mains interference. • Spread spectrum sensor drive capability. • QTouch Studio-Touch Analyzer support to fine tune touch implementation. • IAR and GCC Tool chain support. • MISRA Compliant, MISRAC 2004 Rule Set. • Single Library for QMatrix, QTouch Group A/B and Autonomous QTouch methods. 6.3.2 Device variants supported for UC3L Below is the list of different devices in AT32UC3L family that is supported by the QTouch library. 1. AT32UC3L016, AT32UC3L032, AT32UC3L064 2. ATUC64L3U, ATUC128L3U, ATUC256L3U (Studio 6 Support only.) 3. ATUC64L4U, ATUC128L4U, ATUC256L4U (Studio 6 Support only.) For capacitive touch sensing module related information Refer to, “Capacitive touch module (CAT)” of the datasheet. 6.3.3 Development tool support for UC3L The QTouch libraries for AT32UC3L devices are supported for the following development tools. Tool Version IAR Embedded Workbench for Atmel AVR32. IAR32 Compiler. 4.1 Atmel Studio 6. GCC Compiler 6.0 Table 8 Development tool support for UC3L QTouch Library115 6.3.4 Overview of QTouch Library API for UC3L The diagram below captures the high level arrangement of the QTouch Library for UC3L API. The QTouch Library for UC3L API can be used for Sensor configuration, Sensor Acquisition parameter setting and Sensor Enable/Disable operations. Based on this input Sensor configuration, the QTouch Library takes care of the initialization, configuration and acquisition data capture operations using the CAT module. The UC3L CAT module interfaces with the external capacitive touch sensors and is capable of performing QTouch and QMatrix method acquisition. For an Overview of QMatrix and QTouch Capacitive Touch acquisition, refer Section 5.2. The raw acquisition data from the CAT module is processed by the QTouch Library. The Adjacent Key Suppression (AKS), Detect Integration mechanism, Drift compensation and Automatic Recalibration components of the Touch Library aid in providing a robust Touch performance. Once the raw acquisition data is processed, the individual Sensor Status and Wheel/Slider position information is provided to the user by means of a measurement complete callback operation. Figure 35 Overview diagram of QTouch Library for UC3L116 8207L-AT42-05/12 6.3.5 Acquisition method support for UC3L With the QTouch Library for UC3L, it is possible for a user to configure the following types of Sensors. • QMatrix method sensors. • QTouch Group A method sensors. • QTouch Group B method sensors. • Autonomous QTouch sensor. The QTouch Library for UC3L API has been arranged such that it is possible for the user application either to use any of the above method Standalone or two or more methods combined together. The Table below captures the different API available under each method. For normal operation, it is only required to use the Regular API set for each method. By using only the Regular API set, it is possible to achieve reduced code memory usage when using the QTouch Library. The Helper API is provided for added flexibility to the user application. Acquisition method Regular API Helper API QMatrix method API touch_qm_sensors_init touch_qm_sensor_config touch_qm_sensors_calibrate touch_qm_sensors_start_acquisition touch_event_dispatcher touch_qm_sensor_update_config touch_qm_sensor_get_config touch_qm_channel_update_burstlen touch_qm_update_global_param touch_qm_get_global_param touch_qm_get_libinfo touch_qm_sensor_get_delta touch_deinit QTouch Group A/B method API (The first parameter to the QTouch API, allows to distinguish between QTouch Group A and QTouch Group B.) touch_qt_sensors_init touch_qt_sensor_config touch_qt_sensors_calibrate touch_qt_sensors_start_acquisition touch_event_dispatcher touch_qt_sensor_update_config touch_qt_sensor_get_config touch_qt_update_global_param touch_qt_get_global_param touch_qt_get_libinfo touch_qt_sensor_get_delta touch_qt _sensor_disable touch_qt _sensor_reenable touch_deinit Autonomous QTouch API touch_at_sensor_init touch_at_sensor_enable touch_at_sensor_disable touch_at_sensor_update_config touch_at_sensor_get_config touch_at_get_libinfo touch_deinit Table 9 Acquisition method specific API 6.3.6 API State machine for UC3L The QTouch Library State machine diagram captures the different library States, Events that are allowed in each State and Event transition from one State to the other. The QTouch Library maintains the States of QMatrix, QTouch Group A and QTouch Group B methods independently. This means that QMatrix can be in a state that is different from the state of QTouch Group A or B and vice versa. 117 For the case of Autonomous QTouch, only the TOUCH_STATE_NULL and TOUCH_STATE_INIT states apply in the State diagram. • The touch_at_sensor_init event causes a transition from TOUCH_STATE_NULL to TOUCH_STATE_INIT. • The touch_deinit event causes a transition from TOUCH_STATE_INIT to TOUCH_STATE_NULL. Figure 36 State Diagram of QTouch Library for UC3L 6.3.7 QMatrix method sensor operation for UC3L 6.3.7.1 QMatrix method pin selection for UC3L Please refer AT32UC3L datasheet Table 28-2 Pin Selection Guide and Table 3-1 GPIO Controller Function multiplexing, for mapping between the QMatrix method pin name and the GPIO pin. It is possible to configure a maximum of 17 X Lines and 8 Y-Yk pairs. The X Line X8 (PA16) cannot be used for the QMatrix method as it is required to use this pin for the ACREFN function. The CAT module provides an option to enable a nominal output resistance of 1kOhm on specific CAT module pins during the burst phase. The Table below captures the different QMatrix method pin wherein a Resistive Drive can be optionally enabled. The rows marked with Grey indicate that Resistive Drive option is not available on that pin. By carefully choosing the QMatrix method TOUCH_ STATE_INIT TOUCH_ STATE_ NULL TOUCH_ STATE_ READY TOUCH_ STATE_BUSY touch_xx_sensors_init touch_xx_sensors_calibrate touch_xx_sensor_config touch_xx_sensor_get_config touch_xx_get_global_param touch_xx_get_libinfo touch_xx_sensor_update_config touch_xx_sensor_get_config touch_xx_update_global_param touch_xx_get_global_param touch_xx_get_sensor_delta touch_xx_get_libinfo touch_xx_get_libinfo QTouch Library for UC3L State Diagram TOUCH_ STATE_ CALIBRATE touch_deinit touch_deinit touch_deinit touch_qm_channel_udpate_burstlen touch_qt_sensor_disable touch_qt_sensor_reenable touch_qm_channel_udpate_burstlen touch_qt_sensor_disable touch_qt_sensor_reenable touch_xx_sensor_update_config touch_xx_sensor_get_config touch_xx_update_global_param touch_xx_get_global_param touch_xx_get_libinfo touch_xx_sensors_calibrate touch_xx_sensors_start_acquisition measure_complete_callback (provide measured data and touch status) touch_deinit xx = qm, qt Sensor state machine for QMatrix and QTouch GroupA/B118 8207L-AT42-05/12 X and Yk pins wherein Resistive Drive can be enabled, saving on external components is possible. Section 6.3.1.1 provides detail on the number of Pin and Touch channels required for different QMatrix method sensor. The hardware arrangement for Wheel or Slider must be such that all Touch channels corresponding to the Wheel or Slider belong to the same Yk Line. Also, Section 6.3.11 indicates the various Pin Configuration options for the QTouch Library that can be used to specify a user defined configuration. CAT Module Pin Name QMatrix method Pin Name CSA0 X0 CSB0 X1 CSA1 Y0 CSB1 YK0 CSA2 X2 CSB2 X3 CSA3 Y1 CSB3 YK1 CSA4 X4 CSB4 X5 CSA5 Y2 CSB5 YK2 CSA6 X6 CSB6 X7 CSA7 Y3 CSB7 YK3 CSA8 X8 CSB8 X9 CSA9 Y4 CSB9 YK4 CSA10 X10 CSB10 X11 CSA11 Y5 CSB11 YK5 CSA12 X12 CSB12 X13 CSA13 Y6 CSB13 YK6 CSA14 X14 CSB14 X15 CSA15 Y7 CSB15 YK7 CSA16 X16 CSB16 X17 Table 10 QMatrix Resistive drive pin option (The rows marked with Grey indicate that Resistive Drive option is not available on that pin) 6.3.7.2 QMatrix method Schematic for UC3L 6.3.7.2.1 Internal Discharge mode The CAT module provides an internal discharge arrangement for QMatrix method. When this arrangement is used along with the Resistive drive capability, minimal external component is required as shown in the case A of Figure 27. When the Resistive drive is option is not enabled, it is recommended to use 1kOhm resistors on X and Yk Lines external to the UC3L device. This hardware arrangement is shown in case B.119 6.3.7.2.2 External Discharge mode When the External Discharge arrangement is used, a logic-level (DIS) pin is connected to an external resistor (Rdis) that can be used to control the discharge of the Capacitors. A typical value for Rdis is 100 kOhm. This value of Rdis will give a discharge current of approximately 1.1V/(100 kOhm) = 11 microAmp. The case C shows this arrangement. The Resistive drive option on the X and Yk lines can be optionally enabled or disabled with this arrangement. When the Resistive drive is option is not enabled, it is recommended to use 1kOhm resistors on X and Yk Lines external to the UC3L device. 6.3.7.2.3 SMP Discharge Mode When the SMP Discharge mode arrangement is used, a logic-level (SMP) pin is connected to the capacitors through external high value resistors for the discharge of the capacitors. The case D shows this arrangement. The Resistive drive option on the X and Yk lines can be optionally enabled or disabled with this arrangement. When the Resistive drive is option is not enabled, it is recommended to use 1kOhm resistors on X and Yk Lines external to the UC3L device. 6.3.7.2.4 VDIVEN Voltage Divider Enable option The VDIV pin provides an option to make ACREFN a small positive voltage if required. The VDIV pin is driven when the analog comparators are in use, and this signal can be used along with a voltage divider arrangement to create a small positive offset on the ACREFN pin. The VDIVEN option can be used optionally with any of the QMatrix modes discussed in the previous sections. Typical values for Ra and Rb are Ra=8200 ohm and Rb = 50 ohm. Assuming a 3.3V I/O supply, this will shift the comparator threshold by 3.3V*(Rb/(Ra+Rb)) which is 20 mV. The VDIVEN pin option usage in the Internal Discharge mode scenario is shown in case E. 6.3.7.2.5 SYNC pin option In order to prevent interference from the 50 or 60 Hz mains line the CAT can optionally trigger QMatrix acquisition on the external SYNC input signal. The SYNC signal should be derived from the mains line and the acquisition will trigger on a falling edge of this signal. The SYNC pin option can be used with any of the QMatrix modes discussed in the previous sections. The SYNC pin usage in the Internal Discharge mode scenario is shown in case F. For QMatrix method SMP, DIS, VDIV and SYNC pin options discussed in this Section, Refer to Section 6.3.15.2.13. 120 8207L-AT42-05/12 Figure 37 QMatrix method schematic Atmel AT32UC3L Atmel AT32UC3L Atmel AT32UC3L Atmel AT32UC3L Atmel AT32UC3L Atmel AT32UC3L Sensors X, Y CAT CS0 Module ACIFBACREFN YmA Y0A Xn X2 Sensor n, 0 Sensor 0, m Sensor n, m Sensor 0, 0 CSm YmB Y0B Typical Values: CS:4.7nF n - number of X Lines m - number of Y Lines I/O Pin requirements: X: QMatrix method X Line YA: QMatrix method Yk Line YB: QMatrix method Y Line ACIFB-ACREFN: PA16 I/O pin ... ... A. QMatrix Internal Discharge mode arrangement. Resistive drive enabled on X and Yk Lines Sensors X, Y CS0 CAT Module ACIFBACREFN YmA Y0A Xn RXn X0 RX0 Sensor n, 0 Sensor 0, m Sensor n, m Sensor 0, 0 CSm YmB Y0B RXn RX0 ... ... ... B. QMatrix Internal Discharge mode arrangement. Resistive drive disabled on X and Yk Lines Sensors X, Y CS0 CAT Module ACIFBACREFN YmA Y0A Xn X2 Sensor n, 0 Sensor 0, m Sensor n, m Sensor 0, 0 CSm YmB Y0B DIS ... Rdis C. QMatrix External Discharge mode arrangement. Resistive drive enabled on X and Yk Lines ... Sensors X, Y CS0 CAT Module ACIFBACREFN YmA Y0A Xn RXn X0 RX0 Sensor n, 0 Sensor 0, m Sensor n, m Sensor 0, 0 CSm YmB Y0B RXn RX0 RYB0 RYBm SMP ... ... ... D. QMatrix SMP Discharge mode arrangement. Resistive drive disabled on X and Yk Lines Sensors X, Y CS0 CAT Module ACIFBACREFN YmA Y0A Xn X2 Sensor n, 0 Sensor 0, m Sensor n, m Sensor 0, 0 CSm YmB Y0B ... ... VDIVEN Ra Rb E. QMatrix Internal Discharge mode arrangement with Volage Divider option enabled. Resistive drive enabled on X and Yk Lines Sensors X, Y CS0 CAT Module ACIFBACREFN YmA Y0A Xn X2 Sensor n, 0 Sensor 0, m Sensor n, m Sensor 0, 0 CSm YmB Y0B ... ... SYNC Synchronize signal F. QMatrix Internal Discharge mode arrangement with External Sync option enabled. Resistive drive enabled on X and Yk Lines Typical Values: CS:4.7nF RX: 1kOhm n - number of X Lines m - number of Y Lines I/O Pin requirements: X: QMatrix method X Line YA: QMatrix method Yk Line YB: QMatrix method Y Line ACIFB-ACREFN: PA16 I/O pin Typical Values: CS:4.7nF Rdis: 100kOhm n - number of X Lines m - number of Y Lines I/O Pin requirements: X: QMatrix method X Line YA: QMatrix method Yk Line YB: QMatrix method Y Line DIS: CAT-DIS IO pin ACIFB-ACREFN: PA16 I/O pin Typical Values: CS:4.7nF RX: 1kOhm RYB: 1kOhm n - number of X Lines m - number of Y Lines I/O Pin requirements: X: QMatrix method X Line YA: QMatrix method Yk Line YB: QMatrix method Y Line SMP: CAT-SMP IO pin ACIFB-ACREFN: PA16 I/O pin Typical Values: CS:4.7nF Ra: 16500 Ohm Rb: 50 Ohm n - number of X Lines m - number of Y Lines I/O Pin requirements: X: QMatrix method X Line YA: QMatrix method Yk Line YB: QMatrix method Y Line VDIVEN: CAT-VDIVEN IO pin ACIFB-ACREFN: PA16 I/O pin Typical Values: CS:4.7nF n - number of X Lines m - number of Y Lines I/O Pin requirements: X: QMatrix method X Line YA: QMatrix method Yk Line YB: QMatrix method Y Line SYNC: CAT-SYNC IO pin ACIFB-ACREFN: PA16 I/O pin121 6.3.7.3 QMatrix method hardware resource requirement for UC3L The clock for the CAT module, CLK_CAT, is generated by the Power Manager (PM). This clock is turned on by default, and can be enabled and disabled in the PM. The user must ensure that CLK_CAT is enabled before initializing the QTouch Library. QMatrix operations also require the CAT generic clock, GCLK_CAT. This generic clock is generated by the System Control Interface (SCIF), and is shared between the CAT and the Analog Comparator Interface. The user must ensure that the GCLK_CAT is enabled in the SCIF before using QMatrix functionality. For proper QMatrix operation, the frequency of GCLK_CAT must be less than one fourth the frequency of CLK_CAT. For QMatrix operation, the Analog comparators channels are used (using the ACIFB interface) depending on the Y Lines enabled. See Note 4 in Section 6.3.7.4. The QMatrix method acquisition using the CAT module requires two Peripheral DMA channels that must be provided by the application. 6.3.7.4 QMatrix method Channel and Sensor numbering for UC3L Sensor 4 Sensor 3 Sensor 2 Sensor 1 Ch 0 X0 X3 X2 X1 Yk0 Yk1 Yk2 Yk3 KEY ROTOR/ SLIDER Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 Ch 9 Ch 10 Ch 11 Ch 12 Ch 13 Ch 14 Ch 15 Sensor 0 Sensor 5 Sensor 6 Figure 38 QMatrix channel numbering for UC3L The above figure represents a typical 4 X 4 matrix of QMatrix sensor arrangement along with the channel numbers. The Channel numbering starts with Channel 0 (Ch0) and increase sequentially from Ch0 to Ch15. Similarly the Sensor numbering starts with Sensor 0. The Channel number signifies the order in which the QTouch Library stores the acquisition data in the memory. Note: The touch_qm_sensor_config API must follow the above Channel and Sensor numbering when configuring the Sensors. 6.3.7.5 QMatrix method API Flow for UC3L For the QMatrix operation, the CAT_CLK and GCLK_CAT clocks must be setup appropriately as a first step. The QMatrix and Common configuration parameters in the touch_config_at32uc3l.h configuration must then be set up.122 8207L-AT42-05/12 Figure 39 QMatrix API Flow diagram for UC3L touch_qm_sensors_init() Configure multiple QMatrix sensors Using the init_clock() in main.c and clock.c files, Set the CAT_CLK Clock to appropriate value. Set the GCLK_CAT Clock to appropriate value. touch_qm_sensors_config() Using the touch_config_at32uc3l.h configuration file, Set DEF_TOUCH_QMATRIX = 1. Set all QM_xx and TOUCH_xx macros to appropriate values. (This includes 2 peripheral DMA Channels required for QMatrix operation.) In the main.c file, Set appropriate qm_burst_length[] values corresponding to all Touch channels . Set the desired measurement_period_ms for Touch measurement. touch_qm_sensors_calibrate() touch_event_dispatcher() touch_qm_sensors_start_ acquisition(NORMAL_ACQ_MODE) Call in loop time_to_ measure_touch filter_callback(), if enabled measure_complete_callback(), measured data and Touch Status Host Application code123 The burst length values of each Touch channel must be specified using the qm_burst_length[] array in the main.c file. The burst length must be specified in the same order of Touch Channel numbering. The touch_qm_sensors_init API initializes the QTouch Library as well as the CAT module and does the QMatrix method specific pin, register and Global Sensor configuration. The touch_qm_sensor_config API is used to configure individual sensor. The Sensor specific configuration parameter can be provided as input to this API. The touch_qm_sensors_calibrate API is used to calibrate all the configured sensors thereby preparing the sensors for acquisition. The touch_qm_sensors_start_acquisition API initiates a QMatrix method measurement on all the configured Sensors. This API takes the peripheral DMA channels as an input. When a filter_callback function is enabled, the touch_event_dispatcher function calls the filter_callback function as soon as the raw acquisition data from the Sensors is available. The user can now optionally apply any filtering routine on the raw acquisition data before the QTouch Library does any processing on this data. (For an overview of Filter callback usage, refer Section 5.6.6.4 Example code). Once the QTouch Library has finished processing the acquisition data from Sensors, the touch_event_dispatcher function calls the measure_complete_callback function indicating the end of a single Touch measurement operation. The measure_complete_callback provides the measured data and Touch status information. The measured data is available in the same order of Touch Channel numbering. Note 1: The Host Application code can execute once a QMatrix acquisition is initiated with the touch_qm_sensors_start_acqusition API. Care must be taken in the Host Application such that the touch_event_dispatcher function is called frequently in order to process the acquired data. For a single Touch measurement operation (between a touch_qm_sensors_start_acquisition API call and the measure_complete_callback function being called), the touch_event_dispatcher function may execute multiple times in order to resolve the Touch status of Sensors. Failing to call the touch_event_dispatcher frequently can adversely impact the Touch Sensitivity. Note 2: Once the Touch Library has been initialized for QMatrix method using the touch_qm_sensors_init API, a new qm_burst_length[x] value of a Touch channel must be updated only using the touch_qm_channel_update_burstlen API. It is recommended to have qm_burst_length array as global variable as the Touch Library updates this array when the touch_qm_channel_update_burstlen API is called. Note 3: QMatrix burst length setting recommendation. For a given X Line, the burst length value of ALL enabled Y Lines MUST be the same or set to 0x01(disabled). For example, the burst length value corresponding to (X0,Y1),(X0,Y2)...(X0,Yn) must be the same. In case of a scenario, wherein it is required to have a different a burst length, then the following option can be tried out - Enable the 1k ohm drive resistors on all the enabled Y lines by setting the corresponding bit in the CSARES register. Note 4: For QMatrix operation, the Analog comparators channels are used (using the ACIFB interface) depending on the Y Lines enabled. For example, when Y lines Y2 and Y7 are enabled the Analog comparator channels 2 and 7 are used by the CAT module for QMatrix operation. The user can uses the rest of the Analog comparator channels in the main application. The QTouch Library enables the ACIFB using the Control register (if not already enabled by the main application) when the touch_qm_sensors_init API is called.124 8207L-AT42-05/12 6.3.7.6 QMatrix method Disable and Re-enable Sensor for UC3L The touch_qm_channel_update_burstlen API can be used for Disabling and Re-enabling of QMatrix Sensors. In order to Disable a sensor, the QMatrix burst length value of all the Touch Channels corresponding to the Sensor must be set to 1. For Example, when a Wheel or Slider is composed of 4 Touch Channels, the touch_qm_channel_update_burstlen API should be used to set the burst length of all the 4 Touch Channels to 1. For the case of a Button, touch_qm_channel_update_burstlen API should be used to set burst length of the corresponding single Touch Channel of the Button to 1. Similarly, when re-enabling a Sensor, appropriate burst length must be set to all the Touch channels corresponding to the Sensor. When a QMatrix Sensor is Disabled or re-enabled, it is mandatory to force Calibration on all Sensors. The Calibration of all Sensors is done using the touch_qm_sensors_calibrate API. Note: When disabling a Wheel or Slider, care must be taken to set the burst length of all the Touch channels corresponding to the Wheel or Slider to 1. If any of the Touch channels are missed out, it may result in undesired behavior of the Wheel or Slider. Similarly when re-enabling a Wheel or Slider, burst length of all the Touch channels corresponding to the Wheel or Slider must be set to an appropriate value. If any of the Touch Channels are left disabled with a burst length value 1, it may result in undesired behavior of Wheel or Slider. 6.3.8 QTouch Group A/B method sensor operation for UC3L 6.3.8.1 QTouch Group A/B method pin selection for UC3L Please refer AT32UC3L datasheet Table 28-2 Pin Selection Guide and Table 3-1 GPIO Controller Function multiplexing, for mapping between the QTouch method pin name (SNS/SNSK) and the GPIO pin. The CAT module provides an option to enable a nominal output resistance of 1kOhm on specific CAT module pins during the burst phase. The Table below captures the different QTouch method pin wherein a Resistive Drive can be optionally enabled. The rows marked with Grey indicate that Resistive Drive option is not available on that pin. By carefully choosing the QTouch method SNSK pins wherein Resistive Drive can be enabled, saving on external components is possible. Section 6.3.1.2 provides detail on the number of Pin and Touch channels required for different QTouch method sensor. Also, Section 6.3.11 indicates the various Pin Configuration options for the QTouch Library that can be used to specify a user defined configuration. 125 CAT Module Pin Name QTouch method Pin Name CSA0 SNS0 CSB0 SNSK0 CSA1 SNS1 CSB1 SNSK1 CSA2 SNS2 CSB2 SNSK2 CSA3 SNS3 CSB3 SNSK3 CSA4 SNS4 CSB4 SNSK4 CSA5 SNS5 CSB5 SNSK5 CSA6 SNS6 CSB6 SNSK6 CSA7 SNS7 CSB7 SNSK7 CSA8 SNS8 CSB8 SNSK8 CSA9 SNS9 CSB9 SNSK9 CSA10 SNS10 CSB10 SNSK10 CSA11 SNS11 CSB11 SNSK11 CSA12 SNS12 CSB12 SNSK12 CSA13 SNS13 CSB13 SNSK13 CSA14 SNS14 CSB14 SNSK14 CSA15 SNS15 CSB15 SNSK15 CSA16 SNS16 CSB16 SNSK16 Table 11 QTouch Resistive drive pin option (The rows marked with Grey indicate that Resistive Drive option is not available on that pin.) 6.3.8.2 QTouch Group A/B method Schematic for UC3L 6.3.8.2.1 Resistive Drive option The cases A and B of the Figure provide the schematic arrangement of QTouch Group A/B and Autonomous QTouch Sensors. In option A, Resistive drive is enabled on SNSK line. In case B, Resistive drive is disabled on the SNSK line and in this case, it is recommended to use 1kOhm resistors on SNSK Line external to the UC3L device. 6.3.8.2.2 SYNC pin option In order to prevent interference from the 50 or 60 Hz mains line the CAT can optionally trigger QTouch Group A/B and Autonomous QTouch acquisition on the external SYNC input signal. The SYNC signal should be derived from the mains line and the acquisition will trigger on a falling edge of this signal. The SYNC pin usage in the Internal Discharge mode scenario is shown in case C. For QTouch method SYNC pin options Refer to Section 6.3.15.2.13.126 8207L-AT42-05/12 Figure 40 QTouch Group A/B and Autonomous QTouch schematic arrangement 6.3.8.3 QTouch Group A/B method hardware resource requirement for UC3L The clock for the CAT module, CLK_CAT, is generated by the Power Manager (PM). This clock is turned on by default, and can be enabled and disabled in the PM. The user must ensure that CLK_CAT is enabled before initializing the QTouch Library. The QTouch method acquisition using the CAT module requires one Peripheral DMA channel that must be provided by the application. Atmel AT32UC3L CAT Module A. QTouch Group A/B and Autonomous QTouch arrangement. Resistive drive enabled on SNSK Line. Sensor Cs Typical Values: Cs: 22nF Pin requirements: SNS: CAT QTouch method I/O pin SNSK: CAT QTouch method I/O pin SNSK SNS Atmel AT32UC3L CAT Module Sensor Cs Typical Values: Cs: 22nF Pin requirements: SNS: CAT QTouch method I/O pin SNSK: CAT QTouch method I/O pin SYNC: CAT-SYNC I/O pin SNSK SNS C. QTouch Group A/B and Autonomous QTouch arrangement. Resistive drive enabled on SNSK Line. External Synchronization enabled. Sync signal SYNC Atmel AT32UC3L CAT Module Sensor Cs Typical Values: Cs: 22nF, Rs:1kOhm Pin requirements: SNS: CAT QTouch method I/O pin SNSK: CAT QTouch method I/O pin SNSK SNS Rs B. QTouch Group A/B and Autonomous QTouch arrangement. Resistive drive disabled on SNSK Line.127 6.3.8.4 QTouch Group A/B method Channel and Sensor numbering for UC3L Figure 41 QTouch method Channel/Sensor numbering The above Figure represents an example 4 Channel QTouch sensor arrangement along with the channel numbers. The Channel numbering starts with the lowest SNS-SNSK QTouch method pair number (SNS2-SNSK2 being the least in this case) and increases as the SNS-SNSK pair number increases. Similarly the Sensor numbering starts with Sensor 0. The Channel number signifies the order in which the QTouch Library stores the acquisition data in the memory. Figure 42 QTouch method Channel/Sensor numbering when Group A and B are used together When both QTouch Group A and QTouch Group B method are used at the same time, the SNSSNSK pairs associated with the individual group alone must be taken into consideration when determining the Channel number. Note: The touch_qt_sensor_config API must follow the above Channel and Sensor numbering when configuring the Sensors. channel 0 Sensor 0 Sensor 1 ATMEL AT32UC3L SNSK2 SNS2 SNSK3 SNS3 SNSK5 SNS5 SNSK9 SNS9 channel 1 channel 2 channel 3 QTouch Grp A Channel 0 QTouch Grp A Sensor 0 QTouch Grp B Sensor 0 ATMEL AT32UC3L SNSK2 SNS2 SNSK3 SNS3 SNSK5 SNS5 SNSK6 SNS6 QTouch Grp A Sensor 1 SNSK7 SNS7 SNSK9 SNS9 QTouch Grp B Sensor 1 QTouch Grp A Channel 1 QTouch Grp A Channel 2 QTouch Grp B Channel 0 QTouch Grp A Channel 3 QTouch Grp B Channel 1 128 8207L-AT42-05/12 6.3.8.5 QTouch Group A/B method API Flow for UC3L For the QTouch operation, the CAT_CLK must be setup appropriately as a first step. Depending on QTouch Group that need to be used, the QTouch Group A, QTouch Group B and Common configuration parameters in the touch_config_at32uc3l.h configuration must then be set up. The first input argument to the QTouch API, TOUCH_QT_GRP_A or TOUCH_QT_GRP_B indicates if the QTouch API must perform the necessary operation on Group A Sensors or Group B Sensors. The touch_qt_sensors_init API initializes the QTouch Library as well as the CAT module and does the QTouch method specific pin, register and Global Sensor configuration. The touch_qt_sensor_config API is used to configure individual sensor. The Sensor specific configuration parameter can be provided as input to this API. The touch_qt_sensors_calibrate API is used to calibrate all the configured sensors thereby preparing the sensors for acquisition. The touch_qt_sensors_start_acquisition API initiates a QTouch method measurement on all the configured Sensors (corresponding to the input Touch Group A or B). This API takes the peripheral DMA channels as an input. When a filter_callback function is enabled, the touch_event_dispatcher function calls the filter_callback function as soon as the raw acquisition data from the Sensors is available. The user can now optionally apply any filtering routine on the raw acquisition data before the QTouch Library does any processing on this data. (For an overview of Filter callback usage, refer Section 5.6.6.4 Example code). Once the QTouch Library has finished processing the acquisition data from Sensors, the touch_event_dispatcher function calls the measure_complete_callback function indicating the end of a single Touch measurement operation. The measure_complete_callback provides the measured data and Touch status information. The measured data is available in the same order of Touch Channel numbering. Separate Filter and Measure complete callback functions must be provided for Group A and Group B Sensors. Note: The Host Application code can execute once a QTouch acquisition is initiated with the touch_qt_sensors_start_acqusition API. Care must be taken in the Host Application such that the touch_event_dispatcher function is called frequently in order to process the acquired data. For a single Touch measurement operation (between a touch_qt_sensors_start_acquisition API call and the measure_complete_callback function being called), the touch_event_dispatcher function may execute multiple times in order to resolve the Touch status of Sensors. Failing to call the touch_event_dispatcher frequently can adversely impact the Touch Sensitivity. 129 Figure 43 QTouch method API Flow diagram touch_qt_sensors_init() Configure multiple QTouch sensors Using the init_clock() in main.c and clock.c files, Set the CAT_CLK Clock to appropriate value. touch_qt_sensors_config() Using the touch_config_at32uc3l.h configuration file, Set DEF_TOUCH_QTOUCH_GRP_A = 1, if QTouch Group A is to be used. Set DEF_TOUCH_QTOUCH_GRP_B = 1, if QTouch Group B is to be used. Set all QTA_xx (if Group A is enabled) to appropriate values. Set all QTB_xx (if Group B is enabled) to appropriate values. Set all TOUCH_xx macros to appropriate values. (This includes 1 peripheral DMA Channels required for QTouch operation.) In the main.c file, Set the desired measurement_period_ms for Touch measurement. The API Sequence below must be repeated for Group A and Group B when both the Groups are used at the same time. The first argument to the API TOUCH_QT_GRP_A or TOUCH_QT_GRP_B distinguishes between Group A and Group B operations. Separate Filter and Measurement complete callback functions must be provided for Group A and Group B Sensors. touch_qt_sensors_calibrate() touch_event_dispatcher() touch_qt_sensors_start_ acquisition(NORMAL_ACQ_MODE) Call in loop time_to_ measure_touch filter_callback(), if enabled measure_complete_callback(), measured data and Touch Status Host Application code130 8207L-AT42-05/12 6.3.8.6 QTouch Group A/B method Disable and Re-enable Sensor for UC3L The touch_qt_sensor_disable and touch_qt_sensor_reenable API can be used for Disabling and Re-enabling of QTouch Group A and Group B Sensors. In order to Disable or re-enable a sensor, the API must be called with the corresponding sensor_id. Disabling a Sensor disables the measurement process on all the Touch Channels corresponding to Sensor. When a QTouch Sensor is Disabled or re-enabled, it is mandatory to force Calibration on all Sensors. The Calibration of all Sensors is done using the touch_qt_sensors_calibrate API. 6.3.9 Autonomous QTouch sensor operation for UC3L 6.3.9.1 Autonomous QTouch Sensor pin selection for UC3L The Autonomous QTouch Sensor pin selection is similar to selection of pin for QTouch Group A/B as indicated in Section 6.3.8.1. Any one SNS-SNSK pair between SNS0-SNSK0 and SNS16- SNSK16 can be chosen to function as an Autonomous QTouch sensor. 6.3.9.2 Autonomous QTouch sensor Schematic for UC3L The Autonomous QTouch Sensor Sensor schematic is similar QTouch schematic as indicated in Section 6.3.8.2. 6.3.9.3 Autonomous QTouch method hardware resource requirement for UC3L The clock for the CAT module, CLK_CAT, is generated by the Power Manager (PM). This clock is turned on by default, and can be enabled and disabled in the PM. The user must ensure that CLK_CAT is enabled before initializing the QTouch Library for Autonomous QTouch. For the Autonomous QTouch Sensor, the complete detection algorithm is implemented within the CAT module. This allows detection of proximity or touch without CPU intervention. Since the Autonomous QTouch Sensor operates without software interaction, this Sensor can be used to wakeup from sleep modes when activated. The Autonomous QTouch Status change interrupt can be used to wakeup from any of the Sleep modes shown in the Table. The ‘Static’ Sleep mode being the deepest possible Sleep mode from which a wake up from Sleep is possible using the Autonomous QTouch. Both an IN_TOUCH status change and OUT_OF_TOUCH status change indication is available when using Autonomous QTouch. The Autonomous QTouch method acquisition using the CAT module does not require any Peripheral DMA channel for operation. Sleep Mode CPU HSB PBA,B GCLK Clock sources Osc32 RCSYS BOD & Bandgap Voltage Regulator Idle Stop Run Run Run Run Run On Full power Frozen Stop Stop Run Run Run Run On Full power Standby Stop Stop Stop Run Run Run On Full power Stop Stop Stop Stop Stop Run Run On Low power DeepStop Stop Stop Stop Stop Run Run Off Low power Static Stop Stop Stop Stop Run Stop Off Low power Table 12 Sleep mode support for Autonomous QTouch131 6.3.9.4 Autonomous QTouch Sensor API Flow for UC3L For the Autonomous QTouch operation, the CAT_CLK must be setup appropriately as a first step. The Autonomous QTouch and Common configuration parameters in the touch_config_at32uc3l.h configuration must then be set up. The touch_at_sensors_init API initializes the QTouch Library as well as the CAT module for the Autonomous QTouch sensor related pin, register and Global Sensor configuration. The Autonomous QTouch Sensor can be enabled at any time by the Host Application. Once the Autonomous QTouch Sensor is enabled, the CAT module performs measurements on this sensor continuously to detect a Touch Status. When an IN_TOUCH or OUT_OF_TOUCH status is detected, the QTouch Library calls the touch_at_status_change_interrupt_callback function to indicate the status to the Host application. It is possible to enable and disable Autonomous QTouch sensor multiple times in the Host application by using the touch_at_sensor_enable and touch_at_sensor_disable API. Figure 44 Autonomous QTouch API Flow diagram 6.3.9.5 Autonomous QTouch method Enable and Disable Sensor for UC3L The touch_at_sensor_enable and touch_at_sensor_disable API can be used for Enabling and Disabling and the Autonomous QTouch Sensor. Once the Autonomous QTouch sensor is enabled, the CAT module performs continuous Touch Measurements on the Sensor in order to detect the Touch Status. touch_at_sensor_init() Using the init_clock() in main.c and clock.c files, Set the CAT_CLK Clock to appropriate value. touch_at_sensor_enable() Using the touch_config_at32uc3l.h configuration file, Set DEF_TOUCH_AUTONOMOUS_QTOUCH = 1. Set all AT_xx and TOUCH_xx macros to appropriate values. touch_at_status_change_interrupt_callback(), Autonomous QTouch Status touch_at_sensor_disable() Disable Autonomous QTouch Sensor if required The callback is called as long as Autonomous QTouch sensor is not disabled Re-enable Autonomous QTouch Sensor if required132 8207L-AT42-05/12 6.3.10 Raw acquisition mode support for UC3L The QTouch Library Raw acquisition mode can be used with QMatrix, QTouch Group A and QTouch Group B methods. When raw data acquisition mode is used, once the raw acquisition data is available from the CAT module for all the sensors, the measure_complete_callback function is immediately called with acquisition data (channel_signals). The channel_references, sensor_states and rotor_slider_values data are not updated by the Touch Library in this mode. Figure 45 Raw acquisition mode API Flow diagram touch_xx_sensors_init() Configure multiple sensors touch_xx_sensors_config() touch_xx_sensors_calibrate() touch_event_dispatcher() touch_xx_sensors_start_ acquisition(RAW_ACQ_MODE) Call in loop time_to_ measure_touch measure_complete_callback(), Raw acquisition data. Host Application code133 6.3.11 Library Configuration parameters for UC3L The QTouch Library for UC3L provides a single configuration header file touch_config_at32uc3l.h file for setting the various configuration parameters for each method. The different configuration parameters corresponding to QMatrix, QTouch Group A/B and Autononmous QTouch sensors are listed in the Table below. Paramete r QMatrix QTouch Group A/B Autonomous QTouch Sensor Configuration QM_NUM_X_LINES QM_NUM_Y_LINES QM_NUM_SENSORS QM_NUM_ROTORS_SLIDERS QTx_NUM_SENSORS QTx_NUM_ROTORS_SLIDERS None Pin Configuration QM_X_PINS_SELECTED QM_Y_PAIRS_SELECTED QM_SMP_DIS_PIN_OPTION QM_VDIV_PIN_OPTION QTx_SP_SELECTED AT_SP_SELECTED Clock and Register Configuration QM_GCLK_CAT_DIV QM_CAT_CLK_DIV QM_CHLEN QM_SELEN QM_CXDILEN QM_DILEN QM_DISHIFT QM_MAX_ACQ_COUNT QM_CONSEN QM_INTREFSEL QM_INTVREFSEL QM_ENABLE_SPREAD_SPECTRU M QM_ENABLE_EXTERNAL_SYNC QM_SYNC_TIM QTx_CAT_CLK_DIV QTx_CHLEN QTx_SELEN QTx_DILEN QTx_DISHIFT QTx_MAX_ACQ_COUNT QTx_ENABLE_SPREAD_SPECTRU M QTx_ENABLE_EXTERNAL_SYNC AT_CAT_CLK_DIV AT_CHLEN AT_SELEN AT_DILEN AT_DISHIFT AT_MAX_ACQ_COUN T AT_ENABLE_SPREAD _ SPECTRUM AT_ENABLE_ EXTERNAL_SYNC AT_FILTER AT_OUTSENS AT_SENSE AT_PTHR AT_PDRIFT AT_NDRIFT Peripheral DMA Channel Configuration QM_DMA_CHANNEL_0 QM_DMA_CHANNEL_1 QTx_DMA_CHANNEL_0 None Global acquisition parameter Configuration QM_DI QM_NEG_DRIFT_RATE QM_POS_DRIFT_RATE QM_MAX_ON_DURATION QM_DRIFT_HOLD_TIME QM_POS_ RECAL_DELAY QM_RECAL_THRESHOLD QTx_DI QTx_NEG_DRIFT_RATE QTx_POS_DRIFT_RATE QTx_MAX_ON_DURATION QTx_DRIFT_HOLD_TIME QTx_ POS_RECAL_DELAY QTx_RECAL_THRESHOLD None Callback Function Configuration QM_FILTER_CALLBACK QTx_FILTER_CALLBACK None Common Configuration Options TOUCH_SYNC_PIN_OPTION, TOUCH_SPREAD_SPECTRUM_MAX_DEV, TOUCH_CSARES, TOUCH_CSBRES Table 13 QTouch Library for UC3L Configuration parameters134 8207L-AT42-05/12 For an overview of the Global acquisition configuration parameters and Sensor specific parameters, refer Section 5.3 and Section 5.4. The detailed information on other parameters is available in the configuration header file. For QMatrix method Design guidelines regarding Sensor parameters refer Section 5.6.7.3. 6.3.12 Example projects for QTouch Library for UC3L 6.3.12.1 Example Project usage The GNU Example projects can be used along with Atmel Studio 6. Figure 46 GNU Example project usage with AVR32 Studio The IAR Example Projects can be used with IAR Embedded Workbench for AVR32 v4.1 Figure 47 IAR Example project usage with IAR Embedded Workbench for AVR32135 6.3.12.2 QMatrix Example Project The QMatrix method GNU and IAR Example projects can be found in the following path. \Device_Specific_Libraries\32bit_AVR\UCxx\example_projects\uc3l_gnu_qm_ek_example and \Device_Specific_Libraries\32bit_AVR\UCxx\example_projects\uc3l_iar_qm_ek_example The QMatrix Example projects demonstrate the QMatrix operation on the UC3L Evaluation Kit (Rev 2). QMatrix SMP discharge mode hardware arrangement is used for the UC3L Evaluation Kit with 6 X Lines and 2 Y Lines. Using the 12 Touch Channels (6x2), 6 Touch Sensors are formed that include a Rotor (that uses six Touch Channels) and 5 keys (each using one Touch channel). The Example projects demonstrate the QMatrix measured data and Touch Status usage using the LED Demo application. The onboard LED0, LED1, LED2 and LED3 are set when the Touch Position of the Rotor position varies from 0 to 255. By Touching the up key (^), left key (<), play/pause key (>/||) and right key (>), the LED0, LED1, LED2 and LED3 can be individually cleared. When the down key (v) is touched, it clears all LEDs. Additionally QMatrix Example projects are also available for QT600 and STK600 boards. 6.3.12.3 QTouch Group A Example Project The QTouch Group A method GNU and IAR Example projects can be found in the following path. \Device_Specific_Libraries\32bit_AVR\UCxx\example_projects\uc3l_gnu_qt_grp_a_example and \Device_Specific_Libraries\32bit_AVR\UCxx\example_projects\uc3l_iar_qt_grp_a_example The QTouch Group A Example projects demonstrate the QTouch method API usage with a Rotor, Slider and two keys Sensor configuration. 6.3.12.4 Autonomous QTouch Example Project The Autonomous QTouch Sensor GNU and IAR Example projects can be found in the following path. \Device_Specific_Libraries\32bit_AVR\UCxx\example_projects\ uc3l_gnu_autonomous_qt_example and \Device_Specific_Libraries\32bit_AVR\UCxx\example_projects\ uc3l_iar_autonomous_qt_example The Autonomous QTouch Example projects demonstrate the Autonomous QTouch Sensor API usage. The Example projects also demonstrate wake up from Sleep mode using the Asynchronous Timer peripheral event. Note 1: The Example Projects also support relaying the Touch Sensor debug information to the “QTouch Studio – Touch Analyzer” PC Software. The QTouch Studio can also be used for setting the Sensor and Global configuration parameters of the QTouch Library at run-time. The QTouch Studio can be downloaded from the following path. The QDebug two-way debug protocol used by the Example project to communicate (transmit or receive touch debug data) with the QTouch Studio can be found in the following installation path. http://www.atmel.com/products/touchsoftware/qtouchsuite.asp?family_id=702 \Device_Specific_Libraries\32bit_AVR\UCxx\qdebug136 8207L-AT42-05/12 • For the UC3L Evaluation kit (uc3l_xx_qm_ek_example Example project) to connect with the QTouch Studio using the USB interface, the UC3B MCU on the UC3L Evaluation kit must be Flashed with ISP and Program binaries. The procedure to flash the binaries is available in the readme note in the following path. \Device_Specific_Libraries\32bit_AVR\UC3L\example_projects\uc3l_gnu_qm_ek_exampl e\ uc3b\readme.txt or \Device_Specific_Libraries\32bit_AVR\UC3L\example_projects\uc3l_iar_qm_ek_example \ uc3b\readme.txt • For the case of QTouch Group A and Autonomous QTouch Example projects, the ‘QT600-USB Bridge’ board can be use to capture the QDebug debug data in the QTouch Studio. Note 2: In order to flash the generated elf binary file for GNU and IAR, the following command can be used from the Command Line. avr32program --part UC3L064 program -finternal@0x80000000 -e --run -R -cint uc3l_gnu_qm_ek_example.elf 6.3.13 Code and Data Memory requirements for UC3L 6.3.13.1 QMatrix method memory requirement The Table below captures the Typical Code & Data Memory requirement for the QTouch Library when QMatrix method is used standalone. In addition to the Data memory captured in the Table, the QMatrix method requires additional Data Memory that must be provided to the Touch Library for storing the Signals, References, Sensor information and Touch status. This data memory is provided by the Host Application to the QTouch Library as QMatrix data block. The size of this Data memory block depends on the Number of Sensors and the Number of Wheel or Slider configured. The PRIV_QM_DATA_BLK_SIZE macro in touch_api_at32uc3l.h calculates the size of this data memory block. For example, for the UC3L Evaluation kit Rev2 that has 6 Sensors including 1 Wheel and 5 Buttons, the QMatrix data block memory size is 236 bytes. Library Typical Code with Keys Only Typical Code when one or more Wheel/Sliders is used Typical Data Memory libuc3l-qtouch-iar.r82 5882 7296 278 libuc3l-qtouch-gnu.a 6228 8080 278 Table 14 Typical Code and Data memory for Standalone QMatrix operation Note: This Typical Code memory usage is achieved when only QMatrix Regular API is used in the application. Usage of QMatrix Helper API would consume additional Code memory. Also, the Code and Data memory indicated in the Table do not account for Example QMatrix application. 6.3.13.2 QTouch Group A/B method memory requirement The Table below captures the Typical Code & Data Memory requirement for the QTouch Library when QTouch Group A or QTouch Group B Sensor is used standalone. (Additional Data memory will be required when both Group A and Group B are used at the same time.) In addition to the Data memory captured in the Table, the QTouch Group A/B method requires additional Data Memory that must be provided to the Touch Library for storing the Signals, 137 References, Sensor information and Touch status. This data memory is provided by the Host Application to the QTouch Library as QTouch data block. The size of this Data memory block depends on the Number of Sensors and the Number of Wheel or Slider configured. Refer PRIV_QTx_DATA_BLK_SIZE macro in touch_api_at32uc3l.h. For example, when 6 Sensors are used that include 1 Wheel, 1 Slider and 2 Button, the QTouch GroupA/B data block memory size is 184 bytes. Library Typical Code with Keys Only Typical Code when one or more Wheel/Sliders is used Typical Data Memory libuc3l-qtouch-iar.r82 5198 6450 358 libuc3l-qtouch-gnu.a 5290 6774 358 Table 15 Typical Code and Data memory for Standalone QTouch Group A/B operation Note: This Typical Code memory usage is achieved when only the QTouch Group A/B Regular API is used in the application. Usage of QTouch Group A/B Helper API would consume additional Code memory. Also, the Code and Data memory indicated in the Table do not account for Example QTouch application. 6.3.13.3 Autonomous QTouch memory requirement The Table below captures the Typical Code & Data Memory requirement for the QTouch Library when Autonomous Touch Sensor is used standalone. Library Typical Code with Keys Only Typical Data Memory libuc3l-qtouch-iar.r82 1184 22 libuc3l-qtouch-gnu.a 966 16 Table 16 Minimum Code and Data for Standalone Autonomous QTouch sensor Note: This Typical Code memory usage is achieved when only the Autonomous QTouch Regular API is used in the application. Usage of Autonomous QTouch Helper API would consume additional Code memory. Also, the Code and Data memory indicated in the Table do not account for Example Autonomous QTouch application. 6.3.14 Public header files of QTouch Library for UC3L Following are the public header files which need to be included in user’s application and these have the type definitions and function prototypes of the APIs listed in the following sections 1. touch_api_at32uc3l.h - QTouch Library API and Data structures file. 2. touch_config_at32uc3l.h - QTouch Library configuration file. 6.3.15 Type Definitions and enumerations used in the library 6.3.15.1 Typedefs This section lists the type definitions used in the library. Typedef Notes uint8_t unsigned 8-bit integer. int8_t signed 8 bit integer. uint16_t unsigned 16-bit integer. int16_t signed 16-bit integer.138 8207L-AT42-05/12 uint32_t unsigned 32 bit integer. int32_t signed 32 bit integer. channel_t unsigned 8 bit integer that represents the channel number, starts from 0. threshold_t unsigned 8 bit integer to set sensor detection threshold. sensor_id_t unsigned 8 bit integer that represents the sensor ID, starts from 0. touch_time_t unsigned 16 bit integer that represents current time maintained by the library. touch_bl_t unsigned 8 bit integer that represents the burst length of a QMatrix channel. touch_delta_t signed 16 bit integer that represents the delta value of a channel. touch_acq_status_t unsigned 16 bit Status of Touch measurement. touch_qt_grp_t unsigned 8 bit QTouch Group type. touch_qt_dma_t unsigned 8 bit QTouch Group A/ Group B DMA channel type.. 6.3.15.1.1 touch_acq_status_t uint16_t touch_acq_status_t Use Indicates the result of the last acquisition & processing for a specific touch acquisition method. Values Bitmask Comment TOUCH_NO_ACTIVITY 0x0000u No Touch activity. TOUCH_IN_DETECT 0x0001u At least one Touch channel is in detect. TOUCH_STATUS_CHANGE 0x0002u Status change in at least one channel. TOUCH_ROTOR_SLIDER_POS_CHANGE 0x0004u At least one rotor or slider has changed position. TOUCH_CHANNEL_REF_CHANGE 0x0008u Reference values of at least one of the channel has changed. TOUCH_BURST_AGAIN 0x0100u Indicates that reburst is required to resolve Filtering or Calibration state. TOUCH_RESOLVE_CAL 0x0200u Indicates that reburst is needed to resolve Calibration. TOUCH_RESOLVE_FILTERIN 0x0400u Indicates that reburst is needed to resolve Filtering. TOUCH_RESOLVE_DI 0x0800u Indicates that reburst is needed to resolve Detect Integration. TOUCH_RESOLVE_POS_RECAL 0x1000u Indicates that reburst is needed to resolve Recalibration. 6.3.15.1.2 touch_qt_grp_t uint8_t touch_qt_grp_t Use QTouch Group type. Values Value Comment TOUCH_QT_GRP_A 0u QTouch Group A. TOUCH_QT_GRP_B 1u QTouch Group B. 6.3.15.2 Enumerations This section lists the enumerations used in the QTouch Library.139 6.3.15.2.1 touch_ret_t Enumeration touch_ret_t Use Indicates the Touch Library error code. Values Comment TOUCH_SUCCESS Successful completion of operation. TOUCH_ACQ_INCOMPLETE Touch Library is busy with pending previous Touch measurement. TOUCH_INVALID_INPUT_PARAM Invalid input parameter. TOUCH_INVALID_LIB_STATE Operation not allowed in the current Touch Library state. TOUCH_INVALID_QM_CONFIG_PARAM Invalid QMatrix config input parameter. TOUCH_INVALID_AT_CONFIG_PARAM Invalid Autonomous Touch config input parameter. TOUCH_INVALID_QT_CONFIG_PARAM Invalid QTouch config input parameter. TOUCH_INVALID_GENERAL_CONFIG_PARAM Invalid General config input parameter. TOUCH_INVALID_QM_NUM_X_LINES Mismatch between number of X lines specified as QM_NUM_X_LINES and number of X lines enabled in QMatrix pin configuration touch_qm_pin_t x_lines. TOUCH_INVALID_QM_NUM_Y_LINES Mismatch between number of Y lines specified as QM_NUM_Y_LINES and number of Y lines enabled in QMatrix pin configuration touch_qm_pin_t y_yk_lines. TOUCH_INVALID_QM_NUM_SENSORS Number of Sensors specified is greater than (Number of X Lines * Number of Y Lines). TOUCH_INVALID_MAXDEV_VALUE Spread spectrum MAXDEV value should not exceed (2*DIV + 1). TOUCH_INVALID_RECAL_THRESHOLD Invalid Recalibration threshold input value. TOUCH_INVALID_CHANNEL_NUM Channel number parameter exceeded total number of channels configured. TOUCH_INVALID_SENSOR_TYPE Invalid sensor type. Sensor type can NOT be SENSOR_TYPE_UNASSIGNED. TOUCH_INVALID_SENSOR_ID Invalid Sensor number parameter. TOUCH_INVALID_DMA_PARAM DMA Channel numbers are out of range. TOUCH_FAILURE_ANALOG_COMP Analog comparator configuration error. TOUCH_INVALID_RS_NUM Number of Rotor/Sliders set as 0, when trying to configure a rotor/slider. 6.3.15.2.2 touch_lib_state_t Enumeration touch_lib_state_t Use Indicates the current state of the library with respect to a specific acquisition method Values Comment TOUCH_LIB_STATE_NULL Library is not yet initialized for the specific acquisition method TOUCH_LIB_STATE_INIT Library is initialized, sensor configuration and calibration is not yet done. TOUCH_LIB_STATE_READY Library is ready for a new acquisition in the specific method TOUCH_LIB_STATE_CALIBRATE Library requires re-calibration before acquisition can be 140 8207L-AT42-05/12 done for the specific acquisition method TOUCH_LIB_STATE_BUSY Library is busy with acquisition & processing for the specific acquisition method 6.3.15.2.3 touch_acq_mode_t Enumeration touch_acq_mode_t Use Touch library acquisition mode type. Values Comment RAW_ACQ_MODE When Raw acquisition mode is used, the measure_complete_callback function is called immediately once fresh values of Signals are available. In this mode, the Touch Library does not do any processing on the Signals. So, the references, Sensor states or Rotor/Slider position values are not updated in this mode. NORMAL_ACQ_MODE When Nomal acquisition mode is used, the measure_complete_callback function is called only after the Touch Library completes processing of the Signal values obtained. The References, Sensor states and Rotor/Slider position values are updated in this mode. 6.3.15.2.4 sensor_type_t Enumeration sensor_type_t Use Define the type of the sensor Values Comment SENSOR_TYPE_UNASSIGNED Channel is not assigned to any sensor SENSOR_TYPE_KEY Sensor is a key SENSOR_TYPE_ROTOR Sensor is a rotor SENSOR_TYPE_SLIDER Sensor is a slider 6.3.15.2.5 aks_group_t Enumeration aks_group_t Use Defines the Adjacent Key Suppression (AKS) groups that each sensor may be associated with AKS™ is selectable by the system designer 7 AKS groups are supported by the library Values Comment NO_AKS_GROUP No AKS group is selected for the sensor AKS_GROUP_1 AKS Group number 1 AKS_GROUP_2 AKS Group number 2 AKS_GROUP_3 AKS Group number 3 AKS_GROUP_4 AKS Group number 4 AKS_GROUP_5 AKS Group number 5 AKS_GROUP_6 AKS Group number 6 AKS_GROUP_7 AKS Group number 7 6.3.15.2.6 hysteresis_t Enumeration Hysteresis_t Use Defines the sensor detection hysteresis value. This is expressed as a percentage of the sensor detection threshold.141 This is configurable per sensor. HYST_x = hysteresis value is x percent of detection threshold value (rounded down). Note that a minimum value of 2 is used as a hard limit. Example: if detection threshold = 20, then: HYST_50 = 10 (50 percent of 20) HYST_25 = 5 (25 percent of 20) HYST_12_5 = 2 (12.5 percent of 20) HYST_6_25 = 2 (6.25 percent of 20 = 1, but set to the hard limit of 2) Values Comment HYST_50 50% Hysteresis HYST_25 25% Hysteresis HYST_12_5 12.5% Hysteresis HYST_6_25 6.25% Hysteresis 6.3.15.2.7 recal_threshold_t Enumeration recal_threshold_t Use A sensor recalibration threshold. This is expressed as a percentage of the sensor detection threshold. This is for automatic recovery from false conditions, such as a calibration while sensors were touched, or a significant step change in power supply voltage. If the false condition persists the library will recalibrate according to the settings of the recalibration threshold. This setting is applicable to all the configured sensors. Usage : RECAL_x = recalibration threshold is x percent of detection threshold value (rounded down). Note: a minimum value of 4 is used. Example: if detection threshold = 40, then: RECAL_100 = 40 ( 100 percent of 40) RECAL_50 = 20 ( 50 percent of 40) RECAL_25 = 10 ( 25 percent of 40) RECAL_12_5 = 5 ( 12.5 percent of 40) RECAL_6_25 = 4 ( 6.25 percent of 40 = 2, but value is limited to 4) Values Comment RECAL_100 100% recalibration threshold RECAL_50 50% recalibration threshold RECAL_25 25% recalibration threshold RECAL_12_5 12.5% recalibration threshold RECAL_6_25 6.25% recalibration threshold 6.3.15.2.8 resolution_t Enumeration resolution_t Use For rotors and sliders, the resolution of the reported angle or position. RES_x_BIT = rotor/slider reports x-bit values. Example: if slider resolution is RES_7_BIT, then reported positions are in the range 0..127.142 8207L-AT42-05/12 Values Comment RES_1_BIT 1 bit resolution : reported positions range 0 – 1 RES_2_BIT 2 bit resolution : reported positions range 0 – 3 RES_3_BIT 3 bit resolution : reported positions range 0 – 7 RES_4_BIT 4 bit resolution : reported positions range 0 – 15 RES_5_BIT 5 bit resolution : reported positions range 0 – 31 RES_6_BIT 6 bit resolution : reported positions range 0 – 63 RES_7_BIT 7 bit resolution : reported positions range 0 – 127 RES_8_BIT 8 bit resolution : reported positions range 0 – 255 6.3.15.2.9 at_status_change_t Enumeration at_status_change_t Use Indicates the current status of autonomous QTouch sensor Values Comment OUT_OF_TOUCH Currently the autonomous QTouch channel is out of touch IN_TOUCH Currently the autonomous QTouch channel is in detect 6.3.15.2.10x_pin_options_t Enumeration x_pin_options_t Use Options for various pins to be assigned as X lines in QMatrix Values Comment Xn Use Pin Xn for QMatrix, n ranges from 0 to 17. Note: X8 pin must NOT be used as X Line and it is recommended to be used as ACREFN pin for QMatrix. 6.3.15.2.11y_pin_options_t Enumeration y_pin_options_t Use Options for various pins to be assigned as Y lines in QMatrix Values Comment Yn_YKn Use Pin Yn & YKn for QMatrix, n ranges from 0 to 7 6.3.15.2.12qt_pin_options_t Enumeration qt_pin_options_t Use Options for various pins to be assigned as Sense pair for Autonomous QTouch, QTouch Group A and QTouch Group B acquisition methods. Values Comment SPn Use Sense Pair ‘n’ , n ranges from 0 to 16. 6.3.15.2.13general_pin_options_t Enumeration general_pin_options_t Use Options of various pins to be used for SMP, Discharge, SYNC & VDIV. Values Comment USE_NO_PIN No Pin is to be assigned for this purpose143 USE_PIN_PA12_AS_SMP Use Pin PA12 as SMP for QMatrix USE_PIN_PA13_AS_SMP Use Pin PA13 as SMP for QMatrix USE_PIN_PA14_AS_SMP Use Pin PA14 as SMP for QMatrix USE_PIN_PA17_AS_SMP Use Pin PA17 as SMP for QMatrix USE_PIN_PA21_AS_SMP Use Pin PA21 as SMP for QMatrix USE_PIN_PA22_AS_SMP Use Pin PA22 as SMP for QMatrix USE_PIN_PA17_AS_DIS Use Pin PA17 as Discharge current control for QMatrix USE_PIN_PB11_AS_VDIV Use Pin PB11 as Voltage divider enable (VDIVEN) for QMatrix USE_PIN_PA15_AS_SYNC Use Pin PA15 as external synchronization input signal (SYNC) USE_PIN_PA18_AS_SYNC Use Pin PA18 as external synchronization input signal (SYNC) USE_PIN_PA19_AS_SYNC Use Pin PA19 as external synchronization input signal (SYNC) USE_PIN_PB08_AS_SYNC Use Pin PB08 as external synchronization input signal (SYNC) USE_PIN_PB12_AS_SYNC Use Pin PB12 as external synchronization input signal (SYNC) 6.3.16 Data structures This section lists the data structures that hold sensor status, settings, and diagnostics information. 6.3.16.1 sensor_t structure sensor_t Input / Output Output from the library Use Data structure which holds the sensor state variables used by the library. Fields Type Comment state uint8_t internal sensor state general_counter uint8_t general purpose counter: used for calibration, drifting, etc ndil_counter uint8_t drift Integration counter threshold uint8_t sensor detection threshold type_aks_pos_hyst uint8_t holds information for sensor type, AKS group, positive recalibration flag, and hysteresis value Bit fields Use B1 : B0 Hysteresis B2 positive recalibration flag B5:B3 AKS group B7:B6 sensor type from_channel uint8_t starting channel number for sensor to_channel uint8_t ending channel number for sensor Index uint8_t index for array of rotor/slider values 6.3.16.2 touch_global_param_t structure touch_global_param_t Input / Output Input to the Library Use Holds the sensor acquisition parameters for a specific acquisition method Fields Type Comment di uint8_t Sensor detect integration (DI) limit.144 8207L-AT42-05/12 neg_drift_rate uint8_t Sensor negative drift rate in units of 200 ms. pos_drift_rate uint8_t Sensor positive drift rate in units of 200 ms. max_on_duration uint8_t Sensor maximum on duration in units of 200ms. drift_hold_time uint8_t Sensor drift hold time in units of 200 ms. pos_recal_delay uint8_t Sensor Positive recalibration delay. recal_threshold recal_threshold_t Sensor recalibration threshold. Refer Section 5.3 for Overview of Global configuration parameters. 6.3.16.3 touch_filter_data_t structure touch_filter_data_t Input / Output Output from the Library Use Touch Filter Callback data type. Fields Type Comment num_channel_signals uint8_t Length of the measured signal values list. p_channel_signals uint16_t* Pointer to measured signal values for each channel. 6.3.16.4 touch_measure_data_t structure touch_measure_data_t Input / Output Output from the Library Use This structure provides updated measure data values each time the measure complete callback function is called. Fields Type Comment p_acq_status touch_acq_status_t Acquisition status for the specific acquisition method. num_channel_signals uint8_t Length of the measured signal values list p_channel_signals uint16_t* Pointer to the sequential list of measured signal values of all channels num_channel_references uint8_t Length of the measured reference values list. p_channel_references uint16_t* Pointer to the sequential list of reference values of all channels num_sensor_states uint8_t Number of sensor state bytes. p_sensor_states uint8_t* Pointer to the sequential list of touch status of all sensors num_rotor_slider_values uint8_t Length of the Rotor and Slider position values list. p_rotor_slider_values uint8_t* Pointer to the sequential list of position of all rotors & sliders num_sensors uint8_t Length of the sensors data list. p_sensor sensor_t* Pointer to the sequential list of data of all sensors. 6.3.16.5 touch_qm_param_t structure touch_qm_param_t Input / Output Passed as input to touch_qm_sensor_update_config API & got as output from touch_qm_sensor_get_config API Use Data structure which holds the configuration parameters for a specific QMatrix sensor145 Fields Type Comment aks_group aks_group_t AKS group to which the sensor belong. detect_threshold threshold_t Detection threshold for the sensor detect_hysteresis hysteresis_t Detect hysteresis for the sensor. position_resolution resolution_t Resolution required for the sensor. position_hysteresis uint8_t Position hysteresis for the sensor 6.3.16.6 touch_at_param_t structure touch_at_param_t Input / Output Passed as input to touch_at_sensor_update_config API & got as output from touch_at_sensor_get_config API Use Data structure which holds the configuration parameters for the autonomous QTouch sensor Structure field Type Corresponds to the device register Register Field filter uint8 t ATCFG2 FILTER outsens uint8 t ATCFG2 OUTSENS sense uint8 t ATCFG2 SENSE pthr uint8 t ATCFG3 PTHR pdrift uint8 t ATCFG3 PDRIFT ndrift uint8 t ATCFG3 NDRIFT Refer Section 5.3 for an overview of FILTER (Detect Integration), PTHR (Positive Recalibration threshold), PDRIFT (Positive Drift rate) and NDRIFT (Negative Drift rate). OUTSENS - Autonomous Touch Out-of-Touch Sensitivity. For the autonomous QTouch sensor, specifies how sensitive the out-of-touch detector should be. When the sensor is not touched, the Autonomous Touch Current count register is same as the Autonomous Touch Base count register. When the sensor is touched the Autonomous Touch Current count register decreases. When using the Autonomous QTouch in proximity mode, the Autonomous Touch Base count register decreases as we move towards proximity of the sensor. The OUTSENS value can be arrived at by watching the CAT Autonomous Touch Base Count Register(at memory location 0xFFFF686Cu) and Autonomous Touch Current Count Register(at memory location 0xFFFF6870u) during a sensor touch/proximity and not in touch/proximity. A smaller difference between the Autonomous Touch Base count and Autonomous Touch Current count register can be chosen as the OUTSENS value. Range: 0u to 255u. SENSE - Autonomous Touch Sensitivity. For the autonomous QTouch sensor, specifies how sensitive the touch detector should be. When the sensor is not touched, the Autonomous Touch Current count register is same as the Autonomous Touch Base count register. When the sensor is touched the Autonomous Touch Current count register decreases. When using the Autonomous QTouch in proximity mode, the Autonomous Touch Base count register decreases as we move towards proximity of the sensor. The SENSE value can be arrived at by watching the CAT Autonomous Touch Base Count Register(at memory location 0xFFFF686Cu) and Autonomous Touch Current Count Register(at memory location 0xFFFF6870u) during a sensor touch/proximity and not in touch/proximity. A larger difference between the Autonomous Touch Base count and Autonomous Touch Current count register can be chosen as the SENSE value. Range: 0u to 255u.146 8207L-AT42-05/12 6.3.16.7 touch_qt_param_t structure touch_qt_param_t Input / Output Passed as input to touch_qt_sensor_update_config API & got as output from touch_qt_sensor_get_config API Use Data structure which holds the status parameters for the QTouch Group A or Group B sensor. Fields Type Comment aks_group aks_group_t AKS group to which the sensor belong. detect_threshold threshold_t Detection threshold for the sensor detect_hysteresis hysteresis_t Detect hysteresis for the sensor. position_resolution resolution_t Resolution required for the sensor. 6.3.16.8 touch_at_status structure touch_at_status Input / Output Output structure received as part of the Autonomous QTouch Interrupt callback function. Use Data structure which holds the status parameters for the autonomous QTouch sensor. Structure field Type Comment status change at status change t Autonomous QTouch Status change. base_count uint16_t The base count currently stored by the autonomous touch sensor. This is useful for autonomous touch debugging purposes. current_count uint16_t The current count acquired by the autonomous touch sensor. This is useful for autonomous touch debugging purposes. 6.3.16.9 touch_qm_dma_t structure touch_qm_dma_t Input / Output Input to the touch_qm_sensors_start_acquisition() API. Use Data structure which holds the DMA channel information for touch acquisition data transfer Fields Type Comment dma_ch1 uint8_t Indicates the DMA channel 1. Can take values from 0 – 11, but should not be same as dma_ch2 dma_ch2 uint8_t Indicates the DMA channel 2. Can take values from 0 – 11, but should not be same as dma_ch1 6.3.16.10 touch_qm_pin_t structure touch_qm_pin_t Input / Output Input to the library Use Data structure which holds the Pin configuration information for QMatrix147 Fields Type Comment x_lines uint32_t Bitmask that indicates the selected X pins for QMatrix. If bit n is set, Xn is enabled for QMatrix; n can be 0 to 17. Any other bits set are ignored. Note: For QMatrix operation, X8 is not available as it must be used for ACREFN function. Bit 18 - 31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 X Line - X 17 X 16 X 15 X 14 X 13 X 12 X 11 X 10 X 9 X 8 X 7 X 6 X 5 X 4 X 3 X 2 y_yk_lin es uint8_t Bitmask that indicates the selected Y pins for QMatrix. If bit n is set, Yn & Ykn is enabled for QMatrix; n can be 0 to 7. Bit 7 6 5 4 3 2 1 0 Y Line Y7 & YK7 Y6 & YK6 Y5 & YK5 Y4 & YK4 Y3 & YK3 Y2 & YK2 Y1 & YK1 Y0 & YK0 smp_di s_pin general _pin_op tions_t Specify one of the following USE_NO_PIN USE_PIN_PA12_AS_SMP USE_PIN_PA13_AS_SMP USE_PIN_PA14_AS_SMP USE_PIN_PA17_AS_SMP USE_PIN_PA21_AS_SMP USE_PIN_PA22_AS_SMP USE_PIN_PA17_AS_DIS vdiv_pi n general _pin_op tions_t Specify either USE_NO_PIN or USE_PIN_PB11_AS_VDIV 6.3.16.11 touch_at_pin_t structure touch_at_pin_t Input / Output Input to the library Use Data structure which holds the Pin configuration for Autonomous QTouch sensor Fields Type Comment atsp uint8_t Sense pair to be used for autonomous QTouch detection. Choose any one sense pair from SP0 to SP16 using the qt_pin_options_t enum. For example, if atsp is set as SP7, Sense pair 7 (CSA7, CSB7) will be assigned for autonomous QTouch detection 6.3.16.12 touch_qt_pin_t structure touch_at_pin_t Input / Output Input to the library Use Data structure which holds the Pin configuration for QTouch sensor. Fiel ds Type Comment148 8207L-AT42-05/12 sp uint3 2_t Bit n indicates Sense Pair SP[n] is selected. Choose sense pairs from SP0 to SP16. Bit 1 7- 3 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SP n - X1 6 X1 5 X1 4 X1 3 X1 2 X1 1 X1 0 X 9 X 8 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 6.3.16.13 touch_qm_reg_t structure touch_qm_reg_t Input / Output Input to the library Use Data structure which holds the Register configuration information for QMatrix This structure contains the data fields that correspond to specific fields in different registers. For a more detailed explanation of the register fields, refer to the device datasheet. For example, CHLEN field of MCCFG0 is 8 bits wide (bit 8-15 of MGCFG0 register). The user needs to set values from 0 to 255 (0xFF) in the chlen field of this structure. The library will take care of writing this to the appropriate bit position of MCCFG0 register. Fields Type Corresponds to Register Register Field div uint16 t MGCFG0 DIV chlen uint8 t MGCFG0 CHLEN selen uint8 t MGCFG0 SELEN dishift uint8 t MGCFG1 DISHIFT sync uint8 t MGCFG1 SYNC spread uint8 t MGCFG1 SPREAD dilen uint8 t MGCFG1 DILEN max uint16 t MGCFG1 MAX acctrl uint8 t MGCFG2 ACCTRL consen uint8 t MGCFG2 CONSEN cxdilen uint8 t MGCFG2 CXDILEN synctim uint16 t MGCFG2 SYNCTIM fsources uint8 t DICS FSOURCES glen uint8 t DICS GLEN intvrefsel uint8 t DICS INTVREFSEL Intrefsel uint8 t DICS INTREFSEL trim uint8 t DICS TRIM sources uint8 t DICS SOURCES shival0 uint16 t ACSHI0 SHIVAL shival1 uint16 t ACSHI1 SHIVAL shival2 uint16 t ACSHI2 SHIVAL shival3 uint16 t ACSHI3 SHIVAL shival4 uint16 t ACSHI4 SHIVAL shival5 uint16 t ACSHI5 SHIVAL shival6 uint16 t ACSHI6 SHIVAL shival7 uint16 t ACSHI7 SHIVAL149 6.3.16.14 touch_at_reg_t structure touch_at_reg_t Input / Output Input to the library Use Data structure which holds the Register configuration information for Autonomous QTouch This structure contains the data fields that correspond to specific fields in different registers. For a more detailed explanation of the register fields, refer to the device datasheet. For example, DISHIFT field of ATCFG1 is 2 bits wide (bit 28-29 of ATCFG1 register). The user needs to set values from 0 to 3 in the dishift field of this structure. The library will take care of writing this to the appropriate bit position of ATCFG1 register. Fields Type Corresponds to Register Register Field div uint16 t ATCFG0 DIV chlen uint8 t ATCFG0 CHLEN selen uint8 t ATCFG0 SELEN dishift uint8 t ATCFG1 DISHIFT sync uint8 t ATCFG1 SYNC spread uint8 t ATCFG1 SPREAD dilen uint8 t ATCFG1 DILEN max uint16 t ATCFG1 MAX at_param touch_at_param_t Autonomous Touch Sensor parameters corresponding to ATCFG2 and ATCFG3. FILTER, OUTSENS, SENSE, PTHR, PDRIFT, NDRIFT 6.3.16.15 touch_qt_reg_t structure touch_qt_reg_t Input / Output Input to the library Use Data structure which holds the Register configuration information for QTouch Group A/B. Fields Type Corresponds to Register Register Field div uint16 t TGxCFG0 DIV chlen uint8 t TGxCFG0 CHLEN selen uint8 t TGxCFG0 SELEN dishift uint8 t TGxCFG1 DISHIFT sync uint8 t TGxCFG1 SYNC spread uint8 t TGxCFG1 SPREAD dilen uint8 t TGxCFG1 DILEN max uint16 t TGxCFG1 MAX 6.3.16.16 touch_qm_config_t structure touch_qm_config_t Input / Output Input to the library Use Data structure which holds all configuration information pertaining to QMatrix Fields Type Comment num_channels uint8_t Indicates the number of QMatrix channels required by the user150 8207L-AT42-05/12 num_sensors uint8_t Indicates the number of QMatrix sensors required by the user. num_rotors_and_slider s uint8_t Indicates the number of QMatrix rotors / sliders required by the user. num_x_lines uint8_t Number of QMatrix X lines required by the user. num_y_lines uint8_t Number of QMatrix Y lines required by the user. num_x_sp uint8_t Number of X sense pairs used. This is a private variable to the Touch library. The user must provide PRIV_QM_NUM_X_SENSE_PAIRS for this input field. bl_write_count uint8_t Burst length write count. This is a private variable to the Touch library. The user must provide the PRIV_QM_BURST_LENGTH_WRITE_COUN T macro for this input field. pin touch_qm_pin_t Holds the QMatrix Pin configuration information as filled by the user. reg touch_qm_reg_t Holds the QMatrix register configuration information as filled by the user. global_param touch_global_param_ t Holds the global parameters for QMatrix as filled by the user. p_data_blk uint8_t* Pointer to the data block allocated by the user buffer_size uint16_t Size of the data block pointed to by p_data_blk. The user must provide the PRIV_QM_DATA_BLK_SIZE macro for this input field. p_burst_length uint8_t* Pointer to an array of 8-bit Burst lengths, where each 8-bit value correspond to the burst length of each channel starting from channel 0 to number of channels. filter_callback Pointer to a function Pointer to callback function that will be called before processing the signals 6.3.16.17 touch_at_config_t structure touch_at_config_t Input / Output Input to the library Use Data structure which holds the configuration parameters & register values for autonomous QTouch acquisition Fields Type Comment pin touch_at_pin_t Holds the autonomous QTouch configuration information as filled by the user. reg touch_at_reg_t Holds the autonomous QTouch register configuration information as filled by the user. touch_at_status_change_callback Pointer to a function Pointer to callback function that will be called by the library whenever there is a touch status change in the autonomous QTouch sensor151 6.3.16.18 touch_qt_config_t structure touch_qm_config_t Input / Output Input to the library Use Data structure which holds all configuration information pertaining to QMatrix Fields Type Comment num_channels uint8_t Indicates the number of QTouch Group A/B channels required by the user num_sensors uint8_t Indicates the number of QTouch Group A/B sensors required by the user. num_rotors_and_sliders uint8_t Indicates the number of QTouch Group A/B rotors / sliders required by the user. pin touch_qt_pin_t Holds the QTouch Group A/B Pin configuration information as filled by the user. reg touch_qt_reg_t Holds the QTouch Group A/B register configuration information as filled by the user. global_param touch_global_param_t Holds the global parameters for QTouch Group A/B as filled by the user. p_data_blk uint8_t* Pointer to the data block allocated by the user buffer_size uint16_t Size of the data block pointed to by p_data_blk. The user must provide the PRIV_QTA_DATA_BLK_SIZE or PRIV_QTB_DATA_BLK_SIZE macro for this input field. filter_callback Pointer to a function Pointer to callback function that will be called before processing the signals 6.3.16.19 touch_general_config_t structure touch_general_config_t Input / Output Input to the library Use Data structure which holds the configuration parameters & register values common to all acquisition methods. Fields Type Comment sync_pin general_pin_options_t Specify one of the following values indicating the pin to be assigned as SYNC pin. Refer to the device datasheet for more details. USE_NO_PIN USE_PIN_PA15_AS_SYNC USE_PIN_PA18_AS_SYNC USE_PIN_PA19_AS_SYNC USE_PIN_PB08_AS_SYNC USE_PIN_PB12_AS_SYNC maxdev uint8_t Corresponds to MAXDEV field of SSCFG register that indicates the maximum deviation when spread spectrum is enabled. Ensure that maxdev is always less than or equal to (2*div + 1). div represents div field in touch_qm_reg_t & touch_at_reg_t structures.152 8207L-AT42-05/12 csares uint32_t Corresponds to RES field of CSARES register. csbres uint32_t Corresponds to RES field of CSBRES register. 6.3.16.20 touch_config_t structure touch_config_t Input / Output Input to the library Use Pointer to this structure is passed as input to touch_qm_sensors_init & touch_at_sensor_init APIs Fields Type Comment p_qm_config touch_qm_config_t* Pointer to the QMatrix configuration structure. p_at_config touch_at_config_t* Pointer to the autonomous QTouch configuration structure. p_qta_config touch_qt_config_t* Pointer to the QTouch Group A configuration structure. p_qtb_config touch_qt_config_t* Pointer to the QTouch Group B configuration structure. p_general_config touch_general_config_t* Pointer to the general configuration structure. 6.3.16.21 touch_info_t structure touch_info_t Input / Output Output from the library Use Pointer to this structure is passed as input to touch_qm_get_libinfo & touch_at_get_libinfo APIs Fields Type Comment num_channels_in_use uint8_t Number of channels in use num_sensors_in_use uint8_t Number of sensors in use num_rotors_sliders_in_use uint8_t Number of rotor/sliders in use max_channels_per_rotor_slider uint8_t Maximum number of channels per rotor/slider allowed by the library hw_version uint32_t CAT module hardware revision as per VERSION register in CAT module. fw_version uint16_t QTouch Library version with MSB indicating the major version & LSB indicating the minor version. 6.3.17 Public Functions of QTouch Library for UC3L This section lists the public functions available in the QTouch™ libraries for AT32UC3L devices. 6.3.17.1 QMatrix API This section lists the functions that are specific to QMatrix method of acquisition. 6.3.17.1.1 touch_qm_sensors_init touch_ret_t touch_qm_sensors_init (touch_config_t *p_touch_config) Arguments Type Comment p_touch_config touch_config_t* Pointer to Touch Library input configuration structure. The touch_qm_config_t and touch_general_config_t members of the Structure should be non-NULL.153 • This API initializes the Touch library for QMatrix method acquisition. This API has to be called before calling any other QMatrix API. • Based on the input parameters, the CAT module is initialized with QMatrix method Pin and Register configuration. • The Analog comparators necessary for QMatrix operation are initialized by this API. • Both p_qm_config & p_general_config members of the input configuration structure must point to valid configuration data. • The General configuration data provided by the p_general_config pointer is common to both QMatrix, QTouch Group A, QTouch Group B and Autonomous Touch sensors. 6.3.17.1.2 touch_qm_sensor_config touch_ret_t touch_qm_sensor_config( sensor_type_t sensor_type, channel_t from_channel, channel_t to_channel, aks_group_t aks_group, threshold_t detect_threshold, hysteresis_t detect_hysteresis, resolution_t position_resolution, uint8_t position_hysteresis, sensor_id_t *p_sensor_id) Arguments Type Comment sensor_type sensor_type_t Specifies sensor type – SENSOR_TYPE_KEY or SENSOR_TYPE_ROTOR or SENSOR_TYPE_SLIDER. The SENSOR_TYPE_UNASSIGNED enum is not a valid input to this API. from_channel channel_t Start channel of the Sensor (rotor, slider or key). to_channel channel_t End channel of the Sensor (rotor, slider or key). For a key, the start and end channels must be the same. aks_group aks_group_t AKS group of this sensor. detect_threshold threshold_t Touch Detect threshold level for Sensor. detect_hysteresis hysteresis_t Value for detection hysteresis. position_resolution resolution_t Position resolution when configuring rotor / slider position_hysteresis uint8_t Position hysteresis when configuring rotor / slider p_sensor_id sensor_id_t* The Sensor ID is updated by the Touch Library upon successful sensor configuration. The Sensor ID starts with 0. • This API configures a single QMatrix Key, Rotor or Slider. • The user must provide all the sensor specific settings as input to this API. • Rotor / Slider sensor will occupy contiguous channels from from_channel to to_channel.154 8207L-AT42-05/12 • For QMatrix acquisition method, 3 to 8 Touch channels per rotor / slider are supported. Keys are always formed using 1 Touch channel. 6.3.17.1.3 touch_qm_sensor_update_config touch_ret_t touch_qm_sensor_update_config( sensor_id_t sensor_id, touch_qm_param_t *p_touch_sensor_param) Arguments Type Comment sensor_id sensor_id_t Sensor ID for which the configuration needs to be updated. p_touch_sensor_param touch_qm_param_t* Pointer to the user sensor configuration structure. • This API updates the configuration of a QMatrix sensor with values different from the ones initialized by the touch_qm_sensor_config API. If the sensor was not configured already, the API will return error. • The user must populate the structure pointed by p_touch_sensor_param with required settings before calling this API. 6.3.17.1.4 touch_qm_sensor_get_config touch_ret_t touch_qm_sensor_get_config( sensor_id_t sensor_id, touch_qm_param_t *p_touch_sensor_param) Arguments Type Comment sensor_id sensor_id_t Sensor ID for which the configuration needs to be updated. p_touch_sensor_param touch_sensor_param_t* Pointer to the user sensor configuration structure. • This API copies the current configuration of a QMatrix sensor into the user configuration structure. 6.3.17.1.5 touch_qm_channel_udpate_burstlen touch_ret_t touch_qm_channel_udpate _burstlen( channel_t channel, touch_bl_t qm_burst_length) Arguments Type Comment channel uint8_t Channel number for which the burst length is to be set. qm_burst_length touch_bl_t QMatrix burst length. The burst length value can be 1 to 255. A value of 1 can be used to disable bursting on a given channel. • This API updates the burst length of the specified QMatrix channel • This API can also be used to disable Touch measurement on a Sensor. 155 • In order to disable a Sensor, the burst length value of all the channels corresponding to the Sensor must be set to 1. A Sensor can then be re-enabled by setting the appropriate burst length for all channels using this API. Note: When disabling a sensor care must be taken such that all channels of the Sensor are set to 1. If any of the channels are missed out, it will result in undesired behavior of the Sensor. Similarly when re-enabling a Sensor, if one or more channels are left disabled with a burst length value of 1, it will result in undesired behavior of the Sensor. • The touch_qm_sensors_calibrate API needs to be called whenever burst length is updated for one or more channels before starting a new Touch measurement using the touch_qm_sensors_start_acquisition API. 6.3.17.1.6 touch_qm_update_global_param touch_ret_t touch_qm_update_global_param( touch_global_param_t *p_global_param ) Arguments Type Comment p_global_param touch_global_param_t Pointer to user global parameters structure for QMatrix. • This API can be used to update the QMatrix global parameters, with values different from the ones initialized using touch_qm_sensors_init API. 6.3.17.1.7 touch_qm_get_global_param touch_ret_t touch_qm_get_global_param( touch_global_param_t *p_global_param ) Arguments Type Comment p_global_param touch_global_param_t Pointer to user global parameters structure for QMatrix. • This API can be called to retrieve the QMatrix global parameters. 6.3.17.1.8 touch_qm_sensors_calibrate touch_ret_t touch_qm_sensors_calibrate( void ) Arguments Type Comment Void - • This API can be used to calibrate all configured Sensors. • Calibration of all Sensors must be performed when – o All the Sensors have been configured using touch_sensor_config API after initialization of the Touch Library. o A sensor or a group of Sensors have been disabled or re-enabled. 156 8207L-AT42-05/12 6.3.17.1.9 touch_qm_sensors_start_acquisition touch_ret_t touch_qm_sensors_start_acquisition( touch_time_t current_time_ms, touch_qm_dma_t *p_touch_dma, touch_acq_mode_t qm_acq_mode, void (*measure_complete_callback)( touch_measure_data_t *p_measure_data )) Arguments Type Comment current_time_ms touch_time_t Current time in ms p_touch_dma touch_qm_dma_t* DMA channels to be used for transfer to burst length & acquisition count qm_acq_mode touch_acq_mode_t Specify whether Normal acquisition mode or Raw acquisition mode should be done. void (*measure_complete_callback)( void ) void (*measure_complete_callback)( touch_measure_data_t *p_measure_data) QMatrix Measure complete callback function pointer • This API initiates a capacitive measurement on all enabled QMatrix sensors. • When normal acquisition mode is used, once the Touch measurement is completed on all the QMatrix sensors, before processing the raw acquisition data (channel_signals), a filter_callback function is optionally called by the Touch Library. • Once the filter_callback is completed, the signal values will be processed by the Touch Library. The measure_complete_callback function is then called with touch data (channel_signals, channel_references, sensor_states, sensors structure) as well as the Touch Status (sensor_states) and Rotor/Slider position (rotor_slider_values). • The touch_event_dispatcher API needs to be called as frequently as possible for the Touch Library to process the raw acquisition data. • When raw data acquisition mode is used, once the raw acquisition data is available from the CAT module for all the sensors, the measure_complete_callback function is immediately called with acquisition data (channel_signals). The channel_references, sensor_states and rotor_slider_values data are not updated by the Touch Library in this mode. • This API will return error if a Touch measurement is already in progress. • Two peripheral DMA channels must be provided using p_touch_dma for QMatrix operation. 6.3.17.1.10 touch_qm_get_libinfo touch_ret_t touch_qm_get_libinfo( touch_info_t *p_touch_info) Arguments Type Comment p_ touch_info touch_info_t* User passes the memory address at which the library information is to be stored by the library.157 • The touch_info_t structure is filled by the library with information like number of QMatrix channels, number of QMatrix sensors, number of QMatrix rotors/slider, CAT hardware version, and library version. • The QMatrix number of channels, sensors and rotors/slider indicate the total number of channels, sensors and rotor/slider in use irrespective of Touch measured being disabled or enabled. (Disabling and Re-enabling of a Sensor using the touch_qm_sensor_upate_burstlen API does not alter these values). 6.3.17.1.11touch_qm_sensor_get_delta touch_ret_t touch_qm_sensor_get_delta( sensor_id_t sensor_id, touch_delta_t *p_delta) Arguments Type Comment sensor_id sensor_id_t Sensor ID for which the delta needs to be retrieved. p_delta touch_delta_t* Pointer to Delta variable, that will be update by the Touch Library • This API retrieves the delta information associated with a specific QMatrix sensor. Delta is the difference between the current signal value and reference value. • The user must provide the sensor ID whose delta is sought along with a valid pointer to a Delta variable. • The API updates the delta variable associated with the requested sensor. 6.3.17.2 QTouch Group A and QTouch Group B API This section lists the functions that are specific to QTouch Group A/B method of acquisition. 6.3.17.2.1 touch_qt_sensors_init touch_ret_t touch_qt_sensors_init (touch_qt_grp_t touch_qt_grp, touch_config_t *p_touch_config) Arguments Type Comment touch_qt_grp touch_qt_grp_t Specify if the operation is to be performed on Group A Sensors or Group B Sensors. p_touch_config touch_config_t* Pointer to Touch Library input configuration structure. The p_qta_config/p_qtb_config (based on whether Group A is used or Group B is used) and p_general_config members of the Structure should be non-NULL. • This API initializes the Touch library for QTouch Group A or QTouch Group B method acquisition. This API has to be called before calling any other QTouch API. • Based on the input parameters, the CAT module is initialized with QTouch method Pin and Register configuration. • The p_qta_config/p_qta_config (based on whether Group A is used or Group B is used) and p_general_config members of the input configuration structure must point to valid configuration data.158 8207L-AT42-05/12 • The General configuration data provided by the p_general_config pointer is common to both QMatrix, QTouch Group A, QTouch Group B and Autonomous Touch sensors. 6.3.17.2.2 touch_qt_sensor_config touch_ret_t touch_qt_sensor_config(touch_qt_grp_t touch_qt_grp, sensor_type_t sensor_type, channel_t from_channel, channel_t to_channel, aks_group_t aks_group, threshold_t detect_threshold, hysteresis_t detect_hysteresis, resolution_t position_resolution sensor_id_t *p_sensor_id) Arguments Type Comment touch_qt_grp touch_qt_grp_t Specify if the operation is to be performed on Group A Sensors or Group B Sensors. sensor_type sensor_type_t Specifies sensor type – SENSOR_TYPE_KEY or SENSOR_TYPE_ROTOR or SENSOR_TYPE_SLIDER. The SENSOR_TYPE_UNASSIGNED enum is not a valid input to this API. from_channel channel_t Start channel of the Sensor (rotor, slider or key). to_channel channel_t End channel of the Sensor (rotor, slider or key). For a key, the start and end channels must be the same. aks_group aks_group_t AKS group of this sensor. detect_threshold threshold_t Touch Detect threshold level for Sensor. detect_hysteresis hysteresis_t Value for detection hysteresis. position_resolution resolution_t Position resolution when configuring rotor / slider p_sensor_id sensor_id_t* The Sensor ID is updated by the Touch Library upon successful sensor configuration. The Sensor ID starts with 0. • This API configures a single QTouch Key, Rotor or Slider. • The user must provide all the sensor specific settings as input to this API. • Rotor / Slider sensor will occupy contiguous channels from from_channel to to_channel. • For QTouch acquisition method, 3 Touch channels per rotor / slider are supported. Keys are always formed using 1 Touch channel. 6.3.17.2.3 touch_qt_sensor_update_config touch_ret_t touch_qt_sensor_update_config(touch_qt_grp_t touch_qt_grp, sensor_id_t sensor_id, touch_qt_param_t *p_touch_sensor_param) Arguments Type Comment touch_qt_grp touch_qt_grp_t Specify if the operation is to be performed on Group A Sensors or Group B Sensors.159 sensor_id sensor_id_t Sensor ID for which the configuration needs to be updated. p_touch_sensor_param touch_qt_param_t * Pointer to the user sensor configuration structure. • This API updates the configuration of a QTouch sensor with values different from the ones initialized by the touch_qt_sensor_config API. If the sensor was not configured already, the API will return error. • The user must populate the structure pointed by p_touch_sensor_param with required settings before calling this API. 6.3.17.2.4 touch_qt_sensor_get_config touch_ret_t touch_qt_sensor_get_config(touch_qt_grp_t touch_qt_grp, sensor_id_t sensor_id, touch_qt_param_t *p_touch_sensor_param) Arguments Type Comment touch_qt_grp touch_qt_grp_t Specify if the operation is to be performed on Group A Sensors or Group B Sensors. sensor_id sensor_id_t Sensor ID for which the configuration needs to be updated. p_touch_sensor_param touch_qt_param_t* Pointer to the user sensor configuration structure. • This API copies the current configuration of a QTouch sensor into the user configuration structure. 6.3.17.2.5 touch_qt_update_global_param touch_ret_t touch_qt_update_global_param(touch_qt_grp_t touch_qt_grp, touch_global_param_t *p_global_param ) Arguments Type Comment touch_qt_grp touch_qt_grp_t Specify if the operation is to be performed on Group A Sensors or Group B Sensors. p_global_param touch_global_param_t Pointer to user global parameters structure for QTouch Group A/B. • This API can be used to update the QTouch A or QTouch B global parameters, with values different from the ones initialized using touch_qt_sensors_init API. 6.3.17.2.6 touch_qt_get_global_param touch_ret_t touch_qt_get_global_param(touch_qt_grp_t touch_qt_grp, touch_global_param_t *p_global_param ) Arguments Type Comment touch_qt_grp touch_qt_grp_t Specify if the operation is to be performed on Group A Sensors or Group B Sensors.160 8207L-AT42-05/12 p_global_param touch_global_param_t Pointer to user global parameters structure for QTouch Group A/B. • This API can be called to retrieve the QTouch Group A or Group B global parameters. 6.3.17.2.7 touch_qt_sensors_calibrate touch_ret_t touch_qt_sensors_calibrate(touch_qt_grp_t touch_qt_grp ) Arguments Type Comment touch_qt_grp touch_qt_grp_t Specify if the operation is to be performed on Group A Sensors or Group B Sensors. • This API can be used to calibrate all configured Sensors. • Calibration of all Sensors must be performed when – o All the Sensors have been configured using touch_sensor_config API after initialization of the Touch Library. o A sensor or a group of Sensors have been disabled or re-enabled. 6.3.17.2.8 touch_qt_sensors_start_acquisition touch_ret_t touch_qt_sensors_start_acquisition(touch_qt_grp_t touch_qt_grp, touch_time_t current_time_ms, touch_qt_dma_t *p_touch_dma, touch_acq_mode_t qt_acq_mode, void (*measure_complete_callback)( touch_measure_data_t *p_measure_data )) Arguments Type Comment touch_qt_grp touch_qt_grp_t Specify if the operation is to be performed on Group A Sensors or Group B Sensors. current_time_ms touch_time_t Current time in ms p_touch_dma touch_qt_dma_t* DMA channels to be used for transfer to burst length & acquisition count qt_acq_mode touch_acq_mode_t Specify whether Normal acquisition mode or Raw acquisition mode should be done. void (*measure_complete_callback)( void ) void (*measure_complete_callback)( touch_measure_data_t *p_measure_data) QTouch Group A or Group B Measure complete callback function pointer • This API initiates a capacitive measurement on all enabled QTouch Group A or Group B sensors depending on the touch_qt_grp specified.161 • When normal acquisition mode is used, once the Touch measurement is completed on all the QTouch sensors, before processing the raw acquisition data (channel_signals), a filter_callback function is optionally called by the Touch Library. • Once the filter_callback is completed, the signal values will be processed by the Touch Library. The measure_complete_callback function is then called with touch data (channel_signals, channel_references, sensor_states, sensors structure) as well as the Touch Status (sensor_states) and Rotor/Slider position (rotor_slider_values). • The touch_event_dispatcher API needs to be called as frequently as possible for the Touch Library to process the raw acquisition data. • When raw data acquisition mode is used, once the raw acquisition data is available from the CAT module for all the sensors, the measure_complete_callback function is immediately called with acquisition data (channel_signals). The channel_references, sensor_states and rotor_slider_values data are not updated by the Touch Library in this mode. • This API will return error if a Touch measurement is already in progress. • One peripheral DMA channels must be provided using p_touch_dma for QTouch operation. 6.3.17.2.9 touch_qt _sensor_ disable touch_ret_t touch_qt_ sensor_disable(touch_qt_grp_t touch_qt_grp, sensor_id_t sensor_id) Arguments Type Comment touch_qt_grp touch_qt_grp_t Specify if the operation is to be performed on Group A Sensors or Group B Sensors. sensor_id sensor_id_t Sensor ID of the Sensor to be disabled. • This API can be used to disable Touch measurement on a QTouch Sensor. • The touch_qt_sensors_calibrate API needs to be called whenever one or more Sensors are disabled before starting a new Touch measurement using the touch_qt_sensors_start_acquisition API. • Note: Care must be taken such that a valid Sensor ID corresponding to a QTouch Group A sensor or QTouch Group B Sensor is provided. 6.3.17.2.10 touch_qt _sensor_ reenable touch_ret_t touch_qt _sensor_reenable(touch_qt_grp_t touch_qt_grp, sensor_id_t sensor_id) Arguments Type Comment touch_qt_grp touch_qt_grp_t Specify if the operation is to be performed on Group A Sensors or Group B Sensors. sensor_id sensor_id_t Sensor ID of the Sensor to be disabled. • This API can be used to reenable a disabled QTouch Sensor. 162 8207L-AT42-05/12 • The touch_qt_sensors_calibrate API needs to be called whenever one or more Sensors are reenabled before starting a new Touch measurement using the touch_qt_sensors_start_acquisition API. • Note: Care must be taken such that a valid Sensor ID corresponding to a QTouch Group A sensor or QTouch Group B Sensor is provided. 6.3.17.2.11 touch_qt_get_libinfo touch_ret_t touch_qt_get_libinfo(touch_qt_grp_t touch_qt_grp, touch_info_t *p_touch_info) Arguments Type Comment touch_qt_grp touch_qt_grp_t Specify if the operation is to be performed on Group A Sensors or Group B Sensors. p_ touch_info touch_info_t* User passes the memory address at which the library information is to be stored by the library. • The touch_info_t structure is filled by the library with the Group specific (based on touch_qt_grp input) information like number of QTouch channels, number of QTouch sensors, number of QTouch rotors/slider, CAT hardware version, and library version. • The QTouch number of channels, sensors and rotors/slider indicate the total number of channels, sensors and rotor/slider in use irrespective of Touch measured being disabled or enabled. (Disabling and Re-enabling of a Sensor using the touch_qt_sensor_disable and touch_qt_sensor_reenable API does not alter these values). 6.3.17.2.12touch_qt_sensor_get_delta touch_ret_t touch_qt_sensor_get_delta(touch_qt_grp_t touch_qt_grp, sensor_id_t sensor_id, touch_delta_t *p_delta) Arguments Type Comment sensor_id sensor_id_t Sensor ID for which the delta needs to be retrieved. p_delta touch_delta_t* Pointer to Delta variable, that will be update by the Touch Library • This API retrieves the delta information associated with a specific QTouch sensor. Delta is the difference between the current signal value and reference value. • The user must provide the sensor ID whose delta is sought along with a valid pointer to a Delta variable. • The API updates the delta variable associated with the requested sensor. 6.3.18 Autonomous touch API This section lists the functions that are specific to Autonomous QTouch sensor. 6.3.18.1.1 touch_at_sensor_init touch_ret_t touch_at_sensor_init( touch_config_t *p_touch_config )163 Arguments Type Comment p_touch_config touch_config_t* Pointer to Touch Library input configuration structure. The p_at_config and p_general_config members of the input configuration structure must be non-NULL. • This API initializes the touch library Autonomous touch sensor. This API has to be called before calling any other Autonomous touch API function. • Based on the input parameters, the CAT module is initialized with Autonomous Sensor Pin and Register configuration. • The General configuration data provided by the p_general_config pointer is common to both QMatrix, QTouch Group A, QTouch Group B and Autonomous Touch sensors. 6.3.18.1.2 touch_at_sensor_enable touch_ret_t touch_at_sensor_enable( void) Arguments Type Comment void (*touch_at_status_change_interrupt_ callback) (touch_at_status *p_at_status) void (*touch_at_status_change_interrupt _callback) (touch_at_status *p_at_status) Autonomous QTouch Callback function. • This API enables the autonomous touch sensor and initiates continuous Touch measurement on the Autonomous QTouch sensor. • When there is a change in the autonomous QTouch sensor status, the callback function as specified in touch_at_status_change_interrupt_callback will be called. The callback function lets the user know whether the autonomous QTouch sensor is currently in touch or out of touch. Note that this callback function will be called from an interrupt service routine. Hence it is recommended to have as minimal code as possible in the callback function. • This API should be called only after touch_at_sensor_init API is called. 6.3.18.1.3 touch_at_sensor_disable touch_ret_t touch_at_sensor_disable( void) Arguments Type Comment void - • This API disables the Touch measurement on the Autonomous QTouch sensor. The status change callback function is not called when the Sensor is disabled. 6.3.18.1.4 touch_at_sensor_update_config touch_ret_t touch_at_sensor_update_config( touch_at_param_t *p_at_param ) Arguments Type Comment164 8207L-AT42-05/12 p_at_param touch_at_param_t* Pointer to autonomous QTouch sensor configuration structure. • This API updates the configuration of autonomous QTouch sensor with a setting that is different from the one configured by calling touch_at_sensor_init API. • The user must populate the structure pointed by p_at_param with required settings before calling this API. 6.3.18.1.5 touch_at_sensor_get_config touch_ret_t touch_at_sensor_get_config( touch_at_param_t *p_at_param ) Arguments Type Comment p_at_param touch_at_param_t* Pointer to autonomous QTouch sensor configuration structure. • This API retrieves the current configuration of the autonomous QTouch sensor. 6.3.18.1.6 touch_at_get_libinfo touch_ret_t touch_at_get_libinfo( touch_info_t *p_touch_info) Arguments Type Comment p_touch_info touch_info_t* User passes the memory address at which the library information is to be updated. • The touch_info_t structure is filled by the library with information on the number of autonomous QTouch channels (Fixed value of 1), number of autonomous QTouch sensors (Fixed value of 1), number of autonomous QTouch rotors/slider (Fixed value of 0), CAT hardware version and library version. 6.3.18.2 Common API This section lists the functions that are common to QMatrix, QTouch Group A/B and Autonomous QTouch acquisition methods. 6.3.18.2.1 touch_event_dispatcher void touch_event_dispatcher ( void ) Arguments Type Comment Void - • This API needs to be called by the user application to allow the library to process the raw acquisition data from the sensors. • Once touch_qm_sensors_start_acquisition is called, touch_event_dispatcher API needs to be called as frequently as possible by the Host application. • The signals_callback and measure_complete_callback functions are called from the touch_event_dispatcher API context. 6.3.18.2.2 touch_deinit void touch_deinit (void)165 Arguments Type Comment void - • This API can be used to de-initalize the Touch Library and disable the CAT module. • Calling this API de-initializes the Touch Library for Sensors corresponding to all methods of acquisition (QMatrix, QTouch Group A, QTouch Group B and Autonomous QTouch). 6.3.19 Integrating QTouch libraries for AT32UC3L in your application This section illustrates the key steps required in integrating the QTouch™ library in your application. a. For your design, you would need the following information to select the correct library variant • Device to be used for the design – Current library supports AT32UC3L064, AT32UC3L032, AT32UC3L016 device variants. • Compiler platform you intend to use to integrate the libraries. b. Copy the library variant that was selected in step one to your project’s working directory or update your project to point to the library selected. c. Include touch_api_at32uc3l.h & touch_config_at32uc3l.h header files of the QTouch™ library in your application. The header files can be found in the library installation folder. d. Initialize/create and use the Touch APIs in your application • Set the various configuration options using the touch_config_at32uc3l.h file. • Initialize and configure the sensors in the Host application. • The Host application also has to provide the required timing so as to perform Touch measurement at regular intervals. e. General application notes • Ensure that there are no conflicts between the resources used by the Touch library and the host application • Ensure that the stack size is adjusted to factor in the stack depth required for the operation of the touch libraries. 6.3.20 MISRA Compliance Report of QTouch Library for UC3L This section lists the compliance and deviations for MISRA standards of coding practice for the UC3L QTouch libraries. 6.3.21 What is covered The MISRA compliance covers the QTouch library for AT32UC3L devices. The Example projects and associated code provided is not guaranteed to be MISRA compliant. 6.3.22 Target Environment Development Environment IAR Embedded Workbench for Atmel AVR32 MISRA Checking software The MISRA C Compliance has been performed for the library using MISRA C 2004 Rules in IAR Workbench for Atmel AVR32 MISRA Rule set applied MISRAC 2004 Rule Set, All including advisory 6.3.23 Deviations from MISRA C Standards The QTouch library was subjected to the above mentioned MISRA compliance rules. The following table lists the exceptions in the AT32UC3L QTouch library source code and also provides explanation for these exceptions.166 8207L-AT42-05/12 Apart from these, there were many exceptions in the standard header files supplied by the tool chain and those are not captured here. Rule Rule Description Advisory/ Required Exception noted / How it is addressed 1.1 All code shall conform to ISO 9899 standard C, with no extensions permitted. Required This Rule is not supported as the library implementation requires IAR extensions like __interrupt. These intrinsic functions relate to device hardware functionality, and cannot practically be avoided. 5.4 A tag name shall be a unique identifier Required This is violated as for the reason that enumerated types are mixed with other types. This is caused by integers being assigned to enumerated types in some places to save code space 6.3 The basic types of char, int, short, long, float, and double should not be used, but specific-length equivalents should be typedef'd for the specific compiler, and these type names used in the code Advisory The type bool supported by the compiler violate this rule. 10.3 The value of a complex expression of integer type shall only be cast to a type that is not wider and of the same signedness as the underlying type of the expression Required This is required in the code to do align some pointers in the data block memory. Cannot be avoided. 11.3 A cast should not be done between a pointer type and an integral type Advisory This is required in the code to do align some pointers in the data block memory. Cannot be avoided. 17.4 Array indexing shall be the only allowed form of pointer arithmetic Required Pointer increment has been done in some places for sequential access of signals, references, etc. 19.13 The # and ## preprocessor operators should not be used Advisory This is required for implementation of a macro for ease of use & abstraction 6.3.24 Known Issues with QTouch Library for UC3L • When the IAR Example Project is build, the IAR32 compiler reports the following Warning - Warning[Pe047]: incompatible redefinition of macro "AVR32_PM_PPCR_MASK" (declared at line 607 of "C:\Program Files\IAR Systems\Embedded C:\Program Files\IAR Systems\Embedded Workbench 5.6\avr32\INC\avr32\pm_400.h 467 Workbench 5.6\avr32\INC\avr32/uc3l064.h"). In order to avoid this, this warning (Pe047) has been disabled using the Diagnostics option in the IAR32 Project.167 6.4 QTouch Library for ATtiny20 device ATMEL QTouch Library for ATtiny20 can be used for embedding capacitive touch buttons functionality into ATtiny20 device application. This Section describes the QTouch Library Application Programming API and Configuration interface for QTouch method acquisition using the ATtiny20 devices. 6.4.1 Salient Features of QTouch Library for ATtiny20 6.4.1.1 QTouch method sensor • 1 Physical pin per Touch Button. • 1 to 5 Touch Buttons can be configured. • Individual Sensor Threshold, Sensor Hysteresis and Sensor Global acquisition parameters can be configured. • Adjacent Key Supression (AKS) support. • QTouch Studio support for Touch data analysis. • ‘C’ Programming interface for easy inclusion of User application. 6.4.2 Compiler tool chain support for ATtiny20 The QTouch libraries for ATtiny20 devices are supported for the following compiler tool chains. Tool Version IAR Embedded Workbench for Atmel AVR. IAR Compiler. 5.5 Table 17 Compiler tool chains support for ATtiny20 QTouch Library 6.4.3 Overview of QTouch Library for ATtiny20 For an overview of QTouch method based capacitive touch acquisition, refer Section 5.2.1 QTouch Acquistion method. The QTouch Library for ATtiny20 device allows for Sensor configuration and Sensor Acquisition parameter setting. Based on the input Sensor configuration, the QTouch Library takes care of the capacitive touch acquisition data capture operations on the external capacitive touch sensors. The captured Touch Data and Touch Button ON/OFF Status information is then available for user application. The diagram below indicates a Typical Sensor arrangement using the Tiny20 device. The QTouch Library uses the ATtiny20 ADC Module to peform capacitive Touch measurements. The ADC module must be enabled by the Host Application and configured in Free running mode for QTouch Library to function correctly. The PA0 pin must be configured as Output pin and should be in HIGH state before the qt_measure_sensors API is called. Port pins PA1 to PA7 can be used to support upto 5 Touch Buttons. The Touch Buttons must be connected to sequential Port pins. However, it is not necessary to start the first Touch Button on Port pin PA1. For Example, when 3 Touch Buttons are required, they can by connected to pins PA5, PA6 and PA7. The Sensor numbering is always in the increasing order of Port pin.168 8207L-AT42-05/12 Figure 48 Schematic overview of QTouch on Tiny20 6.4.4 API Flow diagram for ATtiny20 For the QTouch Libraries, the timing information is provided by the Host Application by updating the ‘time_current_ms’ variable in the Timer ISR. The QTouch Library uses this variable to calculate the necessary timing for Max ON Duration, Drift and Recalibration functionality. Before using the QTouch Libraries, the Timer ISR must be configured appropriately. Also, the Timer Interrupt is used to update the ‘time_to_measure_touch’ variable inorder to start a capacitive touch measurement. It is recommended to call qt_measure_sensors within 100ms each time to avoid error in QTouch Library timing. The touch_config_tiny20.h configuration header file can be used to set the desired number of Touch Sensors (Buttons) as well as individual sensor Threshold, Hysteresis and Recalibration parameters. The Sensor Global Configuration parameters must be specified using the IAR Linker define options. Figure 49 Linker configuration options for Tiny20 ATtiny20 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 1Kohm 1Kohm 1Kohm 1Kohm 1Kohm Touch Button 1 Touch Button 2 Touch Button 3 Touch Button 4 Touch Button 5 VCC No Connection GND169 Figure 50 QTouch method for Tiny20 API Flow diagram 6.4.5 QTouch Library configuration parameters for ATtiny20 The Table below describes the various configuration parameters corresponding to the ATtiny20. qt_init_sensing() Setup the desired device clock using the init_system() in main.c Using the init_timer(), setup the Timer ISR such that the Timer Interrupt occurs every 20ms . Enable the ADC and configure in Free running mode. Using the touch_config_tiny20.h configuration file, 1. Set the desired number of Sensors. 2. Set the Individual sensor Threshold, Hysteresis, Recalibration Threshold and Delay cycle values. 3. Set the desired Sensor Global acquisition parameters using the IAR Project->Linker options. 4. The DEF_QT_ADC_CHANNEL_START_INDEX Linker option can be used to set the starting ADC Channel. Add any Host Application (a Sample LED application is available with the Tin20 EK IAR Example project). qt_measure_sensors() Call in loop time_to_ measure_touch Measured data and Touch Status Host Application code170 8207L-AT42-05/12 Parameter Description DEF_QT_QDEBUG_ENABLE Enable/Disable QDebug debug data communication to QTouch Studio. DEF_QT_NUM_SENSORS QTouch number of Sensors. Range: 1u to 5u. DEF_QT_SENSOR_0_THRESHOLD, DEF_QT_SENSOR_1_THRESHOLD, DEF_QT_SENSOR_2_THRESHOLD, DEF_QT_SENSOR_3_THRESHOLD, DEF_QT_SENSOR_4_THRESHOLD Sensor detection threshold value. Range: 1u to 255u. DEF_QT_SENSOR_0_HYSTERESIS, DEF_QT_SENSOR_1_HYSTERESIS, DEF_QT_SENSOR_2_HYSTERESIS, DEF_QT_SENSOR_3_HYSTERESIS, DEF_QT_SENSOR_4_HYSTERESIS Sensor detection hysteresis value. Refer hysteresis_t in touch_api_tiny20.h HYST_50 = (50% of Sensor detection threshold value) HYST_25 = (25% of Sensor detection threshold value) HYST_12_5 = (12.5% of Sensor detection threshold value) HYST_6_25 = (6.25%, but value is hardlimited to 2) DEF_QT_SENSOR_0_RECAL_THRESHOLD, DEF_QT_SENSOR_1_RECAL_THRESHOLD, DEF_QT_SENSOR_2_RECAL_THRESHOLD, DEF_QT_SENSOR_3_RECAL_THRESHOLD, DEF_QT_SENSOR_4_RECAL_THRESHOLD Sensor recalibration threshold value. Refer recal_threshold_t in touch_api_tiny20.h RECAL_100 = (100% of Sensor detection threshold value) RECAL_50 = (50% of Sensor detection threshold value) RECAL_25 = (25% of Sensor detection threshold value) RECAL_12_5 = (12.5% of Sensor detection threshold value) RECAL_6_25 = (6.25%, but value is hardlimited to 4) DEF_QT_DELAY_CYCLES Delay cycles that determine the capacitance charge transfer time. Range: 1, 2, 4, 8 or 10 internal System Clock cycles. DEF_QT_ADC_CHANNEL_START_INDEX ADC Channel starting index. Range: 1u to 7u. DEF_QT_AKS_ENABLE Enable/Disable Adjacent Key suppression (AKS) on all channels. DEF_QT_DI Sensor detect integration (DI) limit.Range: 0u to 255u. Refer Section 5.3 and Section 5.4 for more info. DEF_QT_NEG_DRIFT_RATE*(See Note 1) Sensor negative drift rate. Units: 100ms, Range: 1u to 127u. Refer Section 5.3 and Section 5.4 for more info. DEF_QT_POS_DRIFT_RATE*(See Note 1) Sensor positive drift rate. Units: 100ms, Range: 1u to 127u. Refer Section 5.3 and Section 5.4 for more info. DEF_QT_MAX_ON_DURATION Sensor maximum on duration. Units: 100ms, Range: 0u to 255u. Refer Section 5.3 and Section 5.4 for more info. DEF_QT_DRIFT_HOLD_TIME Sensor drift hold time. Units: 100ms, Range: 1u to 255u. Refer Section 5.3 and Section 5.4 for more info. DEF_QT_POS_RECAL_DELAY Positive Recalibration delay. Range: 1u to 255u. Refer Section 5.3 and Section 5.4 for more info. DEF_QT_NUM_SENSORS_SYM QTouch number of Sensors Symbol for QTouch Library. MUST be the same as DEF_QT_NUM_SENSORS. DEF_QT_BURST_LENGTH Specifies the no:of burst sequence required for a sensor. Multiple burst for adjusting sensitivity by increasing the resolution of the Signal measured.Use higher value for increasing sensitivity. Values: 1u, 4u and 16u, 32u. With a setting of 32u, the Touch Response time would be sluggish. DEF_CHARGE_SHARE_DELAY Defines the Charging Share Delay time as an additional Number of CPU Cycles delay to be introduced during the Charge transfer. Values:0 to 255. Table 18 QTouch Library for ATtiny20 Configuration parameters171 Note1: For the case of ATtiny20 devices, a ‘touch’ causes the Signal value measured on the Sensor to increase above the Sensor Reference value (In the case of Generic Library devices, a ‘touch’ causes the Signal value to decrease below the Reference value). However, the Negative drift rate and Positive drift rate functionality for the case of Tiny20 devices shall be consistent with the Generic Library case. So, it is recommended to have a ‘Slower’ Negative Drift rate (4 seconds is the default setting) and a ‘Faster’ Positive Drift rate (1 second is the default setting) for the Tiny20 device. 6.4.6 QTouch Library ATtiny20 Example projects The QTouch method IAR Example project for the Tiny20 Evaluation Kit can be found in the following path. \Device_Specific_Libraries\8bit_AVR\AVR_Tiny_Mega_XMega\ATtiny20\ tiny20_ek_iar_qt_example The Example projects demonstrate the 5 button sensor configuration with a Sample LED application. The Example projects also support QDebug data transfer to QTouch Studio – Touch Analyzer PC Application. It is possible to configure the number of Sensors in the Example project from 1 to 5 for testing on the ATtiny20 Evaluation kit. 6.4.7 QTouch Library ATtiny20 code and data memory requirements The code and data memory requirements for QTouch Library for ATtiny20 devices is captured in the Table below. The Table indicates these values for the standalone library and not for the entire Example Project application. Library Number of Sensors Code Memory Data memory CStack/RStack libtiny20-5qt-k- 0rs 5 1231 + 15 bytes Const data 70 CStack= 0x1C bytes RStack= 10 (16 bytes) is the Recommended setting. libtiny20-5qt-k- 0rs 4 1231 + 12 bytes Const data 60 CStack= 0x1C bytes RStack= 10 (16 bytes) is the Recommended setting. libtiny20-5qt-k- 0rs 3 1231 + 9 bytes Const data 50 CStack= 0x1C bytes RStack= 10 (16 bytes) is the Recommended setting. libtiny20-5qt-k- 0rs 2 1231+ 6 bytes Const data 40 CStack= 0x1C bytes RStack= 10 (16 bytes) is the Recommended setting. libtiny20-5qt-k- 0rs 1 1231 + 3 bytes Const data 30 CStack= 0x1C bytes RStack= 10 (16 bytes) is the Recommended setting. Table 19 QTouch Library for ATtiny20 Memory requirements172 8207L-AT42-05/12 Data memory for ATtiny20 QTouch Library include the following. 10. QTouch Library data memory – 19 bytes, allocated inside the Library. 11. channel_signals – 2 bytes per Sensor, allocated in main.c 12. channel_references – 2 bytes per Sensor, allocated in main.c 13. sensor_delta – 2 bytes per Sensor, allocated in main.c 14. sensor_general_counter – 2 bytes per Sensor, allocated in main.c 15. sensor_state – 1 byte per Sensor, allocated in main.c 16. sensor_ndil_counter – 1 byte per Sensor, allocated in main.c 17. sensor_states – 1 byte, allocated in main.c Const Data memory for ATtiny20 QTouch Library include the following. 1. sensor_threshold, 1 byte per Sensor, allocated in main.c 2. sensor_hyst_threshold, 1 byte per Sensor, allocated in main.c 3. sensor_recal_threshold, 1 byte per Sensor, allocated in main.c 6.5 QTouch Library for ATtiny40 device ATMEL QTouch Library for ATtiny40 can be used for embedding capacitive touch buttons functionality into ATtiny40 device application. This Section describes the QTouch Library Application Programming API and Configuration interface for QTouch method acquisition using the ATtiny40 devices. 6.5.1 Salient Features of QTouch Library for ATtiny40 6.5.1.1 QTouch method sensor • One Physical pin per Touch Button. • 1 to 12 Touch Buttons can be configured. • Individual Sensor Threshold, Sensor Hysteresis and Sensor Global acquisition parameters can be configured. • Signal resolution can be configured. • Charge Share Delay can be configured. • Adjacent Key Supression (AKS) support. • QTouch Studio support for Touch data analysis. • ‘C’ Programming interface for easy inclusion of User application.173 6.5.2 Compiler tool chain support for ATtiny40 The QTouch libraries for ATtiny40 devices are supported for the following compiler tool chains. Tool Version IAR Embedded Workbench for Atmel AVR. IAR Compiler. 6.10 Table 20 Compiler tool chains support for ATtiny40 QTouch Library 6.5.3 Overview of QTouch Library for ATtiny40 For an overview of QTouch method based capacitive touch acquisition, refer Section 5.2.1 QTouch Acquistion method. The QTouch Library for ATtiny40 device allows for Sensor configuration and Sensor Acquisition parameter setting. Based on the input Sensor configuration, the QTouch Library takes care of the capacitive touch acquisition data capture operations on the external capacitive touch sensors. The captured Touch Data and Touch Button ON/OFF Status information is then available for user application. The diagram below indicates a Typical Sensor arrangement using the Tiny40 device. For one channel configuration, two ADC pins are used for acquisition. For number of touch buttons greater than one, no extra ADC pins are used. Port pins PA0 to PA7 and PB0 to PB3 can be used to support upto 12 Touch Buttons. The Touch Buttons may be connected anywhere on the said port pins. The Sensor numbering is always in the increasing order of Port pin. Figure 51 Schematic overview of QTouch on Tiny40 ATtiny40 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 1Kohm Touch Button 1 VCC GND Touch Button 0 PB0 PB1 PB2 PB3 1Kohm 1Kohm Touch Button 3 Touch Button 2 1Kohm Touch Button 5 Touch Button 4 1Kohm 1Kohm Touch Button 7 Touch Button 6 1Kohm Touch Button 9 Touch Button 8 1Kohm 1Kohm Touch Button 11 Touch Button 10 1Kohm 1Kohm 1Kohm174 8207L-AT42-05/12 6.5.4 API Flow diagram for ATtiny40 For the QTouch Libraries, the timing information is provided by the Host Application by updating the ‘time_current_ms’ variable in the Timer ISR. The QTouch Library uses this variable to calculate the necessary timing for Max ON Duration, Drift and Recalibration functionality. Before using the QTouch Libraries, the Timer ISR must be configured appropriately. Also, the Timer Interrupt is used to update the ‘time_to_measure_touch’ variable inorder to start a capacitive touch measurement. The touch_config_dp.h configuration header file must be used to set the number of channels based on the library used. For example, if the library used is a 12 channel library then QT_NUM_CHANNELS must be specified as 12 in the touch_config_dp.h. This information must be provided irrespective of the number of channels actually used. The desired number of touch buttons used can be enabled using the qt_enable_key() routine. The channel numbers are sequential from Port A through Port B. Also, individual sensor Threshold, Hysteresis, AKS group and Recalibration parameters can be set using this function call. The Sensor Global Configuration parameters can also be set by the user by directly accessing the global configuration data structure. When developing a Host application for ATtiny40 device, ensure that the ADC prescalar is set in such a way that it is in the range of 50 KHz to 250 KHz. For example, if the main clock is running at 8MHz then set the ADC prescalar to 32 or more. This must be done to ensure proper touch sensing acquisition.175 Figure 52 QTouch method for Tiny40 API Flow diagram 6.5.5 QTouch Library configuration parameters for ATtiny40 The Table below describes the various configuration parameters corresponding to the ATtiny40 QTouch Library.176 8207L-AT42-05/12 Parameter Description DEF_QT_DI Sensor detect integration (DI) limit.Range: 0u to 255u. Refer Section 5.3 and Section 5.4 for more info. DEF_QT_NEG_DRIFT_RATE*(See Note 1) Sensor negative drift rate. Units: 100ms, Range: 1u to 127u. Refer Section 5.3 and Section 5.4 for more info. DEF_QT_POS_DRIFT_RATE*(See Note 1) Sensor positive drift rate. Units: 100ms, Range: 1u to 127u. Refer Section 5.3 and Section 5.4 for more info. DEF_QT_MAX_ON_DURATION Sensor maximum on duration. Units: 100ms, Range: 0u to 255u. Refer Section 5.3 and Section 5.4 for more info. DEF_QT_DRIFT_HOLD_TIME Sensor drift hold time. Units: 100ms, Range: 1u to 255u. Refer Section 5.3 and Section 5.4 for more info. DEF_QT_RECAL_THRESHOLD • Setting of 0 = 100% of detect threshold • Setting of 1 = 50% of detect threshold • Setting of 2 = 25% of detect threshold • Setting of 3 = 12.5% of detect threshold • Setting of 4 = 6.25% of detect threshold Refer Section 5.3 and Section 5.4 for more info. DEF_QT_POS_RECAL_DELAY Positive Recalibration delay. Range: 1u to 255u. Refer Section 5.3 and Section 5.4 for more info. DEF_QT_PULSE_SCALE Default value is 0x0 means 1 oversamples and scaling/averaging factor 1. Refer Note on using Pulse Scale Value: DEF_QT_CHARGE_SHARE_DELAY Charge Share Delay. Range: 1u – 255u. This value needs to be increased if we use high value of series resistor on sensor pin to ensure proper charge time. Table 21 QTouch Library for ATtiny40 Configuration parameters Note1: For the case of ATtiny40 devices, a ‘touch’ causes the Signal value measured on the Sensor to increase above the Sensor Reference value (In the case of Generic Library devices, a ‘touch’ causes the Signal value to decrease below the Reference value). However, the Negative drift rate and Positive drift rate functionality for the case of Tiny40 devices shall be consistent with the Generic Library case. So, it is recommended to have a ‘Slower’ Negative Drift rate (4 seconds is the default setting) and a ‘Faster’ Positive Drift rate (1 second is the default setting) for the Tiny40 device. Note on using Pulse Scale Value: This variable is used to increase the resolution of the signal. qt_pulse_scale variable is available to change the oversampling and scaling factor.This is available for all the channels and now with this one should increase the gain for each channel individually. Function set_qt_pulse_scale is provided in main.c file for reference which will change the values of pulse scale variable. This variable is divided into higher(pulse/oversamples) and lower(scaling/averaging) nibble.The higher nibble corresponds to number of oversamples and lower nibble corresponds to scaling/averaging. The Pulse value is the power of 2 number of pulses which will accumulate their results.The Scale value is the power of 2 number which will divide the accumulated result from the pulse measurements. The maximum value of higher nibble possible is 0xA and maximum value of lower nibble is 0xA.177 Consideration should be taken on the overall effect on timing when setting Pulse values. A high gain setting will add considerably time taken to acquire all channels. 6.5.6 QTouch Library ATtiny40 Example projects The QTouch method IAR Example project for the Tiny40 Evaluation Kit can be found in the following path. \Device_Specific_Libraries\8bit_AVR\AVR_Tiny_Mega_XMega\ATtiny40\tiny40_qt_example_iar The Example projects demonstrate the 12 button sensor configuration. The Example projects also support QDebug data transfer to QTouch Studio – Touch Analyzer PC Application. It is possible to configure the number of Sensors in the Example project from 1 to 12 for testing on the ATtiny40 Evaluation kit. 6.5.7 QTouch Library ATtiny40 code and data memory requirements The code and data memory requirements for QTouch Library for ATtiny40 devices is captured in the Table below. The Table indicates these values for the standalone library and not for the entire Example Project application. Library Number of Sensors Code Memory Data memory CStack/RStack libtiny40_4qt_k_0rs 4 2400 149 CStack= 40 bytes RStack= 24 bytes libtiny40_8qt_k_0rs 8 2400 193 CStack= 40 bytes RStack= 24 bytes libtiny40_12qt_k_0rs 12 2500 235 CStack= 40 bytes RStack= 24 bytes Table 22 QTouch Library for ATtiny40 Memory requirements 6.5.8 Interrupt Handling in QTouch ADC In case of ATtiny40, the Interrupts are disabled for each acquisition sample means once per charge transfers cycle and typically this is 1184 Instruction cycles. Depending on number of oversamples and channels, the total number of times the interrupts are disabled will vary. Total number of times interrupts disabled = No of oversamples * No of channels. The Touch measurement will not be affected by longer ISR execution, only the response time will get affected. The acquisition time is a lot more predictable since a fixed amount of pulses/oversamples are used. The time to execute one measurement will depend on various software parameters like no of oversamples, Charge share delay and CPU Frequency. For one button to execute with following below parameters, QTouch ADC takes around 0.7 msec. CPU Freq=4 MHZ, Number of oversamples=1, Charge Share Delay =1.178 8207L-AT42-05/12 7 Generic QTouch Libraries for 2K Devices 7.1 Introduction This section provides information about the QTouch library Acquisition Support for Tiny devices with 2K Flash memory. These libraries have the same API’s as Generic libraries, except for a few which are not supported.Information about the API’s are provided in touch_api_2kdevice.h file which is placed at location mentioned in section 5.6.10.1 7.2 Devices supported The list of different devices that are supported by the QTouch library for 2K devices is given below: 1. ATtiny2313A 2. ATtiny261A 3. ATtiny24A 4. ATtiny25A Complete information is available in Library_Selection_Guide.xls. 7.3 Salient Features of QTouch Library for 2K Devices • 1 to 4 Touch Buttons can be configured. Supports maximum of 4 Buttons. • Libraries in variants of 1, 2 and 4 channels are provided. • 2K device libraries are supported only for IAR. • Library API’s are same as Generic QTouch libraries. • Support for more than one pair of SNS and SNSK ports are not available for 2K tiny devices. NOTE: No AKS, no Power Optimization and no pin configurability support in case of 2K device libraries. The change information like library status flags which reflects if there is any change in Reference values, rotor slider position change status flags etc are not part of the 2K device libraries except burst again flag. 7.4 Library Variants For Different library variants available for 2K Devices, please refer Library_Selection_Guide.xls 7.5 QTouch API for 2K Devices and Usage This section describes the different API’s used during touch sensing. Using the API, Touch sensors and the associated channels can be defined. Once touch sensing has been initiated by the user, the host application can use the API to make touch measurements and determine the status of the sensors.Refer section 5.6.6 and Figure 5.6 for API usage 7.5.1 touch_api_2kdevice.h - public header file179 The touch_api_2kdevice.h header file is the public header file which needs to be included in user’s application. The type definitions and function prototypes of the API’s listed in sections 5.6.3 , 5.6.4 and 5.6.5 The touch_api_2kdevice.h header file is located in the library distribution in the following directory. • ..\Atmel_QTouch_Libraries_5.x\Generic_QTouch_Libraries\include The constant/symbol definitions can be placed in any of the following. Defined user’s project options. All the constants/symbols must be defined for both the compiler and assembler preprocessing definitions. As an alternative, it is also declared in the touch_qt_config_2kdevice.h file. The user may modify these defined values based on the requirements. Global settings common to all sensors and sensor specific settings are listed in sections 5.3 and 5.4 respectively 7.5.2 Sequence of Operations and Using the API Figure 5-6 illustrates the sequence of operations required to be performed to add touch to an end application. By using the simple API’s as illustrated in the sequence flowchart, the user can add touch sensing in his design. 7.5.2.1 Channel Numbering • 1-channel library – supports 1 channel using 1 consecutive pins on different SNS and SNSK ports (or) supports 1 channel using 2 consecutive pins on the same port used for both SNS and SNSK lines. This library requires 1 or 2 port. • 2-channel library – supports up to 2 channels using 2 consecutive pins on different SNS and SNSK ports (or) supports up to 2 channels using 4 consecutive pins on the same port used for both SNS and SNSK lines. This library requires 1 or 2 ports. • 4-channel library – supports up to 4 channels using 4 consecutive pins on different SNS and SNSK ports (or) supports up to 4 channels using 8 consecutive pins on the same port used for both SNS and SNSK lines. This library requires 1 or 2 ports. 7.5.2.1.1 Channel numbering when routing SNS and SNSK pins to different ports When SNS and SNSK pins are available on different ports, the channel numbering follows the pin numbering in the ports selected. • The channel numbers follow the pin numbers starting with the LSB (pin 0 is channel 0 and pin 3 is channel 3). • Since the channel numbers are fixed to the pins of the SNS and SNSK ports, if the design calls for use of a subset of the pins available in the SNS and SNSK ports, the user has to skip the channel numbers of the unused SNS and SNSK pins. For example, on a 4 channel configuration using SNS and SNSK ports, if pin 2 is not used for touch sensing ( on both SNS and SNSK ports), channel number 2 is unavailable and care should be taken while configuring the channels and sensors to avoid using this channel. Also, the SNS and SNSK masks are assigned properly as explained in section 7.5.2.2180 8207L-AT42-05/12 7.5.2.1.2 Channel numbering when routing SNS and SNSK pins to the same port When SNS and SNSK pins are connected to the same port, the even pin numbers will be used as SNS pins and the odd pins will be used as the SNSK pins. • The number of channels supported will be limited 4 channels • For e.g., for a 4 channel configuration where the SNS and SNSK pins are connected to Port B, the port pins 0&1 are used for channel 0. • The channel number is derived from the position of the pins used for SNS and SNSK lines for any channel. channel number = floor( [SNS(or SNSK) pin number] / 2 ) o For e.g., pins 4 and 5 are connected to a SNS/SNSK pair and the channel number associated with the SNS/SNSK pin is 2. 7.5.2.2 Rules For Configuring SNS and SNSK masks for 2K Devices The libraries internally need SNS_array and SNSK_array masks. These masks need to be defined under Macro QTOUCH_STUDIO_MASKS as per the following rules given below: 1. In case of Interport, SNS_array[0] and SNSK_array[0] mask is used for configuring the Channel0 and Channel2.And SNS_array[1] and SNSK_array[1] mask is used for configuring the Channel1 and Channel3.And In case of Intraport SNS_array[0] and SNSK-array[0] are used for all the four channels configured based on enabled bits in SNS_array[0] and SNSK-array[0]. 2. The channel numbers are allocated based on enabled SNS pins starting from LSBBit. In case of Interport, Keys on adjacent channels should be placed on different masks. Channel0 and Channel1 should be on different SNS/SNSK masks ie channel0 on SNS_array[0]/SNSK_array[0] and channel1 on SNS_array[1]/ SNSK_array[1]. But in case of Intraport, Keys on adjacent channels should be placed on same masks. Channel0 and Channel2 should be on same mask ie SNS_array[0]/SNSK_array[0] and Channel1 and Channel3 on SNS_array[1]/ SNSK_array[1]. 7.5.2.2.1 Configuring SNS and SNSK masks in case of Interport: 1. Enable the Bit0 in SNS_array[0] and Bit0 in SNSK_array[0] mask when enabling Channel0. 2. Enable the Bit1 in SNS_array[1] and Bit1 in SNSK_array[1] mask when enabling Channel1. 3. Enable the Bit2 in SNS_array[0] and Bit2 in SNSK_array[0] mask when enabling Channel2. 4. Enable the Bit3 in SNS_array[1] and Bit3 in SNSK_array[1] mask when enabling Channel3. Example 1: In a 4 channel library, two keys on channel 0 and 3 are enabled.SNS on Port A and SNSK on Port B .Channel0 will A0B0 and Channel3 will be A3B3. The SNS and SNSK masks will be SNS_array[0]=0x01; SNS_array[1]=0x08; SNSK_array[0]=0x01; SNSK_array[1]=0x08;181 7.5.2.2.2 Configuring SNS and SNSK masks in case of Intraport: 1. Enable the Bit0 in SNS_array[0] and Bit1 in SNSK_array[0] mask when enabling Channel0. 2. Enable the Bit2 in SNS_array[0] and Bit3 in SNSK_array[0] mask when enabling Channel1. 3. Enable the Bit4 in SNS_array[0] and Bit5 in SNSK_array[0] mask when enabling Channel2. 4. Enable the Bit6 in SNS_array[0] and Bit7 in SNSK_array[0] mask when enabling Channel3. Example 1: In a 4 channel library, two keys on channel 0 and 3 are enabled.SNS and SNSK on Port B .Channel0 will B0B1 and Channel3 will be B6B7. The SNS and SNSK masks will be SNS_array[0]=0x41; SNS_array[1]=0x00; SNSK_array[0]=0x82; SNSK_array[1]=0x00; 7.5.3 Integrating QTouch libraries for 2K Devices in your application In order to Integrate QTouch libraries for 2K devices, the constants and symbol names listed in Table 1 below need to be defined in the user application. These can be defined in either the compiler/assembler preprocessing definitions or in the touch_t_config_2kdegice.h file. Example projects are provided for all the four devices supported.Refer 5.6.10.1 for directory structure of all the files. Table 1: Constant and symbol name definitions required to use the QTouch acquisition method libraries for 2K device libraries Symbol / Constant name Range of values Comments _QTOUCH_ This macro has to be defined in order to use QTouch libraries. SNS & SNSK Refer to library selection guide. _SNS_SNSK_SAME_PORT_ Comment/uncomment define To be enabled if the same port is used for SNSK and SNS pins for QTouch. If SNSK and SNS pins are on different ports then this definition is not required. QT_NUM_CHANNELS 1, 2 and 4 for 2K device libraries. QT_DELAY_CYCLES 1 to 255 Please refer to section 5.6.8. QTOUCH_STUDIO_MASKS This macro has to be defined in order to use QTouch libraries for 2K devices. SNS_array and SNSK_array masks variablesare initialized under this Macro in main file.Refer section 7.5.2.2182 8207L-AT42-05/12 The following files are to be added along with the touch library and user application before compilation: • For ATtiny 2K devices - touch_api_2kdevice.h, touch_qt_config_2kdevice.h and qt_asm_tiny_mega_2kdevice.S 7.6 MISRA Compliance Report This section lists the compliance and deviations for MISRA standards of coding practice for the QTouch acquisition method libraries for 2K devices 7.6.1 What is covered The QTouch acquisition method libraries for 2K devices adhere to the MISRA standards. The additional reference code provided in the form of sample applications is not guaranteed to be MISRA compliant. 7.6.2 Target Environment Development Environment IAR Embedded Workbench MISRA Checking software The MISRA C Compliance has been performed for the library using MISRA C 2004 Rules in IAR Workbench development environment. MISRA Rule set applied MISRAC 2004 Rule Set 7.6.3 Deviations from MISRA C Standards 7.6.3.1 QTouch acquisition method libraries for 2K devices The QTouch acquisition method libraries were subject to the above mentioned MISRA compliance rules. The following exceptions have not been fixed as they are required for the implementation of the library. Applicable Release QTouch libraries Rule No Rule Description Exception noted / How it is addressed 1.1 Rule states that all code shall conform to ISO 9899 standard C, with no extensions permitted. This Rule is not supported as the library implementation requires IAR extensions like __interrupt. These intrinsic functions relate to device hardware functionality, and cannot practically be avoided. 10.1 Rule states that implicit conversion from Underlying long to unsigned long The library uses macros to combine symbol definitions to form a unique expanded symbol name and in this, the usage of unsigned qualifiers for numeric constants (e.g. 98u) causes name mangling. This is the only occurrence of this error in the library. 10.6 This Rule says that a 'U' suffix shall be applied to all constants of 'unsigned' type The library uses macros to combine symbol definitions to form a unique expanded symbol name and in this, the usage of unsigned qualifiers for numeric constants (e.g. 98u) causes name mangling. This is the only occurrence of this error in the library. 14.4 Rule states that go-to statement should not be The library uses conditional jump instructions to reduce the code footprint at a few locations and 183 used. this is localized to small snippets of code. Hence this rule is not supported. 19.10 Rule states that In the definition of a function-like macro, each instance of a parameter shall be enclosed in parenthesis There is one instance where the library breaks this rule where two macro definitions are combined to form a different symbol name. Usage of parenthesis cannot be used in this scenario. 19.12 Rule states that there shall be at most one occurrence of the # or ## preprocessor operator in a single macro definition There is one instance in the library where this rule is violated where the library concatenates two macro definitions to arrive at a different definition. 8 Revision History The table below lists the revision history for chapters in the user guide. QTouch Library User guide Revision History Date/Version Chapter Change notes May 2009 Ver2.0 All 2nd release of QTouch library users guide Sep 2009 Ver. 3.0 All Re-structured user guide with new and expanded sections Nov 2009 Ver. 3.1 6.3, 6.9, 6.10, 7, 10 • Updated API changes • Updated new libraries and device support information • Updated debug interface information supported by the QTouch libraries • Updated known issues table Dec 2009 Ver. 3.2 6.10.4, 7.1.2, 7.1.5, 7.1.6, 10, 7.2.4.2.2, 7.2.4.3.7, 7.2.4.3.2, 7.2.4.3.5, 7.2.4.3.7, • Added section about configuring unused pins in user application • Added more information to some sections to clear ambiguity • Updated Memory footprint information for IAR and GCC compiled QTouch libraries. • Updated known issues table • Added the device support, port combinations, memory requirements • QMatrix IAR and GCC libraries to support ATmega325P, ATmega645, and ATtiny167. • Modified port combinations for the 165P for QMatrix libraries. • Few Port combinations added in case of ATmega88 libraries. Feb 2010 Ver 4.0 All chapters changed • A separate library selection guide is provided external to the user guide. All sections included in the library selection guide have been removed from the user guide. • All sections have been updated to account for the improved configurability of the libraries. Apr 2010 Ver 4.1 • Added sections related to Positive Recalibration Delay, Position Hysteresis, and Position Resolution. 184 8207L-AT42-05/12 • Device support extended for QMatrix for the release has been added in section 5.7.2.4.1 and 5.7.2.3 • In case of QMatrix, 4 ( 4x1) channel has been added wherever needed and in case of ATxmega devices 56 (8x7) channel has been added according to the changes • QTouch Library for UC3L API Device Specific Libraries Section has been added. May 2010 Ver 4.2 • Qtouch acquisition libraries support will be available for ATSAM3U and ATSAM3S devices. • Qdebug protocol support will be extended for all example projects. • Analog comparator usage and burst length setting recommendation Note added for UC3L QMatrix method. • QMatrix device support added for AT90USB82 / 162 / 646 / 647 / 1286 July 2010 Ver 4.3 Section 5.8, Section 5.7.2.4 • Device support added for Tiny44/84/461/861 • Added the details on Pin configuration support for both QTouch and QMatrix libraries. • Added section related to the usage of the pin configurator tool on QTouch Studio.(section 5.8) • Added sections for Tiny20 and Tiny40 Devices. Jan 2011 Ver 4.3.1 Chapter 7, Section 5.6.11.2.1, Section 5.7.11.2.1 • Device support added for QTouch 2K devices ATtiny2313A/261A/24A/25A. • Added Chapter 7 on 2K Device libraries. • QTouch Support added for UC3C family devices. • QTouch Support added for ATtiny87 device • Tiny20 code memory requirement section updated. Aug 2011 Ver 4.4 Chapter 2 Section 5.6.10.3 Section 6.5 Section 5.5.3 • Added Feature Comparison Table • Section 5.6.10 changed and updated for Support for QMatrix AT32UC3C0512 Device • Section 6.5 changed and updated for ATtiny40 libraries • Section 5.5.3 added for Guard Channel April 2012 Ver 5.0 Section 6.5.5 Section 6.5.8 • Section 6.5.5 changed and updated for ATtiny40 libraries • Section 6.5.8 changed and updated for ATtiny40 libraries • Section 5.6.10.3.1 changed and updated for 8-bit Qmatrix libraries related to Shared YA/YB. • Sections 5.6.10.1, 5.6.10.2, 5.7.1.2, 5.7.1.3.1 updated for sam4s addition185 Disclaimer Headquarters International ATMEL Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 ATMEL Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Product Contact ATMEL Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 ATMEL Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Web Site http://www.atmel.com/ Technical Support AVR Libraries: touch@atmel.com SAM Libraries: at91support@atmel.com Sales Contact www.atmel.com/contacts Literature Request www.atmel.com/literature Disclaimer: The information in this document is provided in connection with ATMEL products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of ATMEL products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. ATMEL makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. ATMEL does not make any commitment to update the information contained herein. Unless specifically provided otherwise, ATMEL products are not suitable for, and shall not be used in, automotive applications. ATMEL’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2012 ATMEL Corporation. All rights reserved. ATMEL®, ATMEL logo and combinations thereof, AVR®, AVR Studio®, megaAVR®, tinyAVR® , QTouch®, QMatrix®, ®, XMEGA®,, and others are registered trademarks, others are trademarks of ATMEL Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 2586Q–AVR–08/2013 Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation • Non-volatile Program and Data Memories – 2/4/8K Bytes of In-System Programmable Program Memory Flash • Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles – 128/256/512 Bytes Internal SRAM – Programming Lock for Self-Programming Flash Program and EEPROM Data Security • Peripheral Features – 8-bit Timer/Counter with Prescaler and Two PWM Channels – 8-bit High Speed Timer/Counter with Separate Prescaler • 2 High Frequency PWM Outputs with Separate Output Compare Registers • Programmable Dead Time Generator – USI – Universal Serial Interface with Start Condition Detector – 10-bit ADC • 4 Single Ended Channels • 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x) • Temperature Measurement – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator • Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator • I/O and Packages – Six Programmable I/O Lines – 8-pin PDIP, 8-pin SOIC, 20-pad QFN/MLF, and 8-pin TSSOP (only ATtiny45/V) • Operating Voltage – 1.8 - 5.5V for ATtiny25V/45V/85V – 2.7 - 5.5V for ATtiny25/45/85 • Speed Grade – ATtiny25V/45V/85V: 0 – 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V – ATtiny25/45/85: 0 – 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V • Industrial Temperature Range • Low Power Consumption – Active Mode: • 1 MHz, 1.8V: 300 µA – Power-down Mode: • 0.1 µA at 1.8V Atmel 8-bit AVR Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny25/V / ATtiny45/V / ATtiny85/V Rev. 2586Q–AVR–08/2013ATtiny25/45/85 [DATASHEET] 2 2586Q–AVR–08/2013 1. Pin Configurations Figure 1-1. Pinout ATtiny25/45/85 1.1 Pin Descriptions 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB5:PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. 1 2 3 4 8 7 6 5 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 GND VCC PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2) PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1) PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0) PDIP/SOIC/TSSOP 1 2 3 4 5 QFN/MLF 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 DNC DNC GND DNC DNC DNC DNC DNC DNC DNC NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect NOTE: TSSOP only for ATtiny45/V (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3 DNC DNC (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 VCC PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2) DNC PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1) PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)ATtiny25/45/85 [DATASHEET] 3 2586Q–AVR–08/2013 Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in “Alternate Functions of Port B” on page 60. On ATtiny25, the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in ATtiny15 Compatibility Mode for supporting the backward compatibility with ATtiny15. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 21-4 on page 165. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin.ATtiny25/45/85 [DATASHEET] 4 2586Q–AVR–08/2013 2. Overview The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. PROGRAM COUNTER CALIBRATED INTERNAL OSCILLATOR WATCHDOG TIMER STACK POINTER PROGRAM FLASH SRAM MCU CONTROL REGISTER GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER TIMER/ COUNTER0 SERIAL UNIVERSAL INTERFACE TIMER/ COUNTER1 INSTRUCTION DECODER DATA DIR. REG.PORT B DATA REGISTER PORT B PROGRAMMING LOGIC TIMING AND CONTROL MCU STATUS REGISTER STATUS REGISTER ALU PORT B DRIVERS PB[0:5] VCC GND CONTROL LINES 8-BIT DATABUS Z ADC / ANALOG COMPARATOR INTERRUPT UNIT DATA EEPROM OSCILLATORS Y X RESETATtiny25/45/85 [DATASHEET] 5 2586Q–AVR–08/2013 The ATtiny25/45/85 provides the following features: 2/4/8K bytes of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.ATtiny25/45/85 [DATASHEET] 6 2586Q–AVR–08/2013 3. About 3.1 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically, this means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all AVR devices include an extended I/O map. 3.3 Capacitive Touch Sensing Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcontrollers. The QTouch Library includes support for QTouch® and QMatrix® acquisition methods. Touch sensing is easily added to any application by linking the QTouch Library and using the Application Programming Interface (API) of the library to define the touch channels and sensors. The application then calls the API to retrieve channel information and determine the state of the touch sensor. The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of implementation, refer to the QTouch Library User Guide – also available from the Atmel website. 3.4 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.ATtiny25/45/85 [DATASHEET] 7 2586Q–AVR–08/2013 4. AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.2 Architectural Overview Figure 4-1. Block Diagram of the AVR Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operFlash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registrers ALU Status and Control I/O Lines EEPROM Data Bus 8-bit Data SRAM Direct Addressing Indirect Addressing Interrupt Unit Watchdog Timer Analog Comparator I/O Module 2 I/O Module1 I/O Module nATtiny25/45/85 [DATASHEET] 8 2586Q–AVR–08/2013 ands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format, but there are also 32-bit instructions. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. 4.3 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bitfunctions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 4.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.ATtiny25/45/85 [DATASHEET] 9 2586Q–AVR–08/2013 4.4.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. Bit 7 6 5 4 3 2 1 0 0x3F I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 10 2586Q–AVR–08/2013 4.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 4-2. AVR CPU General Purpose Working Registers Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 4.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3. 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High ByteATtiny25/45/85 [DATASHEET] 11 2586Q–AVR–08/2013 Figure 4-3. The X-, Y-, and Z-registers In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 4.6.1 SPH and SPL — Stack Pointer Register 4.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. 15 XH XL 0 X-register 7 0 7 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 7 0 7 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z-register 7 0 7 0 R31 (0x1F) R30 (0x1E) Bit 15 14 13 12 11 10 9 8 0x3E SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 76543210 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMENDATtiny25/45/85 [DATASHEET] 12 2586Q–AVR–08/2013 Figure 4-4. The Parallel Instruction Fetches and Instruction Executions Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-5. Single Cycle ALU Operation 4.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 48. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. clk 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back T1 T2 T3 T4 clkCPUATtiny25/45/85 [DATASHEET] 13 2586Q–AVR–08/2013 The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. 4.8.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1< ; Address 0x000F ...ATtiny25/45/85 [DATASHEET] 50 2586Q–AVR–08/2013 the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 23. If the low level on the interrupt pin is removed before the device has woken up then program execution will not be diverted to the interrupt service routine but continue from the instruction following the SLEEP command. 9.2.2 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 9-1. Figure 9-1. Timing of pin change interrupts clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF PCINT(0) pin_sync pcint_syn pin_lat D Q LE pcint_setflag PCIF clk clk PCINT(0) in PCMSK(x) pcint_in_(0) 0 xATtiny25/45/85 [DATASHEET] 51 2586Q–AVR–08/2013 9.3 Register Description 9.3.1 MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control. • Bits 1:0 – ISC0[1:0]: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9-2. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. 9.3.2 GIMSK – General Interrupt Mask Register • Bits 7, 4:0 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. • Bit 5 – PCIE: Pin Change Interrupt Enable When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt is enabled. Any change on any enabled PCINT[5:0] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt Vector. PCINT[5:0] pins are enabled individually by the PCMSK0 Register. Bit 7 6 5 4 3 2 1 0 0x35 BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 MCUCR Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 9-2. Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request. Bit 7 6 5 4 3 2 1 0 0x3B – INT0 PCIE – – – – – GIMSK Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 52 2586Q–AVR–08/2013 9.3.3 GIFR – General Interrupt Flag Register • Bits 7, 4:0 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. • Bit 5 – PCIF: Pin Change Interrupt Flag When a logic change on any PCINT[5:0] pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. 9.3.4 PCMSK – Pin Change Mask Register • Bits 7:6 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bits 5:0 – PCINT[5:0]: Pin Change Enable Mask 5:0 Each PCINT[5:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[5:0] is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[5:0] is cleared, pin change interrupt on the corresponding I/O pin is disabled. Bit 7 6 5 4 3 2 1 0 0x3A – INTF0 PCIF – – – – – GIFR Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x15 – – PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 53 2586Q–AVR–08/2013 10. I/O Ports 10.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 10-1. Refer to “Electrical Characteristics” on page 161 for a complete list of parameters. Figure 10-1. I/O Pin Equivalent Schematic All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description” on page 64. Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set. Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 53. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in “Alternate Port Functions” on page 57. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 10.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn. Logic Rpu See Figure "General Digital I/O" for Details PxnATtiny25/45/85 [DATASHEET] 54 2586Q–AVR–08/2013 Figure 10-2. General Digital I/O(1) Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. 10.2.1 Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register Description” on page 64, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 10.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 10.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the clk RPx RRx RDx WDx PUD SYNCHRONIZER WDx: WRITE DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN PUD: PULLUP DISABLE clkI/O: I/O CLOCK RDx: READ DDRx D L Q Q RESET RESET Q D Q Q Q D CLR PORTxn Q Q D CLR DDxn PINxn DATA BUS SLEEP SLEEP: SLEEP CONTROL Pxn I/O WPx 0 1 WRx WPx: WRITE PINx REGISTERATtiny25/45/85 [DATASHEET] 55 2586Q–AVR–08/2013 difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tristate ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b10) as an intermediate step. Table 10-1 summarizes the control signals for the pin value. 10.2.4 Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 10-2, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 10-3 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively. Figure 10-3. Synchronization when Reading an Externally Applied Pin value Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Table 10-1. Port Pin Configurations DDxn PORTxn PUD (in MCUCR) I/O Pull-up Comment 0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low. 0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Output Low (Sink) 1 1 X Output No Output High (Source) XXX in r17, PINx 0x00 0xFF INSTRUCTIONS SYNC LATCH PINxn r17 XXX SYSTEM CLK tpd, max tpd, minATtiny25/45/85 [DATASHEET] 56 2586Q–AVR–08/2013 Figure 10-4. Synchronization when Reading a Software Assigned Pin Value The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1< CS0[2:0] > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. Table 11-1. Definitions Constant Description BOTTOM The counter reaches BOTTOM when it becomes 0x00 MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255) TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment depends on the mode of operationATtiny25/45/85 [DATASHEET] 67 2586Q–AVR–08/2013 11.3.3 External Clock Source An external clock source applied to the T0 pin can be used as timer/counter clock (clkT0). The T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 11-2 shows a functional equivalent block diagram of the T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT0 pulse for each positive (CS0[2:0] = 7) or negative (CS0[2:0] = 6) edge it detects. Figure 11-2. T0 Pin Sampling The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (following the Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Tn_sync (To Clock Select Logic) Synchronization Edge Detector D Q D Q LE Tn D Q clkI/OATtiny25/45/85 [DATASHEET] 68 2586Q–AVR–08/2013 Figure 11-3. Timer/Counter0 Prescaler The synchronization logic on the input pins (T0) in Figure 11-3 is shown in Figure 11-2 on page 67. 11.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 11-4 shows a block diagram of the counter and its surroundings. Figure 11-4. Counter Unit Block Diagram Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS0[2:0]). When no clock source is selected (CS0[2:0] = 0) the timer is stopped. However, the TCNT0 value can PSR10 Clear clkT0 T0 clkI/O Synchronization DATA BUS TCNTn Control Logic count TOVn (Int.Req.) Clock Select top Tn Edge Detector ( From Prescaler ) clkTn bottom direction clearATtiny25/45/85 [DATASHEET] 69 2586Q–AVR–08/2013 be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC0A. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 71. The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM0[1:0] bits. TOV0 can be used for generating a CPU interrupt. 11.5 Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM0[2:0] bits and Compare Output mode (COM0x[1:0]) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See “Modes of Operation” on page 71.). Figure 11-5 shows a block diagram of the Output Compare unit. Figure 11-5. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. OCFnx (Int.Req.) = (8-bit Comparator ) OCRnx OCnx DATA BUS TCNTn WGMn[1:0] Waveform Generator top FOCn COMnX[1:0] bottomATtiny25/45/85 [DATASHEET] 70 2586Q–AVR–08/2013 The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly. 11.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare Match had occurred (the COM0x[1:0] bits settings define whether the OC0x pin is set, cleared or toggled). 11.5.2 Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 11.5.3 Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes. Be aware that the COM0x[1:0] bits are not double buffered together with the compare value. Changing the COM0x[1:0] bits will take effect immediately. 11.6 Compare Match Output Unit The Compare Output mode (COM0x[1:0]) bits have two functions. The Waveform Generator uses the COM0x[1:0] bits for defining the Output Compare (OC0x) state at the next Compare Match. Also, the COM0x[1:0] bits control the OC0x pin output source. Figure 11-6 shows a simplified schematic of the logic affected by the COM0x[1:0] bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM0x[1:0] bits are shown. When referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur, the OC0x Register is reset to “0”.ATtiny25/45/85 [DATASHEET] 71 2586Q–AVR–08/2013 Figure 11-6. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x[1:0] bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x[1:0] bit settings are reserved for certain modes of operation. See “Register Description” on page 77. 11.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x[1:0] bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x[1:0] = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 11-2 on page 78. For fast PWM mode, refer to Table 11-3 on page 78, and for phase correct PWM refer to Table 11-4 on page 78. A change of the COM0x[1:0] bits state will have effect at the first Compare Match after the bits are written. For nonPWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits. 11.7 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM0[2:0]) and Compare Output mode (COM0x[1:0]) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0x[1:0] bits control whether the PWM output generated should be inverted or not (inverted or noninverted PWM). For non-PWM modes the COM0x[1:0] bits control whether the output should be set, cleared, or toggled at a Compare Match (See “Compare Match Output Unit” on page 70.). PORT DDR D Q D Q OCn OCnx Pin D Q Waveform Generator COMnx1 COMnx0 0 1 DATA BU S FOCn clkI/OATtiny25/45/85 [DATASHEET] 72 2586Q–AVR–08/2013 For detailed timing information refer to Figure 11-10, Figure 11-11, Figure 11-12 and Figure 11-13 in “Timer/Counter Timing Diagrams” on page 76. 11.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM0[2:0] = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8- bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare Unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 11.7.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM0[2:0] = 2), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 11-7. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 11-7. CTC Mode, Timing Diagram An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM0A[1:0] = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation: TCNTn OCn (Toggle) OCnx Interrupt Flag Set Period 1 2 3 4 (COMnx[1:0] = 1) f OCnx f clk_I/O 2 N 1 OCRnx + = --------------------------------------------------ATtiny25/45/85 [DATASHEET] 73 2586Q–AVR–08/2013 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 11.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM0[2:0] = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM0[2:0] = 3, and OCR0A when WGM0[2:0] = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 11-8. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 11-8. Fast PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x[1:0] bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x[1:0] to three: Setting the COM0A[1:0] bits to one allowes the AC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 11-3 on page 78). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveTCNTn OCRnx Update and TOVn Interrupt Flag Set Period 1 2 3 OCn OCn (COMnx[1:0] = 2) (COMnx[1:0] = 3) OCRnx Interrupt Flag Set 4 5 6 7ATtiny25/45/85 [DATASHEET] 74 2586Q–AVR–08/2013 form is generated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A[1:0] bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each Compare Match (COM0x[1:0] = 1). The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 11.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM0[2:0] = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM0[2:0] = 1, and OCR0A when WGM0[2:0] = 5. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 11-9. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. f OCnxPWM f clk_I/O N 256 = ------------------ATtiny25/45/85 [DATASHEET] 75 2586Q–AVR–08/2013 Figure 11-9. Phase Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x[1:0] bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x[1:0] to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 11-4 on page 78). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 11-9 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guaratee symmetry around BOTTOM. There are two cases that give a transition without Compare Match, as follows: • OCR0A changes its value from MAX, like in Figure 11-9. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. TOVn Interrupt Flag Set OCnx Interrupt Flag Set 1 2 3 TCNTn Period OCn OCn (COMnx[1:0] = 2) (COMnx[1:0] = 3) OCRnx Update f OCnxPCPWM f clk_I/O N 510 = ------------------ATtiny25/45/85 [DATASHEET] 76 2586Q–AVR–08/2013 • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 11.8 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 11-10 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 11-10. Timer/Counter Timing Diagram, no Prescaling Figure 11-11 shows the same timing data, but with the prescaler enabled. Figure 11-11. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) Figure 11-12 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 11-12. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) clkTn (clkI/O/1) TOVn clkI/O TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8) OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clkI/O clkTn (clkI/O/8)ATtiny25/45/85 [DATASHEET] 77 2586Q–AVR–08/2013 Figure 11-13 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP. Figure 11-13. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) 11.9 Register Description 11.9.1 GTCCR – General Timer/Counter Control Register • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization Mode. In this mode, the value written to PSR0 is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the timer/counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR0 bit is cleared by hardware, and the timer/counter start counting. • Bit 0 – PSR0: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. 11.9.2 TCCR0A – Timer/Counter Control Register A • Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode • Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode The COM0A[1:0] and COM0B[1:0] bits control the behaviour of Output Compare pins OC0A and OC0B, respectively. If any of the COM0A[1:0] bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. Similarly, if any of the COM0B[1:0] bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A and OC0B pins must be set in order to enable the output driver. OCFnx OCRnx TCNTn (CTC) TOP TOP - 1 TOP BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8) Bit 7 6 5 4 3 2 1 0 0x2C TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 GTCCR Read/Write R/W R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x2A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 78 2586Q–AVR–08/2013 When OC0A/OC0B is connected to the I/O pin, the function of the COM0A[1:0]/COM0B[1:0] bits depend on the WGM0[2:0] bit setting. Table 11-2 shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to a normal or CTC mode (non-PWM). Table 11-3 shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to fast PWM mode. Note: 1. A special case occurs when OCR0A or OCR0B equals TOP and COM0A1/COM0B1 is set. In this case, the compare match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 73 for more details. Table 11-4 shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode. Note: 1. A special case occurs when OCR0A or OCR0B equals TOP and COM0A1/COM0B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 74 for more details. • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. Table 11-2. Compare Output Mode, non-PWM Mode COM0A1 COM0B1 COM0A0 COM0B0 Description 0 0 Normal port operation, OC0A/OC0B disconnected. 0 1 Toggle OC0A/OC0B on Compare Match 1 0 Clear OC0A/OC0B on Compare Match 1 1 Set OC0A/OC0B on Compare Match Table 11-3. Compare Output Mode, Fast PWM Mode(1) COM0A1 COM0B1 COM0A0 COM0B0 Description 0 0 Normal port operation, OC0A/OC0B disconnected. 0 1 Reserved 1 0 Clear OC0A/OC0B on Compare Match, set OC0A/OC0B at BOTTOM (non-inverting mode) 1 1 Set OC0A/OC0B on Compare Match, clear OC0A/OC0B at BOTTOM (inverting mode) Table 11-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0B1 COM0A0 COM0B0 Description 0 0 Normal port operation, OC0A/OC0B disconnected. 0 1 Reserved 1 0 Clear OC0A/OC0B on Compare Match when up-counting. Set OC0A/OC0B on Compare Match when down-counting. 1 1 Set OC0A/OC0B on Compare Match when up-counting. Clear OC0A/OC0B on Compare Match when down-counting.ATtiny25/45/85 [DATASHEET] 79 2586Q–AVR–08/2013 • Bits 1:0 – WGM0[1:0]: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 11-5. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 71). Notes: 1. MAX = 0xFF 2. BOTTOM = 0x00 11.9.3 TCCR0B – Timer/Counter Control Register B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is changed according to its COM0A[1:0] bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A[1:0] bits that determines the effect of the forced compare. A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP. The FOC0A bit is always read as zero. • Bit 6 – FOC0B: Force Output Compare B The FOC0B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is changed according to its COM0B[1:0] bits setting. Note that the FOC0B bit is implemented as a strobe. Therefore it is the value present in the COM0B[1:0] bits that determines the effect of the forced compare. A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. Table 11-5. Waveform Generation Mode Bit Description Mode WGM 02 WGM 01 WGM 00 Timer/Counter Mode of Operation TOP Update of OCRx at TOV Flag Set on 0 0 0 0 Normal 0xFF Immediate MAX(1) 1 0 0 1 PWM, Phase Correct 0xFF TOP BOTTOM(2) 2 0 1 0 CTC OCRA Immediate MAX(1) 3 0 1 1 Fast PWM 0xFF BOTTOM(2) MAX(1) 4 1 0 0 Reserved – – – 5 1 0 1 PWM, Phase Correct OCRA TOP BOTTOM(2) 6 1 1 0 Reserved – – – 7 1 1 1 Fast PWM OCRA BOTTOM(2) TOP Bit 7 6 5 4 3 2 1 0 0x33 FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 80 2586Q–AVR–08/2013 The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the “TCCR0A – Timer/Counter Control Register A” on page 77. • Bits 2:0 – CS0[2:0]: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 11.9.4 TCNT0 – Timer/Counter Register The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers. 11.9.5 OCR0A – Output Compare Register A The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin. Table 11-6. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge. Bit 7 6 5 4 3 2 1 0 0x32 TCNT0[7:0] TCNT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x29 OCR0A[7:0] OCR0A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 81 2586Q–AVR–08/2013 11.9.6 OCR0B – Output Compare Register B The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0B pin. 11.9.7 TIMSK – Timer/Counter Interrupt Mask Register • Bits 7, 0 – Res: Reserved Bits These bits are reserved bits and will always read as zero. • Bit 4 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0. • Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0. • Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0. 11.9.8 TIFR – Timer/Counter Interrupt Flag Register • Bits 7, 0 – Res: Reserved Bits These bits are reserved bits and will always read as zero. • Bit 4 – OCF0A: Output Compare Flag 0 A The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. Bit 7 6 5 4 3 2 1 0 0x28 OCR0B[7:0] OCR0B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x39 – OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 – TIMSK Read/Write R R/W R/W R/W R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x38 – OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 – TIFR Read/Write R R/W R/W R/W R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 82 2586Q–AVR–08/2013 • Bit 3 – OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed. • Bit 1 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM0[2:0] bit setting. Refer to Table 11-5, “Waveform Generation Mode Bit Description” on page 79.ATtiny25/45/85 [DATASHEET] 83 2586Q–AVR–08/2013 12. 8-bit Timer/Counter1 The Timer/Counter1 is a general purpose 8-bit Timer/Counter module that has a separate prescaling selection from the separate prescaler. 12.1 Timer/Counter1 Prescaler Figure 12-1 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchronous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base. The PCKE bit from the PLLCSR register enables the asynchronous mode when it is set (‘1’). Figure 12-1. Timer/Counter1 Prescaler In the asynchronous clocking mode the clock selections are from PCK to PCK/16384 and stop, and in the synchronous clocking mode the clock selections are from CK to CK/16384 and stop. The clock options are described in Table 12-5 on page 89 and the Timer/Counter1 Control Register, TCCR1. Setting the PSR1 bit in GTCCR register resets the prescaler. The PCKE bit in the PLLCSR register enables the asynchronous mode. The frequency of the fast peripheral clock is 64 MHz (or 32 MHz in Low Speed Mode). 12.2 Counter and Compare Units The Timer/Counter1 general operation is described in the asynchronous mode and the operation in the synchronous mode is mentioned only if there are differences between these two modes. Figure 12-2 shows Timer/Counter 1 synchronization register block diagram and synchronization delays in between registers. Note that all clock gating details are not shown in the figure. The Timer/Counter1 register values go through the internal synchronization registers, which cause the input synchronization delay, before affecting the counter operation. The registers TCCR1, GTCCR, OCR1A, OCR1B, and OCR1C can be read back right after writing the register. The read back values are delayed for the Timer/Counter1 (TCNT1) register and flags (OCF1A, OCF1B, and TOV1), because of the input and output synchronization. The Timer/Counter1 features a high resolution and a high accuracy usage with the lower prescaling opportunities. It can also support two accurate, high speed, 8-bit Pulse Width Modulators using clock speeds up to 64 MHz (or 32 MHz in Low Speed Mode). In this mode, Timer/Counter1 and the output compare registers serve as dual standalone PWMs with non-overlapping non-inverted and inverted outputs. Refer to page 86 for a detailed description on this function. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. TIMER/COUNTER1 COUNT ENABLE PSR1 CS10 CS11 CS12 PCK 64/32 MHz 0 CS13 14-BIT T/C PRESCALER T1CK T1CK/2 T1CK/4 T1CK/8 T1CK/16 T1CK/32 T1CK/64 T1CK/128 T1CK/256 T1CK/512 T1CK/1024 T1CK/2048 T1CK/4096 T1CK/8192 T1CK/16384 CK PCKE T1CKATtiny25/45/85 [DATASHEET] 84 2586Q–AVR–08/2013 Figure 12-2. Timer/Counter 1 Synchronization Register Block Diagram. Timer/Counter1 and the prescaler allow running the CPU from any clock source while the prescaler is operating on the fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock in the asynchronous mode. Note that the system clock frequency must be lower than one third of the PCK frequency. The synchronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of the PCK when the system clock is high. If the frequency of the system clock is too high, it is a risk that data or control values are lost. The following Figure 12-3 shows the block diagram for Timer/Counter1. 8-BIT DATABUS OCR1A OCR1A_SI OCR1B OCR1B_SI TCNT_SO OCR1C OCR1C_SI TCCR1 TCCR1_SI GTCCR GTCCR_SI TCNT1 TCNT1_SI OCF1A OCF1A_SI OCF1B OCF1B_SI TOV1 TOV1_SI TOV1_SO OCF1B_SO OCF1A_SO TCNT1 S A S A PCKE CK PCK IO-registers Input synchronization registers Timer/Counter1 Output synchronization registers SYNC MODE ASYNC MODE 1 CK Delay 1 PCK Delay No Delay ~1 CK Delay TCNT1 OCF1A OCF1B TOV1 1/2 CK Delay 1 CK Delay 1/2 CK Delay 1..2 PCK DelayATtiny25/45/85 [DATASHEET] 85 2586Q–AVR–08/2013 Figure 12-3. Timer/Counter1 Block Diagram Three status flags (overflow and compare matches) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1 and GTCCR. The interrupt enable/disable settings are found in the Timer/Counter Interrupt Mask Register - TIMSK. The Timer/Counter1 contains three Output Compare Registers, OCR1A, OCR1B, and OCR1C as the data source to be compared with the Timer/Counter1 contents. In normal mode the Output Compare functions are operational with all three output compare registers. OCR1A determines action on the OC1A pin (PB1), and it can generate Timer1 OC1A interrupt in normal mode and in PWM mode. Likewise, OCR1B determines action on the OC1B pin (PB4) and it can generate Timer1 OC1B interrupt in normal mode and in PWM mode. OCR1C holds the Timer/Counter maximum value, i.e. the clear on compare match value. In the normal mode an overflow interrupt (TOV1) is generated when Timer/Counter1 counts from $FF to $00, while in the PWM mode the overflow interrupt is generated when Timer/Counter1 counts either from $FF to $00 or from OCR1C to $00. The inverted PWM outputs OC1A and OC1B are not connected in normal mode. In PWM mode, OCR1A and OCR1B provide the data values against which the Timer Counter value is compared. Upon compare match the PWM outputs (OC1A, OC1A, OC1B, OC1B) are generated. In PWM mode, the Timer Counter counts up to the value specified in the output compare register OCR1C and starts again from $00. This feature allows limiting the counter “full” value to a specified value, lower than $FF. Together with the many prescaler options, flexible PWM frequency selection is provided. Table 12-3 on page 88 lists clock selection and OCR1C values to obtain PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution. 8-BIT DATABUS TIMER INT. FLAG REGISTER (TIFR) TIMER/COUNTER1 8-BIT COMPARATOR T/C1 OUTPUT COMPARE REGISTER TIMER INT. MASK REGISTER (TIMSK) TIMER/COUNTER1 (TCNT1) T/C CLEAR T/C1 CONTROL LOGIC TOV1 OCF1B OCIE1A OCIE1B TOIE1 TOIE0 OCF1A OCF1B TOV1 OCF1A CK PCK T/C1 OVERFLOW IRQ T/C1 COMPARE MATCH B IRQ OC1A (PB1) T/C1 COMPARE MATCH A IRQ T/C CONTROL REGISTER 1 (TCCR1) PWM1A COM1B1 PWM1B COM1B0 FOC1B FOC1A (OCR1A) (OCR1B) (OCR1C) 8-BIT COMPARATOR T/C1 OUTPUT COMPARE REGISTER TOV0 COM1A1 COM1A0 8-BIT COMPARATOR T/C1 OUTPUT COMPARE REGISTER GLOBAL T/C CONTROL REGISTER (GTCCR) CS12 CS11 CS10 PSR1 CTC1 CS13 OC1A (PB0) OC1B (PB4) OC1B (PB3) DEAD TIME GENERATOR DEAD TIME GENERATORATtiny25/45/85 [DATASHEET] 86 2586Q–AVR–08/2013 12.2.1 Timer/Counter1 Initialization for Asynchronous Mode To set Timer/Counter1 in asynchronous mode first enable PLL and then wait 100 µs for PLL to stabilize. Next, poll the PLOCK bit until it is set and then set the PCKE bit. 12.2.2 Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register C - OCR1C form a dual 8-bit, free-running and glitch-free PWM generator with outputs on the PB1(OC1A) and PB4(OC1B) pins and inverted outputs on pins PB0(OC1A) and PB3(OC1B). As default non-overlapping times for complementary output pairs are zero, but they can be inserted using a Dead Time Generator (see description on page 100). Figure 12-4. The PWM Output Pair When the counter value match the contents of OCR1A or OCR1B, the OC1A and OC1B outputs are set or cleared according to the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register A - TCCR1, as shown in Table 12-1. Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output compare register OCR1C, and starting from $00 up again. A compare match with OC1C will set an overflow interrupt flag (TOV1) after a synchronization delay following the compare event. Note that in PWM mode, writing to the Output Compare Registers OCR1A or OCR1B, the data value is first transferred to a temporary location. The value is latched into OCR1A or OCR1B when the Timer/Counter reaches OCR1C. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A or OCR1B. See Figure 12-5 for an example. Table 12-1. Compare Mode Select in PWM Mode COM1x1 COM1x0 Effect on Output Compare Pins 0 0 OC1x not connected. OC1x not connected. 0 1 OC1x cleared on compare match. Set whenTCNT1 = $00. OC1x set on compare match. Cleared when TCNT1 = $00. 1 0 OC1x cleared on compare match. Set when TCNT1 = $00. OC1x not connected. 1 1 OC1x Set on compare match. Cleared when TCNT1= $00. OC1x not connected. PWM1x PWM1x t non-overlap=0 t non-overlap=0 x = A or BATtiny25/45/85 [DATASHEET] 87 2586Q–AVR–08/2013 Figure 12-5. Effects of Unsynchronized OCR Latching During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A or OCR1B. When OCR1A or OCR1B contain $00 or the top value, as specified in OCR1C register, the output PB1(OC1A) or PB4(OC1B) is held low or high according to the settings of COM1A1/COM1A0. This is shown in Table 12-2. In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C value and the TCNT1 is reset to $00. The Timer Overflow Interrupt1 is executed when TOV1 is set provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to the Timer Output Compare flags and interrupts. The frequency of the PWM will be Timer Clock 1 Frequency divided by (OCR1C value + 1). See the following equation: Resolution shows how many bits are required to express the value in the OCR1C register and can be calculated using the following equation: Table 12-2. PWM Outputs OCR1x = $00 or OCR1C, x = A or B COM1x1 COM1x0 OCR1x Output OC1x Output OC1x 0 1 $00 L H 0 1 OCR1C H L 1 0 $00 L Not connected. 1 0 OCR1C H Not connected. 1 1 $00 H Not connected. 1 1 OCR1C L Not connected. PWM Output OC1x PWM Output OC1x Unsynchronized OC1x Latch Synchronized OC1x Latch Counter Value Compare Value Counter Value Compare Value Compare Value changes Glitch Compare Value changes f PWM f TCK1 OCR1C + 1 = ------------------------------------ R = log2 OCR1C 1 ( ) +ATtiny25/45/85 [DATASHEET] 88 2586Q–AVR–08/2013 Table 12-3. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode PWM Frequency Clock Selection CS1[3:0] OCR1C RESOLUTION 20 kHz PCK/16 0101 199 7.6 30 kHz PCK/16 0101 132 7.1 40 kHz PCK/8 0100 199 7.6 50 kHz PCK/8 0100 159 7.3 60 kHz PCK/8 0100 132 7.1 70 kHz PCK/4 0011 228 7.8 80 kHz PCK/4 0011 199 7.6 90 kHz PCK/4 0011 177 7.5 100 kHz PCK/4 0011 159 7.3 110 kHz PCK/4 0011 144 7.2 120 kHz PCK/4 0011 132 7.1 130 kHz PCK/2 0010 245 7.9 140 kHz PCK/2 0010 228 7.8 150 kHz PCK/2 0010 212 7.7 160 kHz PCK/2 0010 199 7.6 170 kHz PCK/2 0010 187 7.6 180 kHz PCK/2 0010 177 7.5 190 kHz PCK/2 0010 167 7.4 200 kHz PCK/2 0010 159 7.3 250 kHz PCK 0001 255 8.0 300 kHz PCK 0001 212 7.7 350 kHz PCK 0001 182 7.5 400 kHz PCK 0001 159 7.3 450 kHz PCK 0001 141 7.1 500 kHz PCK 0001 127 7.0ATtiny25/45/85 [DATASHEET] 89 2586Q–AVR–08/2013 12.3 Register Description 12.3.1 TCCR1 – Timer/Counter1 Control Register • Bit 7 – CTC1 : Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. • Bit 6 – PWM1A: Pulse Width Modulator A Enable When set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. • Bits 5:4 – COM1A[1:0]: Comparator A Output Mode, Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer/Counter1. Since the output pin action is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. In Normal mode, the COM1A1 and COM1A0 control bits determine the output pin actions that affect pin PB1 (OC1A) as described in Table 12-4. Note that OC1A is not connected in normal mode. In PWM mode, these bits have different functions. Refer to Table 12-1 on page 86 for a detailed description. • Bits 3:0 - CS1[3:0]: Clock Select Bits 3, 2, 1, and 0 The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. Bit 7 6 5 4 3 2 1 0 0x30 CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 TCCR1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Table 12-4. Comparator A Mode Select in Normal Mode COM1A1 COM1A0 Description 0 0 Timer/Counter Comparator A disconnected from output pin OC1A. 0 1 Toggle the OC1A output line. 1 0 Clear the OC1A output line. 1 1 Set the OC1A output line Table 12-5. Timer/Counter1 Prescale Select CS13 CS12 CS11 CS10 Asynchronous Clocking Mode Synchronous Clocking Mode 0 0 0 0 T/C1 stopped T/C1 stopped 0 0 0 1 PCK CK 0 0 1 0 PCK/2 CK/2 0 0 1 1 PCK/4 CK/4 0 1 0 0 PCK/8 CK/8 0 1 0 1 PCK/16 CK/16 0 1 1 0 PCK/32 CK/32ATtiny25/45/85 [DATASHEET] 90 2586Q–AVR–08/2013 The Stop condition provides a Timer Enable/Disable function. 12.3.2 GTCCR – General Timer/Counter1 Control Register • Bit 6 – PWM1B: Pulse Width Modulator B Enable When set (one) this bit enables PWM mode based on comparator OCR1B in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. • Bits 5:4 – COM1B[1:0]: Comparator B Output Mode, Bits 1 and 0 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match with compare register B in Timer/Counter1. Since the output pin action is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. In Normal mode, the COM1B1 and COM1B0 control bits determine the output pin actions that affect pin PB4 (OC1B) as described in Table 12-6. Note that OC1B is not connected in normal mode. In PWM mode, these bits have different functions. Refer to Table 12-1 on page 86 for a detailed description. • Bit 3 – FOC1B: Force Output Compare Match 1B Writing a logical one to this bit forces a change in the compare match output pin PB4 (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1B1 and COM1B0 takes place as if a compare match had 0 1 1 1 PCK/64 CK/64 1 0 0 0 PCK/128 CK/128 1 0 0 1 PCK/256 CK/256 1 0 1 0 PCK/512 CK/512 1 0 1 1 PCK/1024 CK/1024 1 1 0 0 PCK/2048 CK/2048 1 1 0 1 PCK/4096 CK/4096 1 1 1 0 PCK/8192 CK/8192 1 1 1 1 PCK/16384 CK/16384 Table 12-5. Timer/Counter1 Prescale Select (Continued) CS13 CS12 CS11 CS10 Asynchronous Clocking Mode Synchronous Clocking Mode Bit 7 6 5 4 3 2 1 0 0x2C TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 GTCCR Read/Write R/W R/W R/W R/W W W R/W R/W Initial value 0 0 0 0 0 0 0 0 Table 12-6. Comparator B Mode Select in Normal Mode COM1B1 COM1B0 Description 0 0 Timer/Counter Comparator B disconnected from output pin OC1B. 0 1 Toggle the OC1B output line. 1 0 Clear the OC1B output line. 1 1 Set the OC1B output lineATtiny25/45/85 [DATASHEET] 91 2586Q–AVR–08/2013 occurred, but no interrupt is generated. The FOC1B bit always reads as zero. FOC1B is not in use if PWM1B bit is set. • Bit 2 – FOC1A: Force Output Compare Match 1A Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written in the same cycle as FOC1A, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit is set. • Bit 1 – PSR1 : Prescaler Reset Timer/Counter1 When this bit is set (one), the Timer/Counter prescaler (TCNT1 is unaffected) will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read as zero. 12.3.3 TCNT1 – Timer/Counter1 This 8-bit register contains the value of Timer/Counter1. Timer/Counter1 is realized as an up counter with read and write access. Due to synchronization of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one and half CPU clock cycles in synchronous mode and at most one CPU clock cycles for asynchronous mode. 12.3.4 OCR1A –Timer/Counter1 Output Compare RegisterA The output compare register A is an 8-bit read/write register. The Timer/Counter Output Compare Register A contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and OCR1A to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1A after a synchronization delay following the compare event. 12.3.5 OCR1B – Timer/Counter1 Output Compare RegisterB The output compare register B is an 8-bit read/write register. The Timer/Counter Output Compare Register B contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts Bit 7 6 5 4 3 2 1 0 0x2F MSB LSB TCNT1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x2E MSB LSB OCR1A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x2B MSB LSB OCR1B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 92 2586Q–AVR–08/2013 to the OCR1B value. A software write that sets TCNT1 and OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1B after a synchronization delay following the compare event. 12.3.6 OCR1C – Timer/Counter1 Output Compare RegisterC The output compare register C is an 8-bit read/write register. The Timer/Counter Output Compare Register C contains data to be continuously compared with Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C value. A software write that sets TCNT1 and OCR1C to the same value does not generate a compare match. If the CTC1 bit in TCCR1 is set, a compare match will clear TCNT1. This register has the same function in normal mode and PWM mode. 12.3.7 TIMSK – Timer/Counter Interrupt Mask Register • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. • Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register. • Bit 5 – OCIE1B: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchB, interrupt is enabled. The corresponding interrupt at vector $009 is executed if a compare matchB occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register. • Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. Bit 7 6 5 4 3 2 1 0 0x2D MSB LSB OCR1C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 0x39 – OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 – TIMSK Read/Write R R/W R/W R/W R/W R/W R/W R Initial value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 93 2586Q–AVR–08/2013 12.3.8 TIFR – Timer/Counter Interrupt Flag Register • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. • Bit 6 – OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 A compare match interrupt is executed. • Bit 5 – OCF1B: Output Compare Flag 1B The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1B - Output Compare Register 1A. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B are set (one), the Timer/Counter1 B compare match interrupt is executed. • Bit 2 – TOV1: Timer/Counter1 Overflow Flag In normal mode (PWM1A=0 and PWM1B=0) the bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. The bit TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared, after synchronization clock cycle, by writing a logical one to the flag. In PWM mode (either PWM1A=1 or PWM1B=1) the bit TOV1 is set (one) when compare match occurs between Timer/Counter1 and data value in OCR1C - Output Compare Register 1C. When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. Bit 7 6 5 4 3 2 1 0 0x38 – OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 – TIFR Read/Write R R/W R/W R/W R/W R/W R/W R Initial value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 94 2586Q–AVR–08/2013 12.3.9 PLLCSR – PLL Control and Status Register • Bit 7 – LSM: Low Speed Mode The high speed mode is enabled as default and the fast peripheral clock is 64 MHz, but the low speed mode can be set by writing the LSM bit to one. Then the fast peripheral clock is scaled down to 32 MHz. The low speed mode must be set, if the supply voltage is below 2.7 volts, because the Timer/Counter1 is not running fast enough on low voltage levels. It is highly recommended that Timer/Counter1 is stopped whenever the LSM bit is changed. Note, that LSM can not be set if PLLCLK is used as system clock. • Bit 6:3 – Res : Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and always read as zero. • Bit 2 – PCKE: PCK Enable The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock mode is enabled and fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock is used as Timer/Counter1 clock source. If this bit is cleared, the synchronous clock mode is enabled, and system clock CK is used as Timer/Counter1 clock source. This bit can be set only if PLLE bit is set. It is safe to set this bit only when the PLL is locked i.e the PLOCK bit is 1. The bit PCKE can only be set, if the PLL has been enabled earlier. • Bit 1 – PLLE: PLL Enable When the PLLE is set, the PLL is started and if needed internal RC-oscillator is started as a PLL reference clock. If PLL is selected as a system clock source the value for this bit is always 1. • Bit 0 – PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock. The PLOCK bit should be ignored during initial PLL lock-in sequence when PLL frequency overshoots and undershoots, before reaching steady state. The steady state is obtained within 100 µs. After PLL lock-in it is recommended to check the PLOCK bit before enabling PCK for Timer/Counter1. Bit 7 6 5 4 3 2 1 0 0x27 LSM - - - - PCKE PLLE PLOCK PLLCSR Read/Write R/W R R R R R/W R/W R Initial value 0 0 0 0 0 0 0/1 0ATtiny25/45/85 [DATASHEET] 95 2586Q–AVR–08/2013 13. 8-bit Timer/Counter1 in ATtiny15 Mode The ATtiny15 compatibility mode is selected by writing the code “0011” to the CKSEL fuses (if any other code is written, the Timer/Counter1 is working in normal mode). When selected the ATtiny15 compatibility mode provides an ATtiny15 backward compatible prescaler and Timer/Counter. Furthermore, the clocking system has same clock frequencies as in ATtiny15. 13.1 Timer/Counter1 Prescaler Figure 13-1 shows an ATtiny15 compatible prescaler. It has two prescaler units, a 10-bit prescaler for the system clock (CK) and a 3-bit prescaler for the fast peripheral clock (PCK). The clocking system of the Timer/Counter1 is always synchronous in the ATtiny15 compatibility mode, because the same RC Oscillator is used as a PLL clock source (generates the input clock for the prescaler) and the AVR core. Figure 13-1. Timer/Counter1 Prescaler The same clock selections as in ATtiny15 can be chosen for Timer/Counter1 from the output multiplexer, because the frequency of the fast peripheral clock is 25.6 MHz and the prescaler is similar in the ATtiny15 compatibility mode. The clock selections are PCK, PCK/2, PCK/4, PCK/8, CK, CK/2, CK/4, CK/8, CK/16, CK/32, CK/64, CK/128, CK/256, CK/512, CK/1024 and stop. 13.2 Counter and Compare Units Figure 13-2 shows Timer/Counter 1 synchronization register block diagram and synchronization delays in between registers. Note that all clock gating details are not shown in the figure. The Timer/Counter1 register values go through the internal synchronization registers, which cause the input synchronization delay, before affecting the counter operation. The registers TCCR1, GTCCR, OCR1A and OCR1C can be read back right after writing the register. The read back values are delayed for the Timer/Counter1 (TCNT1) register and flags (OCF1A and TOV1), because of the input and output synchronization. The Timer/Counter1 features a high resolution and a high accuracy usage with the lower prescaling opportunities. It can also support an accurate, high speed, 8-bit Pulse Width Modulator (PWM) using clock speeds up to 25.6 MHz. In this mode, Timer/Counter1 and the Output Compare Registers serve as a stand-alone PWM. Refer to “Timer/Counter1 in PWM Mode” on page 97 for a detailed description on this function. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. TIMER/COUNTER1 COUNT ENABLE PSR1 CS10 CS11 CS12 PCK (25.6 MHz) 0 CS13 3-BIT T/C PRESCALER PCK PCK/2 PCK/4 PCK/8 CK/2 CK/4 CK/8 CK/16 CK/32 CK/64 CK/128 CK/256 CK/512 CK/1024 10-BIT T/C PRESCALER CK (1.6 MHz) CK CLEAR CLEARATtiny25/45/85 [DATASHEET] 96 2586Q–AVR–08/2013 Figure 13-2. Timer/Counter 1 Synchronization Register Block Diagram. Timer/Counter1 and the prescaler allow running the CPU from any clock source while the prescaler is operating on the fast 25.6 MHz PCK clock in the asynchronous mode. The following Figure 13-3 shows the block diagram for Timer/Counter1. 8-BIT DATABUS OCR1A OCR1A_SI OCR1C OCR1C_SI TCNT_SO TCCR1 TCCR1_SI GTCCR GTCCR_SI TCNT1 TCNT1_SI OCF1A OCF1A_SI TOV1 TOV1_SI TOV1_SO OCF1A_SO TCNT1 S A S A PCKE CK PCK IO-registers Input synchronization registers Timer/Counter1 Output synchronization registers SYNC MODE ASYNC MODE 1 PCK Delay No Delay ~1 CK Delay 1PCK Delay No Delay TCNT1 OCF1A TOV1 1..2 PCK Delay 1..2 PCK Delay ~1 CK DelayATtiny25/45/85 [DATASHEET] 97 2586Q–AVR–08/2013 Figure 13-3. Timer/Counter1 Block Diagram Two status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1 and GTCCR. The interrupt enable/disable settings are found in the Timer/Counter Interrupt Mask Register - TIMSK. The Timer/Counter1 contains two Output Compare Registers, OCR1A and OCR1C as the data source to be compared with the Timer/Counter1 contents. In normal mode the Output Compare functions are operational with OCR1A only. OCR1A determines action on the OC1A pin (PB1), and it can generate Timer1 OC1A interrupt in normal mode and in PWM mode. OCR1C holds the Timer/Counter maximum value, i.e. the clear on compare match value. In the normal mode an overflow interrupt (TOV1) is generated when Timer/Counter1 counts from $FF to $00, while in the PWM mode the overflow interrupt is generated when the Timer/Counter1 counts either from $FF to $00 or from OCR1C to $00. In PWM mode, OCR1A provides the data values against which the Timer Counter value is compared. Upon compare match the PWM outputs (OC1A) is generated. In PWM mode, the Timer Counter counts up to the value specified in the output compare register OCR1C and starts again from $00. This feature allows limiting the counter “full” value to a specified value, lower than $FF. Together with the many prescaler options, flexible PWM frequency selection is provided. Table 12-3 on page 88 lists clock selection and OCR1C values to obtain PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution. 13.2.1 Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register A - OCR1A form an 8-bit, free-running and glitch-free PWM generator with output on the PB1(OC1A). 8-BIT DATABUS TIMER INT. FLAG REGISTER (TIFR) TIMER/COUNTER1 8-BIT COMPARATOR T/C1 OUTPUT COMPARE REGISTER TIMER INT. MASK REGISTER (TIMSK) TIMER/COUNTER1 (TCNT1) T/C CLEAR T/C1 CONTROL LOGIC TOV1 OCIE1A TOIE1 TOIE0 OCF1A TOV1 OCF1A CK PCK T/C1 OVERFLOW IRQ OC1A (PB1) T/C1 COMPARE MATCH A IRQ GLOBAL T/C CONTROL REGISTER 2 (GTCCR) PWM1A FOC1A (OCR1A) (OCR1C) 8-BIT COMPARATOR T/C1 OUTPUT COMPARE REGISTER TOV0 COM1A1 COM1A0 T/C CONTROL REGISTER 1 (TCCR1) CTC1 CS13 CS12 CS11 CS10 PSR1ATtiny25/45/85 [DATASHEET] 98 2586Q–AVR–08/2013 When the counter value match the content of OCR1A, the OC1A and output is set or cleared according to the COM1A1/COM1A0 bits in the Timer/Counter1 Control Register A - TCCR1, as shown in Table 13-1. Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output compare register OCR1C, and starting from $00 up again. A compare match with OCR1C will set an overflow interrupt flag (TOV1) after a synchronization delay following the compare event. Note that in PWM mode, writing to the Output Compare Register OCR1A, the data value is first transferred to a temporary location. The value is latched into OCR1A when the Timer/Counter reaches OCR1C. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A. See Figure 13-4 for an e xample. Figure 13-4. Effects of Unsynchronized OCR Latching During the time between the write and the latch operation, a read from OCR1A will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A. When OCR1A contains $00 or the top value, as specified in OCR1C register, the output PB1(OC1A) is held low or high according to the settings of COM1A1/COM1A0. This is shown in Table 13-2. Table 13-1. Compare Mode Select in PWM Mode COM1A1 COM1A0 Effect on Output Compare Pin 0 0 OC1A not connected. 0 1 OC1A not connected. 1 0 OC1A cleared on compare match. Set when TCNT1 = $00. 1 1 OC1A set on compare match. Cleared when TCNT1 = $00. Table 13-2. PWM Outputs OCR1A = $00 or OCR1C COM1A1 COM1A0 OCR1A Output OC1A 0 1 $00 L 0 1 OCR1C H 1 0 $00 L PWM Output OC1A PWM Output OC1A Unsynchronized OC1A Latch Synchronized OC1A Latch Counter Value Compare Value Counter Value Compare Value Compare Value changes Glitch Compare Value changesATtiny25/45/85 [DATASHEET] 99 2586Q–AVR–08/2013 In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C value and the TCNT1 is reset to $00. The Timer Overflow Interrupt1 is executed when TOV1 is set provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to the Timer Output Compare flags and interrupts. The PWM frequency can be derived from the timer/counter clock frequency using the following equation: The duty cycle of the PWM waveform can be calculated using the following equation: ...where TPCK is the period of the fast peripheral clock (1/25.6 MHz = 39.1 ns). Resolution indicates how many bits are required to express the value in the OCR1C register. It can be calculated using the following equation: 1 0 OCR1C H 1 1 $00 H 1 1 OCR1C L Table 13-3. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode PWM Frequency Clock Selection CS1[3:0] OCR1C RESOLUTION 20 kHz PCK/16 0101 199 7.6 30 kHz PCK/16 0101 132 7.1 40 kHz PCK/8 0100 199 7.6 50 kHz PCK/8 0100 159 7.3 60 kHz PCK/8 0100 132 7.1 70 kHz PCK/4 0011 228 7.8 80 kHz PCK/4 0011 199 7.6 90 kHz PCK/4 0011 177 7.5 100 kHz PCK/4 0011 159 7.3 110 kHz PCK/4 0011 144 7.2 120 kHz PCK/4 0011 132 7.1 130 kHz PCK/2 0010 245 7.9 140 kHz PCK/2 0010 228 7.8 150 kHz PCK/2 0010 212 7.7 Table 13-2. PWM Outputs OCR1A = $00 or OCR1C COM1A1 COM1A0 OCR1A Output OC1A f f TCK1 OCR1C + 1 = ----------------------------------- D OCR1A 1 + TTCK1 TPCK – OCR1C 1 + TTCK1 = ---------------------------------------------------------------------------- R = log2 OCR1C 1 ( ) +ATtiny25/45/85 [DATASHEET] 100 2586Q–AVR–08/2013 13.3 Register Description 13.3.1 TCCR1 – Timer/Counter1 Control Register • Bit 7 – CTC1 : Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1A register. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. • Bit 6 – PWM1A: Pulse Width Modulator A Enable When set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. • Bits 5:4 – COM1A[1:0]: Comparator A Output Mode, Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. In PWM mode, these bits have different functions. Refer to Table 13-1 on page 98 for a detailed description. 160 kHz PCK/2 0010 199 7.6 170 kHz PCK/2 0010 187 7.6 180 kHz PCK/2 0010 177 7.5 190 kHz PCK/2 0010 167 7.4 200 kHz PCK/2 0010 159 7.3 250 kHz PCK 0001 255 8.0 300 kHz PCK 0001 212 7.7 350 kHz PCK 0001 182 7.5 400 kHz PCK 0001 159 7.3 450 kHz PCK 0001 141 7.1 500 kHz PCK 0001 127 7.0 Table 13-3. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode (Continued) PWM Frequency Clock Selection CS1[3:0] OCR1C RESOLUTION Bit 7 6 5 4 3 2 1 0 0x30 CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 TCCR1A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Table 13-4. Comparator A Mode Select COM1A1 COM1A0 Description 0 0 Timer/Counter Comparator A disconnected from output pin OC1A. 0 1 Toggle the OC1A output line. 1 0 Clear the OC1A output line. 1 1 Set the OC1A output lineATtiny25/45/85 [DATASHEET] 101 2586Q–AVR–08/2013 • Bits 3:0 – CS1[3:0]: Clock Select Bits 3, 2, 1, and 0 The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. The Stop condition provides a Timer Enable/Disable function. 13.3.2 GTCCR – General Timer/Counter1 Control Register • Bit 2 – FOC1A: Force Output Compare Match 1A Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written in the same cycle as FOC1A, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit is set. • Bit 1 – PSR1 : Prescaler Reset Timer/Counter1 When this bit is set (one), the Timer/Counter prescaler (TCNT1 is unaffected) will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read as zero. Table 13-5. Timer/Counter1 Prescale Select CS13 CS12 CS11 CS10 T/C1 Clock 0 0 0 0 T/C1 stopped 0 0 0 1 PCK 0 0 1 0 PCK/2 0 0 1 1 PCK/4 0 1 0 0 PCK/8 0 1 0 1 CK 0 1 1 0 CK/2 0 1 1 1 CK/4 1 0 0 0 CK/8 1 0 0 1 CK/16 1 0 1 0 CK/32 1 0 1 1 CK/64 1 1 0 0 CK/128 1 1 0 1 CK/256 1 1 1 0 CK/512 1 1 1 1 CK/1024 Bit 7 6 5 4 3 2 1 0 0x2C TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 GTCCR Read/Write R/W R/W R/W R/W W W R/W R/W Initial value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 102 2586Q–AVR–08/2013 13.3.3 TCNT1 – Timer/Counter1 This 8-bit register contains the value of Timer/Counter1. Timer/Counter1 is realized as an up counter with read and write access. Due to synchronization of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one CPU clock cycle in synchronous mode and at most two CPU clock cycles for asynchronous mode. 13.3.4 OCR1A – Timer/Counter1 Output Compare RegisterA The output compare register A is an 8-bit read/write register. The Timer/Counter Output Compare Register A contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and OCR1A to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1A after a synchronization delay following the compare event. 13.3.5 OCR1C – Timer/Counter1 Output Compare Register C The Output Compare Register B - OCR1B from ATtiny15 is replaced with the output compare register C - OCR1C that is an 8-bit read/write register. This register has the same function as the Output Compare Register B in ATtiny15. The Timer/Counter Output Compare Register C contains data to be continuously compared with Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C value. A software write that sets TCNT1 and OCR1C to the same value does not generate a compare match. If the CTC1 bit in TCCR1 is set, a compare match will clear TCNT1. 13.3.6 TIMSK – Timer/Counter Interrupt Mask Register • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. Bit 7 6 5 4 3 2 1 0 0x2F MSB LSB TCNT1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x2E MSB LSB OCR1A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x2D MSB LSB OCR1C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 0x39 – OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 – TIMSK Read/Write R R/W R/W R/W R/W R/W R/W R Initial value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 103 2586Q–AVR–08/2013 • Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register. • Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. 13.3.7 TIFR – Timer/Counter Interrupt Flag Register • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. • Bit 6 – OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 A compare match interrupt is executed. • Bit 2 – TOV1: Timer/Counter1 Overflow Flag The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared, after synchronization clock cycle, by writing a logical one to the flag. When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. 13.3.8 PLLCSR – PLL Control and Status Register • Bits 6:3 – Res : Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and always read as zero. • Bit 2 – PCKE: PCK Enable The bit PCKE is always set in the ATtiny15 compatibility mode. • Bit 1 – PLLE: PLL Enable The PLL is always enabled in the ATtiny15 compatibility mode. Bit 7 6 5 4 3 2 1 0 0x38 – OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 – TIFR Read/Write R R/W R/W R/W R/W R/W R/W R Initial value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x27 LSM – – – – PCKE PLLE PLOCK PLLCSR Read/Write R/W R R R R R/W R/W R Initial value 0 0 0 0 0 0 0/1 0ATtiny25/45/85 [DATASHEET] 104 2586Q–AVR–08/2013 • Bit 0 – PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock. The PLOCK bit should be ignored during initial PLL lock-in sequence when PLL frequency overshoots and undershoots, before reaching steady state. The steady state is obtained within 100 µs. After PLL lock-in it is recommended to check the PLOCK bit before enabling PCK for Timer/Counter1.ATtiny25/45/85 [DATASHEET] 105 2586Q–AVR–08/2013 14. Dead Time Generator The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be connected to Timer/Counter1 and it is used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary output pairs (OC1A-OC1A and OC1B-OC1B). The sharing of tasks is as follows: the timer/counter generates the PWM output and the Dead Time Generator generates the non-overlapping PWM output pair from the timer/counter PWM signal. Two Dead Time Generators are provided, one for each PWM output. The non-overlap time is adjustable and the PWM output and it’s complementary output are adjusted separately, and independently for both PWM outputs. Figure 14-1. Timer/Counter1 & Dead Time Generators The dead time generation is based on the 4-bit down counters that count the dead time, as shown in Figure 46. There is a dedicated prescaler in front of the Dead Time Generator that can divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8. This provides for large range of dead times that can be generated. The prescaler is controlled by two control bits DTPS1[1:0] from the I/O register at address 0x23. The block has also a rising and falling edge detector that is used to start the dead time counting period. Depending on the edge, one of the transitions on the rising edges, OC1x or OC1x is delayed until the counter has counted to zero. The comparator is used to compare the counter with zero and stop the dead time insertion when zero has been reached. The counter is loaded with a 4-bit DT1xH or DT1xL value from DT1x I/O register, depending on the edge of the PWM generator output when the dead time insertion is started. Figure 14-2. Dead Time Generator The length of the counting period is user adjustable by selecting the dead time prescaler setting in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM output and its’ complementary output separately. Thus TIMER/COUNTER1 OC1A OC1A OC1B OC1B DEAD TIME GENERATOR PWM GENERATOR PCKE T15M PCK CK DT1AH DT1BH DEAD TIME GENERATOR PWM1A PWM1B DT1AL DT1BL CLOCK CONTROL OC1x OC1x T/C1 CLOCK PWM1x 4-BIT COUNTER COMPARATOR DT1xH DT1xL DT1x I/O REGISTER DEAD TIME PRESCALER DTPS1[1:0]ATtiny25/45/85 [DATASHEET] 106 2586Q–AVR–08/2013 the rising edge of OC1x and OC1x can have different dead time periods. The dead time is adjusted as the number of prescaled dead time generator clock cycles. Figure 14-3. The Complementary Output Pair 14.1 Register Description 14.1.1 DTPS1 – Timer/Counter1 Dead Time Prescaler Register 1 The dead time prescaler register, DTPS1 is a 2-bit read/write register. • Bits 1:0 – DTPS1[1:0]: Dead Time Prescaler The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can be generated. The Dead Time prescaler is controlled by two bits DTPS1[1:0] from the Dead Time Prescaler register. These bits define the division factor of the Dead Time prescaler. The division factors are given in table 46. OC1x x = A or B t non-overlap / rising edge t non-overlap / falling edge OC1x PWM1x Bit 7 6 5 4 3 2 1 0 0x23 DTPS11 DTPS10 DTPS1 Read/Write R R R R R R R/W R/W Initial value 0 0 0 0 0 0 0 0 Table 14-1. Division factors of the Dead Time prescaler DTPS11 DTPS10 Prescaler divides the T/C1 clock by 0 0 1x (no division) 0 1 2x 1 0 4x 1 1 8xATtiny25/45/85 [DATASHEET] 107 2586Q–AVR–08/2013 14.1.2 DT1A – Timer/Counter1 Dead Time A The dead time value register A is an 8-bit read/write register. The dead time delay of is adjusted by the dead time value register, DT1A. The register consists of two fields, DT1AH[3:0] and DT1AL[3:0], one for each complementary output. Therefore a different dead time delay can be adjusted for the rising edge of OC1A and the rising edge of OC1A. • Bits 7:4 – DT1AH[3:0]: Dead Time Value for OC1A Output The dead time value for the OC1A output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. • Bits 3:0 – DT1AL[3:0]: Dead Time Value for OC1A Output The dead time value for the OC1A output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. 14.1.3 DT1B – Timer/Counter1 Dead Time B The dead time value register Bis an 8-bit read/write register. The dead time delay of is adjusted by the dead time value register, DT1B. The register consists of two fields, DT1BH[3:0] and DT1BL[3:0], one for each complementary output. Therefore a different dead time delay can be adjusted for the rising edge of OC1A and the rising edge of OC1A. • Bits 7:4 – DT1BH[3:0]: Dead Time Value for OC1B Output The dead time value for the OC1B output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. • Bits 3:0 – DT1BL[3:0]: Dead Time Value for OC1B Output The dead time value for the OC1B output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. Bit 7 6 5 4 3 2 1 0 0x25 DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 DT1A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x24 DT1BH3 DT1BH2 DT1BH1 DT1BH0 DT1BL3 DT1BL2 DT1BL1 DT1BL0 DT1B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 108 2586Q–AVR–08/2013 15. USI – Universal Serial Interface 15.1 Features • Two-wire Synchronous Data Transfer (Master or Slave) • Three-wire Synchronous Data Transfer (Master or Slave) • Data Received Interrupt • Wakeup from Idle Mode • Wake-up from All Sleep Modes In Two-wire Mode • Two-wire Start Condition Detector with Interrupt Capability 15.2 Overview The Universal Serial Interface (USI), provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load. A simplified block diagram of the USI is shown in Figure 15-1 For actual placement of I/O pins refer to “Pinout ATtiny25/45/85” on page 2. Device-specific I/O Register and bit locations are listed in the “Register Descriptions” on page 115. Figure 15-1. Universal Serial Interface, Block Diagram The 8-bit USI Data Register (USIDR) contains the incoming and outgoing data. It is directly accessible via the data bus but a copy of the contents is also placed in the USI Buffer Register (USIBR) where it can be retrieved later. If reading the USI Data Register directly, the register must be read as quickly as possible to ensure that no data is lost. The most significant bit of the USI Data Register is connected to one of two output pins (depending on the mode configuration, see “USICR – USI Control Register” on page 116). There is a transparent latch between the output of the USI Data Register and the output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. DATA BUS USIPF USICS1 USICS0 USICLK USITC USIOIF USIOIE USISIF USIDC USISIE Bit7 USIWM1 USIWM0 Two-wire Clock Control Unit DO (Output only) DI/SDA (Input/Open Drain) USCK/SCL (Input/Open Drain) 4-bit Counter USIDR USISR D Q LE USICR CLOCK HOLD TIM0 COMP Bit0 [1] 3 0 1 2 3 0 1 2 0 1 2 USIBRATtiny25/45/85 [DATASHEET] 109 2586Q–AVR–08/2013 The 4-bit counter can be both read and written via the data bus, and it can generate an overflow interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. This means the counter registers the number of clock edges and not the number of data bits. The clock can be selected from three different sources: The USCK pin, Timer/Counter0 Compare Match or from software. The two-wire clock control unit can be configured to generate an interrupt when a start condition has been detected on the two-wire bus. It can also be set to generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows. 15.3 Functional Descriptions 15.3.1 Three-wire Mode The USI three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software, if required. Pin names used in this mode are DI, DO, and USCK. Figure 15-2. Three-wire Mode Operation, Simplified Diagram Figure 15-2 shows two USI units operating in three-wire mode, one as Master and one as Slave. The two USI Data Registers are interconnected in such way that after eight USCK clocks, the data in each register has been interchanged. The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORTB register or by writing a one to bit USITC bit in USICR. SLAVE MASTER Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DO DI USCK Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DO DI USCK PORTxnATtiny25/45/85 [DATASHEET] 110 2586Q–AVR–08/2013 Figure 15-3. Three-Wire Mode, Timing Diagram The three-wire mode timing is shown in Figure 15-3 At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes. In external clock mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (USI Data Register is shifted by one) at negative edges. In external clock mode 1 (USICS0 = 1) the opposite edges with respect to mode 0 are used. In other words, data is sampled at negative and changes the output at positive edges. The USI clock modes corresponds to the SPI data mode 0 and 1. Referring to the timing diagram (Figure 15-3), a bus transfer involves the following steps: 1. The slave and master devices set up their data outputs and, depending on the protocol used, enable their output drivers (mark A and B). The output is set up by writing the data to be transmitted to the USI Data Register. The output is enabled by setting the corresponding bit in the Data Direction Register of Port B. Note that there is not a preferred order of points A and B in the figure, but both must be at least one half USCK cycle before point C, where the data is sampled. This is in order to ensure that the data setup requirement is satisfied. The 4-bit counter is reset to zero. 2. The master software generates a clock pulse by toggling the USCK line twice (C and D). The bit values on the data input (DI) pins are sampled by the USI on the first edge (C), and the data output is changed on the opposite edge (D). The 4-bit counter will count both edges. 3. Step 2. is repeated eight times for a complete register (byte) transfer. 4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that the transfer has been completed. If USI Buffer Registers are not used the data bytes that have been transferred must now be processed before a new transfer can be initiated. The overflow interrupt will wake up the processor if it is set to Idle mode. Depending of the protocol used the slave device can now set its output to high impedance. 15.3.2 SPI Master Operation Example The following code demonstrates how to use the USI as an SPI Master: SPITransfer: out USIDR,r16 ldi r16,(1< 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz 20.5.1 Serial Programming Algorithm When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK. When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See Figure 21-4 and Figure 21-5 for timing details. Table 20-10. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB0 I Serial Data in MISO PB1 O Serial Data out SCK PB2 I Serial Clock VCC GND SCK MISO MOSI RESET +1.8 - 5.5VATtiny25/45/85 [DATASHEET] 152 2586Q–AVR–08/2013 To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 20-12): 1. Power-up sequence: apply power between VCC and GND while RESET and SCK are set to “0” – In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse after SCK has been set to '0'. The duration of the pulse must be at least tRST plus two CPU clock cycles. See Table 21-4 on page 165 for minimum pulse width on RESET pin, tRST 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 5 LSB of the address and data together with the Load Program memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program memory Page is stored by loading the Write Program memory Page instruction with the 6 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 20-11.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 20-11.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed. B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 6 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the next page (See Table 20-9). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off.ATtiny25/45/85 [DATASHEET] 153 2586Q–AVR–08/2013 20.5.2 Serial Programming Instruction set Table 20-12 on page 153 and Figure 20-2 on page 154 describes the Instruction set. Notes: 1. Not all instructions are applicable for all parts. Table 20-11. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 9.0 ms tWD_FUSE 4.5 ms Table 20-12. Serial Programming Instruction Set Instruction/Operation Instruction Format Byte 1 Byte 2 Byte 3 Byte4 Programming Enable $AC $53 $00 $00 Chip Erase (Program Memory/EEPROM) $AC $80 $00 $00 Poll RDY/BSY $F0 $00 $00 data byte out Load Instructions Load Extended Address byte(1) $4D $00 Extended adr $00 Load Program Memory Page, High byte $48 adr MSB adr LSB high data byte in Load Program Memory Page, Low byte $40 adr MSB adr LSB low data byte in Load EEPROM Memory Page (page access) $C1 $00 0000 000aa data byte in Read Instructions Read Program Memory, High byte $28 adr MSB adr LSB high data byte out Read Program Memory, Low byte $20 adr MSB adr LSB low data byte out Read EEPROM Memory $A0 $00 00aa aaaa data byte out Read Lock bits $58 $00 $00 data byte out Read Signature Byte $30 $00 0000 000aa data byte out Read Fuse bits $50 $00 $00 data byte out Read Fuse High bits $58 $08 $00 data byte out Read Extended Fuse Bits $50 $08 $00 data byte out Read Calibration Byte $38 $00 $00 data byte out Write Instructions(6) Write Program Memory Page $4C adr MSB adr LSB $00 Write EEPROM Memory $C0 $00 00aa aaaa data byte in Write EEPROM Memory Page (page access) $C2 $00 00aa aa00 $00 Write Lock bits $AC $E0 $00 data byte in Write Fuse bits $AC $A0 $00 data byte in Write Fuse High bits $AC $A8 $00 data byte in Write Extended Fuse Bits $AC $A4 $00 data byte inATtiny25/45/85 [DATASHEET] 154 2586Q–AVR–08/2013 2. a = address 3. Bits are programmed ‘0’, unprogrammed ‘1’. 4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) . 5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers. If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out. Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 20-2 on page 154. Figure 20-2. Serial Programming Instruction example Byte 1 Byte 2 Byte 3 Byte 4 Adr MSB Adr LSB Bit 15 B 0 Serial Programming Instruction Program Memory/ EEPROM Memory Page 0 Page 1 Page 2 Page N-1 Page Buffer Write Program Memory Page/ Write EEPROM Memory Page Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Byte 3 Byte 4 Bit 15 B 0 Adr MSB Adr LSB Page Offset Page Number Adr MSB Adr LSBATtiny25/45/85 [DATASHEET] 155 2586Q–AVR–08/2013 20.6 High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the ATtiny25/45/85. Figure 20-3. High-voltage Serial Programming The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Programming is 220 ns. 20.7 High-voltage Serial Programming Algorithm To program and verify the ATtiny25/45/85 in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in Table 20-16): Table 20-13. Pin Name Mapping Signal Name in High-voltage Serial Programming Mode Pin Name I/O Function SDI PB0 I Serial Data Input SII PB1 I Serial Instruction Input SDO PB2 O Serial Data Output SCI PB3 I Serial Clock Input (min. 220ns period) Table 20-14. Pin Values Used to Enter Programming Mode Pin Symbol Value SDI Prog_enable[0] 0 SII Prog_enable[1] 0 SDO Prog_enable[2] 0 VCC GND SDO SII SDI (RESET) +4.5 - 5.5V PB0 PB1 PB2 PB5 +11.5 - 12.5V SCI PB3ATtiny25/45/85 [DATASHEET] 156 2586Q–AVR–08/2013 20.7.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1. Set Prog_enable pins listed in Table 20-14 to “000”, RESET pin and VCC to 0V. 2. Apply 4.5 - 5.5V between VCC and GND. Ensure that VCC reaches at least 1.8V within the next 20 µs. 3. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET. 4. Keep the Prog_enable pins unchanged for at least 10 µs after the High-voltage has been applied to ensure the Prog_enable Signature has been latched. 5. Release the Prog_enable[2] pin to avoid drive contention on the Prog_enable[2]/SDO pin. 6. Wait at least 300 µs before giving any serial instructions on SDI/SII. 7. Exit Programming mode by power the device down or by bringing RESET pin to 0V. If the rise time of the VCC is unable to fulfill the requirements listed above, the following alternative algorithm can be used: 1. Set Prog_enable pins listed in Table 20-14 to “000”, RESET pin and VCC to 0V. 2. Apply 4.5 - 5.5V between VCC and GND. 3. Monitor VCC, and as soon as VCC reaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET. 4. Keep the Prog_enable pins unchanged for at least 10 µs after the High-voltage has been applied to ensure the Prog_enable Signature has been latched. 5. Release the Prog_enable[2] pin to avoid drive contention on the Prog_enable[2]/SDO pin. 6. Wait until VCC actually reaches 4.5 - 5.5V before giving any serial instructions on SDI/SII. 7. Exit Programming mode by power the device down or by bringing RESET pin to 0V. 20.7.2 Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. • The command needs only be loaded once when writing or reading multiple memory locations. • Skip writing the data value 0xFF that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase. • Address High byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading. 20.7.3 Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the Program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are re-programmed. Note: 1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. Table 20-15. High-voltage Reset Characteristics Supply Voltage RESET Pin High-voltage Threshold Minimum High-voltage Period for Latching Prog_enable VCC VHVRST tHVRST 4.5V 11.5V 100 ns 5.5V 11.5V 100 nsATtiny25/45/85 [DATASHEET] 157 2586Q–AVR–08/2013 1. Load command “Chip Erase” (see Table 20-16). 2. Wait after Instr. 3 until SDO goes high for the “Chip Erase” cycle to finish. 3. Load Command “No Operation”. 20.7.4 Programming the Flash The Flash is organized in pages, see Table 20-12 on page 153. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: 1. Load Command “Write Flash” (see Table 20-16). 2. Load Flash Page Buffer. 3. Load Flash High Address and Program Page. Wait after Instr. 3 until SDO goes high for the “Page Programming” cycle to finish. 4. Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed. 5. End Page Programming by Loading Command “No Operation”. When writing or reading serial data to the ATtiny25/45/85, data is clocked on the rising edge of the serial clock, see Figure 20-5, Figure 21-6 and Table 21-12 for details. Figure 20-4. Addressing the Flash which is Organized in Pages Figure 20-5. High-voltage Serial Programming Waveforms PROGRAM MEMORY WORD ADDRESS WITHIN A PAGE PAGE ADDRESS WITHIN THE FLASH INSTRUCTION WORD PAGE PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND PAGE PCPAGE PCWORD PCMSB PAGEMSB PROGRAM COUNTER MSB MSB MSB LSB LSB LSB 0 1 2 3 4 5 6 7 8 9 10 SDI PB0 SII PB1 SDO PB2 SCI PB3ATtiny25/45/85 [DATASHEET] 158 2586Q–AVR–08/2013 20.7.5 Programming the EEPROM The EEPROM is organized in pages, see Table 21-11 on page 170. When programming the EEPROM, the data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM Data memory is as follows (refer to Table 20-16): 1. Load Command “Write EEPROM”. 2. Load EEPROM Page Buffer. 3. Program EEPROM Page. Wait after Instr. 2 until SDO goes high for the “Page Programming” cycle to finish. 4. Repeat 2 through 3 until the entire EEPROM is programmed or until all data has been programmed. 5. End Page Programming by Loading Command “No Operation”. 20.7.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to Table 20-16): 1. Load Command "Read Flash". 2. Read Flash Low and High Bytes. The contents at the selected address are available at serial output SDO. 20.7.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to Table 20-16): 1. Load Command “Read EEPROM”. 2. Read EEPROM Byte. The contents at the selected address are available at serial output SDO. 20.7.8 Programming and Reading the Fuse and Lock Bits The algorithms for programming and reading the Fuse Low/High bits and Lock bits are shown in Table 20-16. 20.7.9 Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in Table 20-16. 20.7.10 Power-off sequence Set SCI to “0”. Set RESET to “1”. Turn VCC power off. Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 Instruction Instruction Format Instr.1/5 Instr.2/6 Instr.3 Instr.4 Operation Remarks Chip Erase SDI SII SDO 0_1000_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Wait after Instr.3 until SDO goes high for the Chip Erase cycle to finish. Load “Write Flash” Command SDI SII SDO 0_0001_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx Enter Flash Programming code. Load Flash Page Buffer SDI SII SDO 0_bbbb_bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx 0_eeee_eeee_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_dddd_dddd_00 0_0011_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1101_00 x_xxxx_xxxx_xx Repeat after Instr. 1 - 5 until the entire page buffer is filled or until all data within the page is filled.(2) SDI SII SDO 0_0000_0000_00 0_0111_1100_00 x_xxxx_xxxx_xx Instr 5.ATtiny25/45/85 [DATASHEET] 159 2586Q–AVR–08/2013 Load Flash High Address and Program Page SDI SII SDO 0_0000_000a_00 0_0001_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Wait after Instr 3 until SDO goes high. Repeat Instr. 2 - 3 for each loaded Flash Page until the entire Flash or all data is programmed. Repeat Instr. 1 for a new 256 byte page.(2) Load “Read Flash” Command SDI SII SDO 0_0000_0010_00 0_0100_1100_00 x_xxxx_xxxx_xx Enter Flash Read mode. Read Flash Low and High Bytes SDI SII SDO 0_bbbb_bbbb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_000a_00 0_0001_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 q_qqqq_qqqx_xx Repeat Instr. 1, 3 - 6 for each new address. Repeat Instr. 2 for a new 256 byte page. SDI SII SDO 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 p_pppp_pppx_xx Instr 5 - 6. Load “Write EEPROM” Command SDI SII SDO 0_0001_0001_00 0_0100_1100_00 x_xxxx_xxxx_xx Enter EEPROM Programming mode. Load EEPROM Page Buffer SDI SII SDO 0_00bb_bbbb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_aaaa_aaaa_00 0_0001_1100_00 x_xxxx_xxxx_xx 0_eeee_eeee_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1101_00 x_xxxx_xxxx_xx Repeat Instr. 1 - 5 until the entire page buffer is filled or until all data within the page is filled.(3) SDI SII SDO 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Instr. 5 Program EEPROM Page SDI SII SDO 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Wait after Instr. 2 until SDO goes high. Repeat Instr. 1 - 2 for each loaded EEPROM page until the entire EEPROM or all data is programmed. Write EEPROM Byte SDI SII SDO 0_bbbb_bbbb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_aaaa_aaaa_00 0_0001_1100_00 x_xxxx_xxxx_xx 0_eeee_eeee_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1101_00 x_xxxx_xxxx_xx Repeat Instr. 1 - 6 for each new address. Wait after Instr. 6 until SDO goes high.(4) SDI SII SDO 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Instr. 6 Load “Read EEPROM” Command SDI SII SDO 0_0000_0011_00 0_0100_1100_00 x_xxxx_xxxx_xx Enter EEPROM Read mode. Read EEPROM Byte SDI SII SDO 0_bbbb_bbbb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_aaaa_aaaa_00 0_0001_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 q_qqqq_qqq0_00 Repeat Instr. 1, 3 - 4 for each new address. Repeat Instr. 2 for a new 256 byte page. Write Fuse Low Bits SDI SII SDO 0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_A987_6543_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Wait after Instr. 4 until SDO goes high. Write A - 3 = “0” to program the Fuse bit. Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued) Instruction Instruction Format Instr.1/5 Instr.2/6 Instr.3 Instr.4 Operation RemarksATtiny25/45/85 [DATASHEET] 160 2586Q–AVR–08/2013 Notes: 1. a = address high bits, b = address low bits, d = data in high bits, e = data in low bits, p = data out high bits, q = data out low bits, x = don’t care, 1 = Lock Bit1, 2 = Lock Bit2, 3 = CKSEL0 Fuse, 4 = CKSEL1 Fuse, 5 = CKSEL2 Fuse, 6 = CKSEL3 Fuse, 7 = SUT0 Fuse, 8 = SUT1 Fuse, 9 = CKOUT Fuse, A = CKDIV8 Fuse, B = BODLEVEL0 Fuse, C = BODLEVEL1 Fuse, D = BODLEVEL2 Fuse, E = EESAVE Fuse, F = WDTON Fuse, G = SPIEN Fuse, H = DWEN Fuse, I = RSTDISBL Fuse, J = SELFPRGEN Fuse 2. For page sizes less than 256 words, parts of the address (bbbb_bbbb) will be parts of the page address. 3. For page sizes less than 256 bytes, parts of the address (bbbb_bbbb) will be parts of the page address. 4. The EEPROM is written page-wise. But only the bytes that are loaded into the page are actually written to the EEPROM. Page-wise EEPROM access is more efficient when multiple bytes are to be written to the same page. Note that auto-erase of EEPROM is not available in High-voltage Serial Programming, only in SPI Programming. Write Fuse High Bits SDI SII SDO 0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_IHGF_EDCB_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 x_xxxx_xxxx_xx Wait after Instr. 4 until SDO goes high. Write I - B = “0” to program the Fuse bit. Write Fuse Extended Bits SDI SII SDO 0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_000J_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0110_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1110_00 x_xxxx_xxxx_xx Wait after Instr. 4 until SDO goes high. Write J = “0” to program the Fuse bit. Write Lock Bits SDI SII SDO 0_0010_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0021_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Wait after Instr. 4 until SDO goes high. Write 2 - 1 = “0” to program the Lock bit. Read Fuse Low Bits SDI SII SDO 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 A_9876_543x_xx Reading A - 3 = “0” means the Fuse bit is programmed. Read Fuse High Bits SDI SII SDO 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1010_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1110_00 I_HGFE_DCBx_xx Reading I - B = “0” means the Fuse bit is programmed. Read Fuse Extended Bits SDI SII SDO 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1010_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1110_00 x_xxxx_xxJx_xx Reading J = “0” means the Fuse bit is programmed. Read Lock Bits SDI SII SDO 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 x_xxxx_x21x_xx Reading 2, 1 = “0” means the Lock bit is programmed. Read Signature Bytes SDI SII SDO 0_0000_1000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_00bb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 q_qqqq_qqqx_xx Repeats Instr 2 4 for each signature byte address. Read Calibration Byte SDI SII SDO 0_0000_1000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 p_pppp_pppx_xx Load “No Operation” Command SDI SII SDO 0_0000_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued) Instruction Instruction Format Instr.1/5 Instr.2/6 Instr.3 Instr.4 Operation RemarksATtiny25/45/85 [DATASHEET] 161 2586Q–AVR–08/2013 21. Electrical Characteristics 21.1 Absolute Maximum Ratings* 21.2 DC Characteristics Operating Temperature.................................. -55C to +125C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins................................ 200.0 mA Table 21-1. DC Characteristics. TA = -40C to +85C Symbol Parameter Condition Min. Typ.(1) Max. Units VIL Input Low-voltage, except XTAL1 and RESET pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V -0.5 -0.5 0.2VCC(3) 0.3VCC(3) V V VIH Input High-voltage, except XTAL1 and RESET pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.7VCC(2) 0.6VCC(2) VCC +0.5 VCC +0.5 V V VIL1 Input Low-voltage, XTAL1 pin, External Clock Selected VCC = 1.8V - 5.5V -0.5 0.1VCC(3) V VIH1 Input High-voltage, XTAL1 pin, External Clock Selected VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.8VCC(2) 0.7VCC(2) VCC +0.5 VCC +0.5 V V VIL2 Input Low-voltage, RESET pin VCC = 1.8V - 5.5V -0.5 0.2VCC(3) V V VIH2 Input High-voltage, RESET pin VCC = 1.8V - 5.5V 0.9VCC(2) VCC +0.5 V VIL3 Input Low-voltage, RESET pin as I/O VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V -0.5 -0.5 0.2VCC(3) 0.3VCC(3) V V VIH3 Input High-voltage, RESET pin as I/O VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.7VCC(2) 0.6VCC(2) VCC +0.5 VCC +0.5 V V VOL Output Low-voltage,(4) Port B (except RESET) (6) IOL = 10 mA, VCC = 5V IOL = 5 mA, VCC = 3V 0.6 0.5 V V VOH Output High-voltage, (5) Port B (except RESET) (6) IOH = -10 mA, VCC = 5V IOH = -5 mA, VCC = 3V 4.3 2.5 V V IIL Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) < 0.05 1 µA IIH Input Leakage Current I/O Pin VCC = 5.5V, pin high (absolute value) < 0.05 1 µA RRST Reset Pull-up Resistor VCC = 5.5V, input low 30 60 kATtiny25/45/85 [DATASHEET] 162 2586Q–AVR–08/2013 Notes: 1. Typical values at 25C. 2. “Min” means the lowest value where the pin is guaranteed to be read as high. 3. “Max” means the highest value where the pin is guaranteed to be read as low. 4. Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOL, for all ports, should not exceed 60 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 5. Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOH, for all ports, should not exceed 60 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 6. The RESET pin must tolerate high voltages when entering and operating in programming modes and, as a consequence, has a weak drive strength as compared to regular I/O pins. See Figure 22-23, Figure 22-24, Figure 22-25, and Figure 22-26 (starting on page 184). 7. Values are with external clock using methods described in “Minimizing Power Consumption” on page 36. Power Reduction is enabled (PRR = 0xFF) and there is no I/O drive. 8. Brown-Out Detection (BOD) disabled. Rpu I/O Pin Pull-up Resistor VCC = 5.5V, input low 20 50 k ICC Power Supply Current (7) Active 1 MHz, VCC = 2V 0.3 0.55 mA Active 4 MHz, VCC = 3V 1.5 2.5 mA Active 8 MHz, VCC = 5V 5 8 mA Idle 1 MHz, VCC = 2V 0.1 0.2 mA Idle 4 MHz, VCC = 3V 0.35 0.6 mA Idle 8 MHz, VCC = 5V 1.2 2 mA Power-down mode (8) WDT enabled, VCC = 3V 10 µA WDT disabled, VCC = 3V 2 µA Table 21-1. DC Characteristics. TA = -40C to +85C (Continued) Symbol Parameter Condition Min. Typ.(1) Max. UnitsATtiny25/45/85 [DATASHEET] 163 2586Q–AVR–08/2013 21.3 Speed Figure 21-1. Maximum Frequency vs. VCC Figure 21-2. Maximum Frequency vs. VCC 10 MHz 4 MHz 1.8V 2.7V 5.5V Safe Operating Area 20 MHz 10 MHz 2.7V 4.5V 5.5V Safe Operating AreaATtiny25/45/85 [DATASHEET] 164 2586Q–AVR–08/2013 21.4 Clock Characteristics 21.4.1 Calibrated Internal RC Oscillator Accuracy It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Please note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in Figure 22-40 on page 193 and Figure 22-41 on page 193. Notes: 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage). 2. ATtiny25/V, only: 6.4 MHz in ATtiny15 Compatibility Mode. 3. Voltage range for ATtiny25V/45V/85V. 4. Voltage range for ATtiny25/45/85. 21.4.2 External Clock Drive Figure 21-3. External Clock Drive Waveforms Table 21-2. Calibration Accuracy of Internal RC Oscillator Calibration Method Target Frequency VCC Temperature Accuracy at given Voltage & Temperature (1) Factory Calibration 8.0 MHz (2) 3V 25C ±10% User Calibration Fixed frequency within: 6 – 8 MHz Fixed voltage within: 1.8V - 5.5V (3) 2.7V - 5.5V (4) Fixed temperature within: -40C to +85C ±1% VIL1 VIH1 Table 21-3. External Clock Drive Characteristics Symbol Parameter VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Min. Max. Min. Max. Min. Max. Units 1/tCLCL Clock Frequency 0 4 0 10 0 20 MHz tCLCL Clock Period 250 100 50 ns tCHCX High Time 100 40 20 ns tCLCX Low Time 100 40 20 ns tCLCH Rise Time 2.0 1.6 0.5 µs tCHCL Fall Time 2.0 1.6 0.5 µs t CLCL Change in period from one clock cycle to the next 2 2 2 %ATtiny25/45/85 [DATASHEET] 165 2586Q–AVR–08/2013 21.5 System and Reset Characteristics Note: 1. Values are guidelines only. Two versions of power-on reset have been implemented, as follows. 21.5.1 Standard Power-On Reset This implementation of power-on reset existed in early versions of ATtiny25/45/85. The table below describes the characteristics of this power-on reset and it is valid for the following devices, only: • ATtiny25, revision D, and older • ATtiny45, revision F, and older • ATtiny85, revision B, and newer Note: Revisions are marked on the package (packages 8P3 and 8S2: bottom, package 20M1: top) Note: 1. Values are guidelines, only 2. Threshold where device is released from reset when voltage is rising 3. The power-on reset will not work unless the supply voltage has been below VPOA 21.5.2 Enhanced Power-On Reset This implementation of power-on reset exists in newer versions of ATtiny25/45/85. The table below describes the characteristics of this power-on reset and it is valid for the following devices, only: • ATtiny25, revision E, and newer Table 21-4. Reset, Brown-out and Internal Voltage Characteristics Symbol Parameter Condition Min(1) Typ(1) Max(1) Units VRST RESET Pin Threshold Voltage VCC = 3V 0.2 VCC 0.9 VCC V tRST Minimum pulse width on RESET Pin VCC = 3V 2.5 µs VHYST Brown-out Detector Hysteresis 50 mV tBOD Min Pulse Width on Brown-out Reset 2 µs VBG Bandgap reference voltage VCC = 5.5V TA = 25°C 1.0 1.1 1.2 V tBG Bandgap reference start-up time VCC = 2.7V TA = 25°C 40 70 µs IBG Bandgap reference current consumption VCC = 2.7V TA = 25°C 15 µA Table 21-5. Characteristics of Standard Power-On Reset. TA = -40 to +85C Symbol Parameter Min(1) Typ(1) Max(1) Units VPOR Release threshold of power-on reset (2) 0.7 1.0 1.4 V VPOA Activation threshold of power-on reset (3) 0.05 0.9 1.3 V SRON Power-on slope rate 0.01 4.5 V/msATtiny25/45/85 [DATASHEET] 166 2586Q–AVR–08/2013 • ATtiny45, revision G, and newer • ATtiny85, revision C, and newer Note: 1. Values are guidelines, only 2. Threshold where device is released from reset when voltage is rising 3. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling) 21.6 Brown-Out Detection Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. Table 21-6. Characteristics of Enhanced Power-On Reset. TA = -40C to +85C Symbol Parameter Min(1) Typ(1) Max(1) Units VPOR Release threshold of power-on reset (2) 1.1 1.4 1.6 V VPOA Activation threshold of power-on reset (3) 0.6 1.3 1.6 V SRON Power-On Slope Rate 0.01 V/ms Table 21-7. BODLEVEL Fuse Coding. TA = -40C to +85C BODLEVEL[2:0] Fuses Min(1) Typ(1) Max(1) Units 111 BOD Disabled 110 1.7 1.8 2.0 101 2.5 2.7 2.9 V 100 4.1 4.3 4.5 0XX ReservedATtiny25/45/85 [DATASHEET] 167 2586Q–AVR–08/2013 21.7 ADC Characteristics Note: 1. Values are guidelines only. Table 21-8. ADC Characteristics, Single Ended Channels. TA = -40C to +85C Symbol Parameter Condition Min Typ Max Units Resolution 10 Bits Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset errors) VREF = 4V, VCC = 4V, ADC clock = 200 kHz 2 LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz 3 LSB VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 1.5 LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 2.5 LSB Integral Non-linearity (INL) (Accuracy after offset and gain calibration) VREF = 4V, VCC = 4V, ADC clock = 200 kHz 1 LSB Differential Non-linearity (DNL) VREF = 4V, VCC = 4V, ADC clock = 200 kHz 0.5 LSB Gain Error VREF = 4V, VCC = 4V, ADC clock = 200 kHz 2.5 LSB Offset Error VREF = 4V, VCC = 4V, ADC clock = 200 kHz 1.5 LSB Conversion Time Free Running Conversion 14 280 µs Clock Frequency 50 1000 kHz VIN Input Voltage GND VREF V Input Bandwidth 38.4 kHz AREF External Reference Voltage 2.0 VCC V VINT Internal Voltage Reference 1.0 1.1 1.2 V Internal 2.56V Reference (1) VCC > 3.0V 2.3 2.56 2.8 V RREF 32 k RAIN Analog Input Resistance 100 M ADC Output 0 1023 LSBATtiny25/45/85 [DATASHEET] 168 2586Q–AVR–08/2013 Note: 1. Values are guidelines only. Table 21-9. ADC Characteristics, Differential Channels (Unipolar Mode). TA = -40C to +85C Symbol Parameter Condition Min Typ Max Units Resolution Gain = 1x 10 Bits Gain = 20x 10 Bits Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 10.0 LSB Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 20.0 LSB Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 4.0 LSB Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 10.0 LSB Gain Error Gain = 1x 10.0 LSB Gain = 20x 15.0 LSB Offset Error Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 3.0 LSB Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 4.0 LSB Conversion Time Free Running Conversion 70 280 µs Clock Frequency 50 200 kHz VIN Input Voltage GND VCC V VDIFF Input Differential Voltage VREF/Gain V Input Bandwidth 4 kHz AREF External Reference Voltage 2.0 VCC - 1.0 V VINT Internal Voltage Reference 1.0 1.1 1.2 V Internal 2.56V Reference (1) VCC > 3.0V 2.3 2.56 2.8 V RREF Reference Input Resistance 32 k RAIN Analog Input Resistance 100 M ADC Conversion Output 0 1023 LSBATtiny25/45/85 [DATASHEET] 169 2586Q–AVR–08/2013 Note: 1. Values are guidelines only. Table 21-10. ADC Characteristics, Differential Channels (Bipolar Mode). TA = -40C to +85C Symbol Parameter Condition Min Typ Max Units Resolution Gain = 1x 10 Bits Gain = 20x 10 Bits Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 8.0 LSB Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 8.0 LSB Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 4.0 LSB Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 5.0 LSB Gain Error Gain = 1x 4.0 LSB Gain = 20x 5.0 LSB Offset Error Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 3.0 LSB Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 4.0 LSB Conversion Time Free Running Conversion 70 280 µs Clock Frequency 50 200 kHz VIN Input Voltage GND VCC V VDIFF Input Differential Voltage VREF/Gain V Input Bandwidth 4 kHz AREF External Reference Voltage 2.0 VCC - 1.0 V VINT Internal Voltage Reference 1.0 1.1 1.2 V Internal 2.56V Reference (1) VCC > 3.0V 2.3 2.56 2.8 V RREF Reference Input Resistance 32 k RAIN Analog Input Resistance 100 M ADC Conversion Output -512 511 LSBATtiny25/45/85 [DATASHEET] 170 2586Q–AVR–08/2013 21.8 Serial Programming Characteristics Figure 21-4. Serial Programming Waveforms Figure 21-5. Serial Programming Timing Note: 1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz Table 21-11. Serial Programming Characteristics, TA = -40C to +85C, VCC = 1.8 - 5.5V (Unless Otherwise Noted) Symbol Parameter Min Typ Max Units 1/tCLCL Oscillator Frequency (VCC = 1.8 - 5.5V) 0 4 MHz tCLCL Oscillator Period (VCC = 1.8 - 5.5V) 250 ns 1/tCLCL Oscillator Frequency (VCC = 2.7 - 5.5V) 0 10 MHz t CLCL Oscillator Period (VCC = 2.7 - 5.5V) 100 ns 1/tCLCL Oscillator Frequency (VCC = 4.5V - 5.5V) 0 20 MHz t CLCL Oscillator Period (VCC = 4.5V - 5.5V) 50 ns t SHSL SCK Pulse Width High 2 tCLCL* ns t SLSH SCK Pulse Width Low 2 tCLCL* ns t OVSH MOSI Setup to SCK High tCLCL ns t SHOX MOSI Hold after SCK High 2 tCLCL ns tSLIV SCK Low to MISO Valid 100 ns MSB MSB LSB LSB SERIAL CLOCK INPUT (SCK) SERIAL DATA INPUT (MOSI) (MISO) SAMPLE SERIAL DATA OUTPUT MOSI MISO SCK t OVSH t SHSL t t SHOX SLSH t SLIVATtiny25/45/85 [DATASHEET] 171 2586Q–AVR–08/2013 21.9 High-voltage Serial Programming Characteristics Figure 21-6. High-voltage Serial Programming Timing Table 21-12. High-voltage Serial Programming Characteristics TA = 25C ± 10%, VCC = 5.0V ± 10% (Unless otherwise noted) Symbol Parameter Min Typ Max Units tSHSL SCI (PB3) Pulse Width High 125 ns tSLSH SCI (PB3) Pulse Width Low 125 ns tIVSH SDI (PB0), SII (PB1) Valid to SCI (PB3) High 50 ns t SHIX SDI (PB0), SII (PB1) Hold after SCI (PB3) High 50 ns t SHOV SCI (PB3) High to SDO (PB2) Valid 16 ns tWLWH_PFB Wait after Instr. 3 for Write Fuse Bits 2.5 ms SDI (PB0), SII (PB1) SDO (PB2) SCI (PB3) t IVSH t SHSL t t SHIX SLSH t SHOVATtiny25/45/85 [DATASHEET] 172 2586Q–AVR–08/2013 22. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 22.1 Active Supply Current Figure 22-1. Active Supply Current vs. Low frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 -1.0 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0,2 0,4 0,6 0,8 1 1,2 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) ICC (mA)ATtiny25/45/85 [DATASHEET] 173 2586Q–AVR–08/2013 Figure 22-2. Active Supply Current vs. Frequency (1 - 20 MHz) Figure 22-3. Active Supply Current vs. VCC (Internal RC oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 5.5 V 5.0 V 4.5 V 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) ICC (mA) 1.8V 2.7V 3.3V 4.0V ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 85 ˚C 25 ˚C -40 ˚C 0 1 2 3 4 5 6 7 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA)ATtiny25/45/85 [DATASHEET] 174 2586Q–AVR–08/2013 Figure 22-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) Figure 22-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 85 ˚C 25 ˚C -40 ˚C 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 128 KHz 85 ˚C 25 ˚C -40 ˚C 0 0,05 0,1 0,15 0,2 0,25 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA)ATtiny25/45/85 [DATASHEET] 175 2586Q–AVR–08/2013 22.2 Idle Supply Current Figure 22-6. Idle Supply Current vs. low Frequency (0.1 - 1.0 MHz) Figure 22-7. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0,05 0,1 0,15 0,2 0,25 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) ICC (mA) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 5.5 V 5.0 V 4.5 V 0 0,5 1 1,5 2 2,5 3 3,5 4 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) ICC (mA) 1.8V 2.7V 3.3V 4.0VATtiny25/45/85 [DATASHEET] 176 2586Q–AVR–08/2013 Figure 22-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)I Figure 22-9. Idle Supply Current vs. VCC (Internal RC Oscilllator, 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 85 ˚C 25 ˚C -40 ˚C 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 85 ˚C 25 ˚C -40 ˚C 0 0,05 0,1 0,15 0,2 0,25 0,3 0,35 0,4 0,45 0,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA)ATtiny25/45/85 [DATASHEET] 177 2586Q–AVR–08/2013 Figure 22-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 22.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See “PRR – Power Reduction Register” on page 38 for details. It is possible to calculate the typical current consumption based on the numbers from Table 22-2 for other VCC and frequency settings that listed in Table 22-1. IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 128 kHz 85 ˚C 25 ˚C -40 ˚C 0 0,01 0,02 0,03 0,04 0,05 0,06 0,07 0,08 0,09 0,1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA) Table 22-1. Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers VCC = 2V, f = 1 MHz VCC = 3V, f = 4 MHz VCC = 5V, f = 8 MHz PRTIM1 45 uA 300 uA 1100 uA PRTIM0 5 uA 30 uA 110 uA PRUSI 5 uA 25 uA 100 uA PRADC 15 uA 85 uA 340 uA Table 22-2. Additional Current Consumption (percentage) in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock (see Figure 22-1 and Figure 22-2) Additional Current consumption compared to Idle with external clock (see Figure 22-6 and Figure 22-7) PRTIM1 20 % 80 % PRTIM0 2 % 10 % PRUSI 2 % 10 % PRADC 5 % 25 %ATtiny25/45/85 [DATASHEET] 178 2586Q–AVR–08/2013 22.3.1 Example Calculate the expected current consumption in idle mode with USI, TIMER0, and ADC enabled at VCC = 2.0V and f = 1 MHz. From Table 22-2 on page 177, third column, we see that we need to add 10% for the USI, 25% for the ADC, and 10% for the TIMER0 module. Reading from Figure 22-9, we find that the idle current consumption is ~0,18 mA at VCC = 2.0V and f = 1 MHz. The total current consumption in idle mode with USI, TIMER0, and ADC enabled, gives: 22.4 Power-down Supply Current Figure 22-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) ICC = 0 18 , mA 1 01 ++ + , 0 25 , 0 1, 0 261 , mA POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 85 ˚C 25 ˚C -40 ˚C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA)ATtiny25/45/85 [DATASHEET] 179 2586Q–AVR–08/2013 Figure 22-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 22.5 Pin Pull-up Figure 22-13. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 85 ˚C 25 ˚C -40 ˚C 0 2 4 6 8 10 12 14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 1.8V 85 ˚C 25 ˚C 0 -40 ˚C 10 20 30 40 50 60 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOP (V) IOP (uA)ATtiny25/45/85 [DATASHEET] 180 2586Q–AVR–08/2013 Figure 22-14. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) Figure 22-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 85 ˚C 25 ˚C -40 ˚C 0 10 20 30 40 50 60 70 80 0 0,5 1 1,5 2 2,5 3 VOP (V) IOP (uA) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 5V 85 ˚C 25 ˚C -40 ˚C 0 20 40 60 80 100 120 140 160 0123456 VOP (V) IOP (uA)ATtiny25/45/85 [DATASHEET] 181 2586Q–AVR–08/2013 Figure 22-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) Figure 22-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 1.8V 85 ˚C 25 ˚C -40 ˚C 0 5 10 15 20 25 30 35 40 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VRESET (V) IRESET (uA) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC =2.7V 85 ˚C 25 ˚C -40 ˚C 0 10 20 30 40 50 60 0 0,5 1 1,5 2 2,5 3 VRESET (V) IRESET (uA)ATtiny25/45/85 [DATASHEET] 182 2586Q–AVR–08/2013 Figure 22-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 22.6 Pin Driver Strength Figure 22-19. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 5V 85 ˚C 25 ˚C -40 ˚C 0 20 40 60 80 100 120 0123456 VRESET (V) IRESET (uA) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 85 25 -40 0 0,2 0,4 0,6 0,8 1 1,2 0 5 10 15 20 25 IOL (mA) VOL (V)ATtiny25/45/85 [DATASHEET] 183 2586Q–AVR–08/2013 Figure 22-20. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) Figure 22-21. I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 85 25 -40 0 0,1 0,2 0,3 0,4 0,5 0,6 0 5 10 15 20 25 IOL (mA) VOL (V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 85 25 -40 0 0,5 1 1,5 2 2,5 3 3,5 0 5 10 15 20 25 IOH (mA) VOH (V)ATtiny25/45/85 [DATASHEET] 184 2586Q–AVR–08/2013 Figure 22-22. I/O Pin Output Voltage vs. Source Current (VCC = 5V) Figure 22-23. Reset Pin Output Voltage vs. Sink Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 85 25 -40 4,4 4,5 4,6 4,7 4,8 4,9 5 5,1 0 5 10 15 20 25 IOH (mA) VOH (V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V -45 °C 0 °C 85 °C 0 0.5 1 1.5 0 0.5 1 1.5 2 2.5 3 IOL (mA) VOL (V)ATtiny25/45/85 [DATASHEET] 185 2586Q–AVR–08/2013 Figure 22-24. Reset Pin Output Voltage vs. Sink Current (VCC = 5V) Figure 22-25. Reset Pin Output Voltage vs. Source Current (VCC = 3V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V -45 °C 0 °C 85 °C 0 0.2 0.4 0.6 0.8 1 0 0.5 1 1.5 2 2.5 3 IOL (mA) VOL (V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V -45 °C 25 °C 85 °C 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 IOH (mA) VOH (V)ATtiny25/45/85 [DATASHEET] 186 2586Q–AVR–08/2013 Figure 22-26. Reset Pin Output Voltage vs. Source Current (VCC = 5V) 22.7 Pin Threshold and Hysteresis Figure 22-27. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V -45 °C 25 °C 2.5 85 °C 3 3.5 4 4.5 5 0 0.5 1 1.5 2 IOH (mA) VOH (V) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 85 ˚C 25 ˚C -40 ˚C 0 0,5 1 1,5 2 2,5 3 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V)ATtiny25/45/85 [DATASHEET] 187 2586Q–AVR–08/2013 Figure 22-28. I/O Pin Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’) Figure 22-29. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 85 ˚C 25 ˚C -40 ˚C 0 0,5 1 1,5 2 2,5 3 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V) 85 °C 25 °C -40 °C 0 0,1 0,2 0,3 0,4 0,5 0,6 1,5 2 2,5 3 3,5 4 4,5 5 5,5 Input Hysteresis (V) V CC (V) I/O PIN INPUT HYSTERESIS vs. VCCATtiny25/45/85 [DATASHEET] 188 2586Q–AVR–08/2013 Figure 22-30. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’) Figure 22-31. Reset Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 85 °C 25 °C -40 °C 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 85 °C 25 °C -40 °C 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V)ATtiny25/45/85 [DATASHEET] 189 2586Q–AVR–08/2013 Figure 22-32. Reset Pin Input Hysteresis vs. VCC 22.8 BOD Threshold Figure 22-33. BOD Threshold vs. Temperature (BOD Level is 4.3V) RESET PIN INPUT HYSTERESIS vs. VCC 85 °C 25 °C -40 °C 0 0,05 0,1 0,15 0,2 0,25 0,3 0,35 0,4 0,45 0,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Input Hysteresis (V) BOD THRESHOLDS vs. TEMPERATURE Rising VCC Falling VCC 4,26 4,28 4,3 4,32 4,34 4,36 4,38 4,4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) Threshold (V)ATtiny25/45/85 [DATASHEET] 190 2586Q–AVR–08/2013 Figure 22-34. BOD Threshold vs. Temperature (BOD Level is 2.7V) Figure 22-35. BOD Threshold vs. Temperature (BOD Level is 1.8V) BOD THRESHOLDS vs. TEMPERATURE Rising VCC Falling VCC 2,68 2,7 2,72 2,74 2,76 2,78 2,8 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) Threshold (V) BOD THRESHOLDS vs. TEMPERATURE Rising VCC Falling VCC 1,795 1,8 1,805 1,81 1,815 1,82 1,825 1,83 1,835 1,84 1,845 1,85 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) Threshold (V)ATtiny25/45/85 [DATASHEET] 191 2586Q–AVR–08/2013 Figure 22-36. Bandgap Voltage vs. Supply Voltage Figure 22-37. Bandgap Voltage vs. Temperature BANDGAP VOLTAGE vs. VCC 85 °C 25 °C -40 °C 1 1,02 1,04 1,06 1,08 1,1 1,12 1,14 1,16 1,18 1,2 1,5 2 2,5 3 3,5 4 4,5 5 5,5 Vcc (V) Bandgap Voltage (V) BANDGAP VOLTAGE vs. Temperature 5 V 3 V 1.8 V 1 1,02 1,04 1,06 1,08 1,1 1,12 1,14 1,16 1,18 1,2 -40 -20 0 20 40 60 80 100 Temperature Bandgap Voltage (V)ATtiny25/45/85 [DATASHEET] 192 2586Q–AVR–08/2013 22.9 Internal Oscillator Speed Figure 22-38. Watchdog Oscillator Frequency vs. VCC Figure 22-39. Watchdog Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. VCC 85 ˚C 25 ˚C -40 ˚C 0,112 0,114 0,116 0,118 0,12 0,122 0,124 0,126 0,128 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) FRC (MHz) WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 5.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0,108 0,11 0,112 0,114 0,116 0,118 0,12 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature FRC (MHz)ATtiny25/45/85 [DATASHEET] 193 2586Q–AVR–08/2013 Figure 22-40. Calibrated 8 MHz RC Oscillator Frequency vs. VCC Figure 22-41. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. VCC 85 ˚C 25 ˚C -40 ˚C 7,5 7,6 7,7 7,8 7,9 8 8,1 8,2 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) FRC (MHz) CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.0 V 3.0 V 7,7 7,75 7,8 7,85 7,9 7,95 8 8,05 8,1 8,15 -60 -40 -20 0 20 40 60 80 100 Temperature FRC (MHz)ATtiny25/45/85 [DATASHEET] 194 2586Q–AVR–08/2013 Figure 22-42. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value Figure 22-43. Calibrated 1.6 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 85 ˚C 25 ˚C -40 ˚C 0 2 4 6 8 10 12 14 16 18 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) FRC (MHz) CALIBRATED 1.6 MHz RC OSCILLATOR FREQUENCY vs. VCC 85 ˚C 25 ˚C -40 ˚C 1,4 1,45 1,5 1,55 1,6 1,65 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) FRC (MHz)ATtiny25/45/85 [DATASHEET] 195 2586Q–AVR–08/2013 Figure 22-44. Calibrated 1.6 MHz RC Oscillator Frequency vs. Temperature Figure 22-45. Calibrated 1.6 MHz RC Oscillator Frequency vs. OSCCAL Value CALIBRATED 1.6MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.0 V 3.0 V 1,5 1,52 1,54 1,56 1,58 1,6 1,62 1,64 -60 -40 -20 0 20 40 60 80 100 Temperature FRC (MHz) CALIBRATED 1.6 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 85 ˚C 25 ˚C -40 ˚C 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) FRC (MHz)ATtiny25/45/85 [DATASHEET] 196 2586Q–AVR–08/2013 22.10 Current Consumption of Peripheral Units Figure 22-46. Brownout Detector Current vs. VCC Figure 22-47. ADC Current vs. VCC (AREF = AVCC) BROWNOUT DETECTOR CURRENT vs. VCC 85 °C 25 °C -40 °C 0 5 10 15 20 25 30 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (uA) ADC CURRENT vs. VCC AREF = AVCC 85 °C 25 °C -40 °C 0 50 100 150 200 250 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (uA)ATtiny25/45/85 [DATASHEET] 197 2586Q–AVR–08/2013 Figure 22-48. Analog Comparator Current vs. VCC Figure 22-49. Programming Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 85 °C 25 °C -40 °C 0 5 10 15 20 25 30 35 40 45 50 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (uA) PROGRAMMING CURRENT vs. Vcc Ext Clk 85 °C 25 °C -40 °C 0 2 4 6 8 10 12 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA)ATtiny25/45/85 [DATASHEET] 198 2586Q–AVR–08/2013 22.11 Current Consumption in Reset and Reset Pulsewidth Figure 22-50. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) Figure 22-51. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. VCC 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0,02 0,04 0,06 0,08 0,1 0,12 0,14 0,16 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) ICC (mA) RESET SUPPLY CURRENT vs. VCC 1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5 V 5.0 V 4.5 V 0 0,5 1 1,5 2 2,5 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) ICC (mA) 1.8V 2.7V 3.3V 4.0VATtiny25/45/85 [DATASHEET] 199 2586Q–AVR–08/2013 Figure 22-52. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs. VCC 85 ˚C 25 ˚C -40 ˚C 0 500 1000 1500 2000 2500 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Pulsewidth (ns)ATtiny25/45/85 [DATASHEET] 200 2586Q–AVR–08/2013 23. Register Summary Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F SREG I T H S V N Z C page 8 0x3E SPH – – – – – – SP9 SP8 page 11 0x3D SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 11 0x3C Reserved – 0x3B GIMSK – INT0 PCIE – – – – – page 51 0x3A GIFR – INTF0 PCIF – – – – – page 52 0x39 TIMSK – OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 – pages 81, 102 0x38 TIFR – OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 – page 81 0x37 SPMCSR – – RSIG CTPB RFLB PGWRT PGERS SPMEN page 145 0x36 Reserved – 0x35 MCUCR BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 pages 37, 51, 64 0x34 MCUSR – – – – WDRF BORF EXTRF PORF page 44, 0x33 TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 page 79 0x32 TCNT0 Timer/Counter0 page 80 0x31 OSCCAL Oscillator Calibration Register page 31 0x30 TCCR1 CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 pages 89, 100 0x2F TCNT1 Timer/Counter1 pages 91, 102 0x2E OCR1A Timer/Counter1 Output Compare Register A pages 91, 102 0x2D OCR1C Timer/Counter1 Output Compare Register C pages 91, 102 0x2C GTCCR TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 pages 77, 90, 101 0x2B OCR1B Timer/Counter1 Output Compare Register B page 92 0x2A TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – WGM01 WGM00 page 77 0x29 OCR0A Timer/Counter0 – Output Compare Register A page 80 0x28 OCR0B Timer/Counter0 – Output Compare Register B page 81 0x27 PLLCSR LSM – – – – PCKE PLLE PLOCK pages 94, 103 0x26 CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 32 0x25 DT1A DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 page 107 0x24 DT1B DT1BH3 DT1BH2 DT1BH1 DT1BH0 DT1BL3 DT1BL2 DT1BL1 DT1BL0 page 107 0x23 DTPS1 - - - - - - DTPS11 DTPS10 page 106 0x22 DWDR DWDR[7:0] page 140 0x21 WDTCR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 page 45 0x20 PRR – PRTIM1 PRTIM0 PRUSI PRADC page 36 0x1F EEARH EEAR8 page 20 0x1E EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 page 21 0x1D EEDR EEPROM Data Register page 21 0x1C EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE page 21 0x1B Reserved – 0x1A Reserved – 0x19 Reserved – 0x18 PORTB – – PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 64 0x17 DDRB – – DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 64 0x16 PINB – – PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 64 0x15 PCMSK – – PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 page 52 0x14 DIDR0 – – ADC0D ADC2D ADC3D ADC1D AIN1D AIN0D pages 121, 138 0x13 GPIOR2 General Purpose I/O Register 2 page 10 0x12 GPIOR1 General Purpose I/O Register 1 page 10 0x11 GPIOR0 General Purpose I/O Register 0 page 10 0x10 USIBR USI Buffer Register page 115 0x0F USIDR USI Data Register page 115 0x0E USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 page 115 0x0D USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC page 116 0x0C Reserved – 0x0B Reserved – 0x0A Reserved – 0x09 Reserved – 0x08 ACSR ACD ACBG ACO ACI ACIE – ACIS1 ACIS0 page 120 0x07 ADMUX REFS1 REFS0 ADLAR REFS2 MUX3 MUX2 MUX1 MUX0 page 134 0x06 ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 136 0x05 ADCH ADC Data Register High Byte page 137 0x04 ADCL ADC Data Register Low Byte page 137 0x03 ADCSRB BIN ACME IPR – – ADTS2 ADTS1 ADTS0 pages 120, 137 0x02 Reserved – 0x01 Reserved – 0x00 Reserved –ATtiny25/45/85 [DATASHEET] 201 2586Q–AVR–08/2013 should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.ATtiny25/45/85 [DATASHEET] 202 2586Q–AVR–08/2013 24. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd Rd Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd Rd K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1 COM Rd One’s Complement Rd 0xFF Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd 0x00 Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd Rd (0xFF - K) Z,N,V 1 INC Rd Increment Rd Rd + 1 Z,N,V 1 DEC Rd Decrement Rd Rd 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd Rd Rd Z,N,V 1 CLR Rd Clear Register Rd Rd Rd Z,N,V 1 SER Rd Set Register Rd 0xFF None 1 BRANCH INSTRUCTIONS RJMP k Relative Jump PC PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC Z None 2 RCALL k Relative Subroutine Call PC PC + k + 1 None 3 ICALL Indirect Call to (Z) PC Z None 3 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd Rr C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1ATtiny25/45/85 [DATASHEET] 203 2586Q–AVR–08/2013 SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1 BSET s Flag Set SREG(s) 1 SREG(s) 1 BCLR s Flag Clear SREG(s) 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) T None 1 SEC Set Carry C 1 C1 CLC Clear Carry C 0 C 1 SEN Set Negative Flag N 1 N1 CLN Clear Negative Flag N 0 N 1 SEZ Set Zero Flag Z 1 Z1 CLZ Clear Zero Flag Z 0 Z 1 SEI Global Interrupt Enable I 1 I1 CLI Global Interrupt Disable I 0 I 1 SES Set Signed Test Flag S 1 S1 CLS Clear Signed Test Flag S 0 S 1 SEV Set Twos Complement Overflow. V 1 V1 CLV Clear Twos Complement Overflow V 0 V 1 SET Set T in SREG T 1 T1 CLT Clear T in SREG T 0 T 1 SEH Set Half Carry Flag in SREG H 1 H1 CLH Clear Half Carry Flag in SREG H 0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd K None 1 LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2 LD Rd, Y Load Indirect Rd (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2 LD Rd, Z Load Indirect Rd (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2 ST Y, Rr Store Indirect (Y) Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2 ST Z, Rr Store Indirect (Z) Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2 STS k, Rr Store Direct to SRAM (k) Rr None 2 LPM Load Program Memory R0 (Z) None 3 LPM Rd, Z Load Program Memory Rd (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3 SPM Store Program Memory (z) R1:R0 None IN Rd, P In Port Rd P None 1 OUT P, Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1 BREAK Break For On-chip Debug Only None N/A Mnemonics Operands Description Operation Flags #ClocksATtiny25/45/85 [DATASHEET] 204 2586Q–AVR–08/2013 25. Ordering Information Notes: 1. For speed vs. supply voltage, see section 21.3 “Speed” on page 163. 2. All Pb-free, halide-free, fully green, and comply with European directive for Restriction of Hazardous Substances (RoHS). 3. Code indicators: H = NiPdAu lead finish, U/N = matte tin, R = tape & reel. 4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities. 5. For characteristics, see “Appendix A – Specification at 105C”. 6. For characteristics, see “Appendix B – Specification at 125C”. 25.1 ATtiny25 Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3) 10 1.8 – 5.5 Industrial (-40C to +85C) (4) 8P3 ATtiny25V-10PU 8S2 ATtiny25V-10SU ATtiny25V-10SUR ATtiny25V-10SH ATtiny25V-10SHR S8S1 ATtiny25V-10SSU ATtiny25V-10SSUR ATtiny25V-10SSH ATtiny25V-10SSHR 20M1 ATtiny25V-10MU ATtiny25V-10MUR Industrial (-40C to +105C) (5) 8S2 ATtiny25V-10SN ATtiny25V-10SNR S8S1 ATtiny25V-10SSN ATtiny25V-10SSNR Industrial (-40C to +125C) (6) 20M1 ATtiny25V-10MF ATtiny25V-10MFR 20 2.7 – 5.5 Industrial (-40C to +85C) (4) 8P3 ATtiny25-20PU 8S2 ATtiny25-20SU ATtiny25-20SUR ATtiny25-20SH ATtiny25-20SHR S8S1 ATtiny25-20SSU ATtiny25-20SSUR ATtiny25-20SSH ATtiny25-20SSHR 20M1 ATtiny25-20MU ATtiny25-20MUR Industrial (-40C to +105C) (5) 8S2 ATtiny25-20SN ATtiny25-20SNR S8S1 ATtiny25-20SSN ATtiny25-20SSNR Industrial (-40C to +125C) (6) 20M1 ATtiny25-20MF ATtiny25-20MFR Package Types 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.208" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) S8S1 8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC) 20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)ATtiny25/45/85 [DATASHEET] 205 2586Q–AVR–08/2013 Notes: 1. For speed vs. supply voltage, see section 21.3 “Speed” on page 163. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). 3. Code indicators: – H: NiPdAu lead finish – U: matte tin – R: tape & reel 4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 25.2 ATtiny45 Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3) 10 1.8 – 5.5 Industrial (-40C to +85C) (4) 8P3 ATtiny45V-10PU 8S2 ATtiny45V-10SU ATtiny45V-10SUR ATtiny45V-10SH ATtiny45V-10SHR 8X ATtiny45V-10XU ATtiny45V-10XUR 20M1 ATtiny45V-10MU ATtiny45V-10MUR 20 2.7 – 5.5 Industrial (-40C to +85C) (4) 8P3 ATtiny45-20PU 8S2 ATtiny45-20SU ATtiny45-20SUR ATtiny45-20SH ATtiny45-20SHR 8X ATtiny45-20XU ATtiny45-20XUR 20M1 ATtiny45-20MU ATtiny45-20MUR Package Types 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.208" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) 8X 8-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline Package (TSSOP) 20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)ATtiny25/45/85 [DATASHEET] 206 2586Q–AVR–08/2013 Notes: 1. For speed vs. supply voltage, see section 21.3 “Speed” on page 163. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). 3. Code indicators: – H: NiPdAu lead finish – U: matte tin – R: tape & reel 4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 25.3 ATtiny85 Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3) 10 1.8 – 5.5 Industrial (-40C to +85C) (4) 8P3 ATtiny85V-10PU 8S2 ATtiny85V-10SU ATtiny85V-10SUR ATtiny85V-10SH ATtiny85V-10SHR 20M1 ATtiny85V-10MU ATtiny85V-10MUR 20 2.7 – 5.5 Industrial (-40C to +85C) (4) 8P3 ATtiny85-20PU 8S2 ATtiny85-20SU ATtiny85-20SUR ATtiny85-20SH ATtiny85-20SHR 20M1 ATtiny85-20MU ATtiny85-20MUR Package Types 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.208" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) 20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)ATtiny25/45/85 [DATASHEET] 207 2586Q–AVR–08/2013 26. Packaging Information 26.1 8P3 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B D D1 E E1 e b2 L b A2 A 1 N eA c b3 4 PLCS Top View Side View End View COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). A 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC 4 L 0.115 0.130 0.150 2ATtiny25/45/85 [DATASHEET] 208 2586Q–AVR–08/2013 26.2 8S2 TITLE GPC DRAWING NO. REV. Package Drawing Contact: packagedrawings@atmel.com STN F 8S2 8S2, 8-lead, 0.208” Body, Plastic Small Outline Package (EIAJ) 4/15/08 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. A 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 2 E 7.70 8.26 L 0.51 0.85 θ 0° 8° e 1.27 BSC 3 θ 1 N E TOP VIEW TOP VIEW C E1 END VIEW END VIEW A b L A1 e D SIDE VIEW SIDE VIEWATtiny25/45/85 [DATASHEET] 209 2586Q–AVR–08/2013 26.3 S8S1 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. S8S1, 8-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline (JEDEC SOIC) 7/28/03 S8S1 A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc. E 5.79 6.20 E1 3.81 3.99 A 1.35 1.75 A1 0.1 0.25 D 4.80 4.98 C 0.17 0.25 b 0.31 0.51 L 0.4 1.27 e 1.27 BSC 0o 8o Top View Side View End View 1 N C A A1 b L e D E1 EATtiny25/45/85 [DATASHEET] 210 2586Q–AVR–08/2013 26.4 8X TITLE DRAWING NO. R REV. Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153AC. 2325 Orchard Parkway San Jose, CA 95131 4/14/05 8X, 8-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) 8X A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 1.05 1.10 1.20 A1 0.05 0.10 0.15 b 0.25 – 0.30 C – 0.127 – D 2.90 3.05 3.10 E1 4.30 4.40 4.50 E 6.20 6.40 6.60 e 0.65 TYP L 0.50 0.60 0.70 Ø 0o – 8o C A b L A1 D Side View Top View End View E 1 E1 e ØATtiny25/45/85 [DATASHEET] 211 2586Q–AVR–08/2013 26.5 20M1 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 20M1 B 10/27/04 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 0.20 REF b 0.18 0.23 0.30 D 4.00 BSC D2 2.45 2.60 2.75 E 4.00 BSC E2 2.45 2.60 2.75 e 0.50 BSC L 0.35 0.40 0.55 SIDE VIEW Pin 1 ID Pin #1 Notch (0.20 R) BOTTOM VIEW TOP VIEW Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D E e A2 A1 A D2 E2 0.08 C L 1 2 3 b 1 2 3ATtiny25/45/85 [DATASHEET] 212 2586Q–AVR–08/2013 27. Errata 27.1 Errata ATtiny25 The revision letter in this section refers to the revision of the ATtiny25 device. 27.1.1 Rev D – F No known errata. 27.1.2 Rev B – C • EEPROM read may fail at low supply voltage / low clock frequency 1. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data. Problem Fix/Workaround Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage can not be raised above 2V then operating frequency should be more than 1MHz. This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for room temperature, only. 27.1.3 Rev A Not sampled. 27.2 Errata ATtiny45 The revision letter in this section refers to the revision of the ATtiny45 device. 27.2.1 Rev F – G No known errata 27.2.2 Rev D – E • EEPROM read may fail at low supply voltage / low clock frequency 1. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data. Problem Fix/Workaround Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage can not be raised above 2V then operating frequency should be more than 1MHz. This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for room temperature, only.ATtiny25/45/85 [DATASHEET] 213 2586Q–AVR–08/2013 27.2.3 Rev B – C • PLL not locking • EEPROM read from application code does not work in Lock Bit Mode 3 • EEPROM read may fail at low supply voltage / low clock frequency • Timer Counter 1 PWM output generation on OC1B- XOC1B does not work correctly 1. PLL not locking When at frequencies below 6.0 MHz, the PLL will not lock Problem fix / Workaround When using the PLL, run at 6.0 MHz or higher. 2. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Work around Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 3. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data. Problem Fix/Workaround Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage can not be raised above 2V then operating frequency should be more than 1MHz. This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for room temperature, only. 4. Timer Counter 1 PWM output generation on OC1B – XOC1B does not work correctly Timer Counter1 PWM output OC1B-XOC1B does not work correctly. Only in the case when the control bits, COM1B1 and COM1B0 are in the same mode as COM1A1 and COM1A0, respectively, the OC1B-XOC1B output works correctly. Problem Fix/Work around The only workaround is to use same control setting on COM1A[1:0] and COM1B[1:0] control bits, see table 14- 4 in the data sheet. The problem has been fixed for Tiny45 rev D. 27.2.4 Rev A • Too high power down power consumption • DebugWIRE looses communication when single stepping into interrupts • PLL not locking • EEPROM read from application code does not work in Lock Bit Mode 3 • EEPROM read may fail at low supply voltage / low clock frequency 1. Too high power down power consumption Three situations will lead to a too high power down power consumption. These are: – An external clock is selected by fuses, but the I/O PORT is still enabled as an output. – The EEPROM is read before entering power down. – VCC is 4.5 volts or higher. Problem fix / WorkaroundATtiny25/45/85 [DATASHEET] 214 2586Q–AVR–08/2013 – When using external clock, avoid setting the clock pin as Output. – Do not read the EEPROM if power down power consumption is important. – Use VCC lower than 4.5 Volts. 2. DebugWIRE looses communication when single stepping into interrupts When receiving an interrupt during single stepping, debugwire will loose communication. Problem fix / Workaround – When singlestepping, disable interrupts. – When debugging interrupts, use breakpoints within the interrupt routine, and run into the interrupt. 3. PLL not locking When at frequencies below 6.0 MHz, the PLL will not lock Problem fix / Workaround When using the PLL, run at 6.0 MHz or higher. 4. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Work around Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 5. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data. Problem Fix/Workaround Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage can not be raised above 2V then operating frequency should be more than 1MHz. This feature is known to be temperature dependent but it has not been characterized. Guidelines are given for room temperature, only.ATtiny25/45/85 [DATASHEET] 215 2586Q–AVR–08/2013 27.3 Errata ATtiny85 The revision letter in this section refers to the revision of the ATtiny85 device. 27.3.1 Rev B – C No known errata. 27.3.2 Rev A • EEPROM read may fail at low supply voltage / low clock frequency 1. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data. Problem Fix/Workaround Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage can not be raised above 2V then operating frequency should be more than 1MHz. This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for room temperature, only.ATtiny25/45/85 [DATASHEET] 216 2586Q–AVR–08/2013 28. Datasheet Revision History 28.1 Rev. 2586Q-08/13 28.2 Rev. 2586P-06/13 28.3 Rev. 2586O-02/13 Updated ordering codes on page 204, page 205, and page 206. 28.4 Rev. 2586N-04/11 1. Added: – Section “Capacitive Touch Sensing” on page 6. 2. Updated: – Document template. – Removed “Preliminary” on front page. All devices now final and in production. – Section “Limitations” on page 36. – Program example on page 49. – Section “Overview” on page 122. – Table 17-4 on page 135. – Section “Limitations of debugWIRE” on page 140. – Section “Serial Programming Algorithm” on page 151. – Table 21-7 on page 166. – EEPROM errata on pages 212, 212, 213, 214, and 215 – Ordering information on pages 204, 205, and 206. 28.5 Rev. 2586M-07/10 1. Clarified Section 6.4 “Clock Output Buffer” on page 31. 2. Added Ordering Codes -SN and -SNR for ATtiny25 extended temperature. 28.6 Rev. 2586L-06/10 1. Added: – TSSOP for ATtiny45 in “Features” on page 1, Pinout Figure 1-1 on page 2, Ordering Information in Section 25.2 “ATtiny45” on page 205, and Packaging Information in Section 26.4 “8X” on page 210 – Table 6-11, “Capacitance of Low-Frequency Crystal Oscillator,” on page 29 – Figure 22-36 on page 191 and Figure 22-37 on page 191, Typical Characteristics plots for Bandgap Voltage vs. VCC and Temperature – Extended temperature in Section 25.1 “ATtiny25” on page 204, Ordering Information – Tape & reel part numbers in Ordering Information, in Section 25.1 “ATtiny25” on page 204 and Section 25.2 “ATtiny45” on page 205 1. “Bit 3 – FOC1B: Force Output Compare Match 1B” description in “GTCCR – General Timer/Counter1 Control Register” on page 90 updated: PB3 in “compare match output pin PB3 (OC1B)” corrected to PB4. 1. Updated description of “EEARH – EEPROM Address Register” and “EEARL – EEPROM Address Register” on page 20.ATtiny25/45/85 [DATASHEET] 217 2586Q–AVR–08/2013 2. Updated: – “Features” on page 1, removed Preliminary from ATtiny25 – Section 8.4.2 “Code Example” on page 44 – “PCMSK – Pin Change Mask Register” on page 52, Bit Descriptions – “TCCR1 – Timer/Counter1 Control Register” on page 89 and “GTCCR – General Timer/Counter1 Control Register” on page 90, COM bit descriptions clarified – Section 20.3.2 “Calibration Bytes” on page 150, frequencies (8 MHz, 6.4 MHz) – Table 20-11, “Minimum Wait Delay Before Writing the Next Flash or EEPROM Location,” on page 153, value for tWD_ERASE – Table 20-16, “High-voltage Serial Programming Instruction Set for ATtiny25/45/85,” on page 158 – Table 21-1, “DC Characteristics. TA = -40°C to +85°C,” on page 161, notes adjusted – Table 21-11, “Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V (Unless Otherwise Noted),” on page 170, added tSLIV – Bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0]. 28.7 Rev. 2586K-01/08 1. Updated Document Template. 2. Added Sections: – “Data Retention” on page 6 – “Low Level Interrupt” on page 49 – “Device Signature Imprint Table” on page 149 3. Updated Sections: – “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24 – “System Clock and Clock Options” on page 23 – “Internal PLL in ATtiny15 Compatibility Mode” on page 24 – “Sleep Modes” on page 34 – “Software BOD Disable” on page 35 – “External Interrupts” on page 49 – “Timer/Counter1 in PWM Mode” on page 97 – “USI – Universal Serial Interface” on page 108 – “Temperature Measurement” on page 133 – “Reading Lock, Fuse and Signature Data from Software” on page 143 – “Program And Data Memory Lock Bits” on page 147 – “Fuse Bytes” on page 148 – “Signature Bytes” on page 150 – “Calibration Bytes” on page 150 – “System and Reset Characteristics” on page 165 4. Added Figures: – “Reset Pin Output Voltage vs. Sink Current (VCC = 3V)” on page 184 – “Reset Pin Output Voltage vs. Sink Current (VCC = 5V)” on page 185 – “Reset Pin Output Voltage vs. Source Current (VCC = 3V)” on page 185 – “Reset Pin Output Voltage vs. Source Current (VCC = 5V)” on page 186ATtiny25/45/85 [DATASHEET] 218 2586Q–AVR–08/2013 5. Updated Figure: – “Reset Logic” on page 39 6. Updated Tables: – “Start-up Times for Internal Calibrated RC Oscillator Clock” on page 28 – “Start-up Times for Internal Calibrated RC Oscillator Clock (in ATtiny15 Mode)” on page 28 – “Start-up Times for the 128 kHz Internal Oscillator” on page 28 – “Compare Mode Select in PWM Mode” on page 86 – “Compare Mode Select in PWM Mode” on page 98 – “DC Characteristics. TA = -40°C to +85°C” on page 161 – “Calibration Accuracy of Internal RC Oscillator” on page 164 – “ADC Characteristics” on page 167 7. Updated Code Example in Section: – “Write” on page 17 8. Updated Bit Descriptions in: – “MCUCR – MCU Control Register” on page 37 – “Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode” on page 77 – “Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode” on page 77 – “Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source” on page 138 – “SPMCSR – Store Program Memory Control and Status Register” on page 145. 9. Updated description of feature “EEPROM read may fail at low supply voltage / low clock frequency” in Sections: – “Errata ATtiny25” on page 212 – “Errata ATtiny45” on page 212 – “Errata ATtiny85” on page 215 10. Updated Package Description in Sections: – “ATtiny25” on page 204 – “ATtiny45” on page 205 – “ATtiny85” on page 206 11. Updated Package Drawing: – “S8S1” on page 209 12. Updated Order Codes for: – “ATtiny25” on page 204 28.8 Rev. 2586J-12/06 1. Updated “Low Power Consumption” on page 1. 2. Updated description of instruction length in “Architectural Overview” . 3. Updated Flash size in “In-System Re-programmable Flash Program Memory” on page 15. 4. Updated cross-references in sections “Atomic Byte Programming” , “Erase” and “Write” , starting on page 17. 5. Updated “Atomic Byte Programming” on page 17. 6. Updated “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24. 7. Replaced single clocking system figure with two: Figure 6-2 and Figure 6-3.ATtiny25/45/85 [DATASHEET] 219 2586Q–AVR–08/2013 8. Updated Table 6-1 on page 25, Table 6-13 on page 30 and Table 6-6 on page 27. 9. Updated “Calibrated Internal Oscillator” on page 27. 10. Updated Table 6-5 on page 26. 11. Updated “OSCCAL – Oscillator Calibration Register” on page 31. 12. Updated “CLKPR – Clock Prescale Register” on page 32. 13. Updated “Power-down Mode” on page 35. 14. Updated “Bit 0” in “PRR – Power Reduction Register” on page 38. 15. Added footnote to Table 8-3 on page 46. 16. Updated Table 10-5 on page 63. 17. Deleted “Bits 7, 2” in “MCUCR – MCU Control Register” on page 64. 18. Updated and moved section “Timer/Counter0 Prescaler and Clock Sources”, now located on page 66. 19. Updated “Timer/Counter1 Initialization for Asynchronous Mode” on page 86. 20. Updated bit description in “PLLCSR – PLL Control and Status Register” on page 94 and “PLLCSR – PLL Control and Status Register” on page 103. 21. Added recommended maximum frequency in“Prescaling and Conversion Timing” on page 125. 22. Updated Figure 17-8 on page 129 . 23. Updated “Temperature Measurement” on page 133. 24. Updated Table 17-3 on page 134. 25. Updated bit R/W descriptions in: “TIMSK – Timer/Counter Interrupt Mask Register” on page 81, “TIFR – Timer/Counter Interrupt Flag Register” on page 81, “TIMSK – Timer/Counter Interrupt Mask Register” on page 92, “TIFR – Timer/Counter Interrupt Flag Register” on page 93, “PLLCSR – PLL Control and Status Register” on page 94, “TIMSK – Timer/Counter Interrupt Mask Register” on page 102, “TIFR – Timer/Counter Interrupt Flag Register” on page 103, “PLLCSR – PLL Control and Status Register” on page 103 and “DIDR0 – Digital Input Disable Register 0” on page 138. 26. Added limitation to “Limitations of debugWIRE” on page 140. 27. Updated “DC Characteristics” on page 161. 28. Updated Table 21-7 on page 166. 29. Updated Figure 21-6 on page 171. 30. Updated Table 21-12 on page 171. 31. Updated Table 22-1 on page 177. 32. Updated Table 22-2 on page 177. 33. Updated Table 22-30, Table 22-31 and Table 22-32, starting on page 188. 34. Updated Table 22-33, Table 22-34 and Table 22-35, starting on page 189. 35. Updated Table 22-39 on page 192. 36. Updated Table 22-46, Table 22-47, Table 22-48 and Table 22-49.ATtiny25/45/85 [DATASHEET] 220 2586Q–AVR–08/2013 28.9 Rev. 2586I-09/06 28.10 Rev. 2586H-06/06 28.11 Rev. 2586G-05/06 28.12 Rev. 2586F-04/06 1. All Characterization data moved to “Electrical Characteristics” on page 161. 2. All Register Descriptions are gathered up in seperate sections in the end of each chapter. 3. Updated Table 11-3 on page 78, Table 11-5 on page 79, Table 11-6 on page 80 and Table 20-4 on page 148. 4. Updated “Calibrated Internal Oscillator” on page 27. 5. Updated Note in Table 7-1 on page 34. 6. Updated “System Control and Reset” on page 39. 7. Updated Register Description in “I/O Ports” on page 53. 8. Updated Features in “USI – Universal Serial Interface” on page 108. 9. Updated Code Example in “SPI Master Operation Example” on page 110 and “SPI Slave Operation Example” on page 111. 10. Updated “Analog Comparator Multiplexed Input” on page 119. 11. Updated Figure 17-1 on page 123. 12. Updated “Signature Bytes” on page 150. 13. Updated “Electrical Characteristics” on page 161. 1. Updated “Calibrated Internal Oscillator” on page 27. 2. Updated Table 6.5.1 on page 31. 3. Added Table 21-2 on page 164. 1. Updated “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24. 2. Updated “Default Clock Source” on page 30. 3. Updated “Low-Frequency Crystal Oscillator” on page 29. 4. Updated “Calibrated Internal Oscillator” on page 27. 5. Updated “Clock Output Buffer” on page 31. 6. Updated “Power Management and Sleep Modes” on page 34. 7. Added “Software BOD Disable” on page 35. 8. Updated Figure 16-1 on page 119. 9. Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 120. 10. Added note for Table 17-2 on page 125. 11. Updated “Register Summary” on page 200. 1. Updated “Digital Input Enable and Sleep Modes” on page 57. 2. Updated Table 20-16 on page 158. 3. Updated “Ordering Information” on page 204.ATtiny25/45/85 [DATASHEET] 221 2586Q–AVR–08/2013 28.13 Rev. 2586E-03/06 28.14 Rev. 2586D-02/06 28.15 Rev. 2586C-06/05 28.16 Rev. 2586B-05/05 28.17 Rev. 2586A-02/05 Initial revision. 1. Updated Features in “Analog to Digital Converter” on page 122. 2. Updated Operation in “Analog to Digital Converter” on page 122. 3. Updated Table 17-2 on page 133. 4. Updated Table