Atmel Xplained Pro - Atmel Corporation - Farnell Element 14 - Revenir à l'accueil

 

 

Branding Farnell element14 (France)

 

Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

Logiciels :

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's Soldering Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Pinball Tutorial Trailer

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Ben Heck's Interface Tutorial Trailer

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

Autres documentations :

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Atmel Xplained Pro Atmel® Xplained Pro kits provide a complete and easy to use low-cost development platform for evaluating and prototyping your Atmel Flash-based microcontrollers (MCUs) designs. The Xplained Pro kits offer expansion ports that allow you to connect extension boards to provide more system functionality including OLED LCD displays, buttons, sensors and more, for fast application prototyping. You can purchase add-on boards from Atmel, or build your own. The new kits are part of Atmel’s complete MCU tools ecosystem, working seamlessly with Atmel Studio 6 IDP that includes over 1600 example projects from Atmel Software Framework. When combined with Atmel Gallery, an online apps store for development tools and embedded software, and Atmel Spaces, a cloud-based collaborative development work space, the Xplained Pro kits further simplify your embedded MCU designs reducing your overall development time. To learn more about Atmel Xplained Pro kits, visit http://www.atmel.com/XplainedPro Atmel Xplained Pro kits are available from your Atmel distributor or at store.atmel.com.© 2013 Atmel Corporation. All rights reserved. / Rev.: Atmel-45024B-Xplained-Pro-Flyer_E_A5_0213 Atmel®, Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T : (+1)(408) 441. 0311 F : (+1)(408) 436. 4200 | www.atmel.com Evaluation Kit Contents SAP Code Price SAM4L Xplained Pro Evaluation Kit SAM4L MCU Board ATSAM4L-XPRO $39 SAM4S Xplained Pro Evaluation Kit SAM4S MCU Board ATSAM4S-XPRO $39 ATmega256RFR2 Xplained Pro Evaluation Kit ATmega256RFR2 MCU Board ATMEGA256RFR2-XPRO $39 SAM4L Xplained Pro Starter Kit SAM4L MCU Board 4 Extension Boards: Segment LCD, OLED Display, I/O, Prototyping ATSAM4L-XSTK $109 SAM4S Xplained Pro Starter Kit SAM4S MCU Board 3 Extension Boards: OLED Display, I/O, Prototyping ATSAM4S-XSTK $99 RFR2 Xplained Pro Starter Kit 3 Extension Boards: OLED Display, I/O, Prototyping ATMEGA256RFR2-XSTK $99 OLED Xplained Pro Extension Extension board with 128x32 OLED Display, 3 Buttons and 3 LEDs ATOLED1-XPRO $22 Segment LCD Xplained Pro Extension Extension Board with LCD Segment Display ATSLCD1-XPRO $22 I/O Xplained Pro Extension Extension Board with Light Sensor, Temperature Sensor, Micro SD Card, UART Loopback ATIO1-XPRO $27 Prototyping Xplained Pro Extension Prototyping Extension Board with Bread-boarding Area ATPROTO1-XPRO $18 Not recommended for new designs - Use XMEGA A1U series 8067O–AVR–06/2013 Features  High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller  Nonvolatile program and data memories  64K - 128KBytes of in-system self-programmable flash  4K - 8KBytes boot section  2 KBBytes EEPROM  4 KB - 8 KBBytes internal SRAM  External bus interface for up to 16Mbytes SRAM  External bus interface for up to 128Mbit SDRAM  Peripheral features  Four-channel DMA controller  Eight-channel event system  Eight 16-bit timer/counters  Four timer/counters with 4 output compare or input capture channels  Four timer/counters with 2 output compare or input capture channels  High resolution extension on all timer/counters  Advanced waveform extension (AWeX) on two timer/counters  Eight USARTs with IrDA support for one USART  Four two-wire interfaces with dual address match (I2 C and SMBus compatible)  Four serial peripheral interfaces (SPIs)  AES and DES crypto engine  16-bit real time counter (RTC) with separate oscillator  Two sixteen channel, 12-bit, 2msps Analog to Digital Converters  Two two-channel, 12-bit, 1msps Digital to Analog Converters  Four Analog Comparators (ACs) with window compare function, and current sources  External interrupts on all general purpose I/O pins  Programmable watchdog timer with separate on-chip ultra low power oscillator  QTouch® library support  Capacitive touch buttons, sliders and wheels  Special microcontroller features  Power-on reset and programmable brown-out detection  Internal and external clock options with PLL and prescaler  Programmable multilevel interrupt controller  Five sleep modes  Programming and debug interfaces  JTAG (IEEE 1149.1 compliant) interface, including boundary scan  PDI (Program and Debug Interface)  I/O and packages  78 Programmable I/O pins  100 lead TQFP  100 ball BGA  100 ball VFBGA  Operating voltage  1.6 – 3.6V  Operating frequency  0 – 12MHz from 1.6V  0 – 32MHz from 2.7V 8/16-bit XMEGA A1 Microcontroller ATxmega128A1 / ATxmega64A1 Preliminary 8067O–AVR–06/2013 Not recommended for new designs - Use XMEGA A1U series[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 2 8067O–AVR–06/2013 ‘ 1. Ordering Information Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For packaging information, see “Packaging information” on page 70. Typical Applications Ordering Code Flash (B) E2 SRAM Speed (MHz) Power Supply Package(1)(2)(3) Temp ATxmega128A1-AU 128K + 8K 2 KB 8 KB 32 1.6 - 3.6V 100A -40C - 85C ATxmega128A1-AUR ATxmega64A1-AU 64K + 4K 2 KB 4 KB ATxmega64A1-AUR ATxmega128A1-CU 128K + 8K 2 KB 8 KB 100C1 ATxmega128A1CUR ATxmega64A1-CU 64K + 4K 2 KB 4 KB ATxmega64A1-CUR ATxmega128A1-C7U 128K + 8K 2 KB 8 KB 100C2 ATxmega128A1-C7UR ATxmega64A1-C7U 64K + 4K 2 KB 4 KB ATxmega64A1-C7UR Package Type 100A 100-lead, 14 x 14 x 1.0mm, 0.5mm lead pitch, thin profile plastic quad flat package (TQFP) 100C1 100-ball, 9 x 9 x 1.2mm body, ball pitch 0.88mm, chip ball grid array (CBGA) 100C2 100-ball, 7 x 7 x 1.0mm body, ball pitch 0.65mm, very thin fine-pitch ball grid array (VFBGA) Industrial control Climate control Low power battery applications Factory automation RF and ZigBee® Power tools Building control Sensor control HVAC Board control Optical Utility metering White goods Medical applications[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 3 8067O–AVR–06/2013 2. Pinout/Block Diagram Figure 2-1. Block diagram and pinout Notes: 1. For full details on pinout and pin functions refer to “Pinout and Pin Functions” on page 55. 2. VCC/GND on pin 83/84 are swapped compared to other VCC/GND to allow easier routing of GND to 32kHz crystal. INDEX CORNER PA6 PA7 GND AVCC PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 GND VCC PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND VCC PD0 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PD1 PD2 PD3 PD4 PD5 PD6 PD7 GND VCC PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 GND VCC PF0 PF1 PF2 PF3 PF4 PF5 PK0 VCC GND PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 VCC GND PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 VCC GND PF7 PF6 PA5 PA4 PA3 PA2 PA1 PA0 AVCC GND PR1 PR0 RESET/PDI PDI PQ3 PQ2 PQ1 PQ0 GND VCC PK7 PK6 PK5 PK4 PK3 PK2 PK1 FLASH RAM E 2PROM DMA Interrupt Controlle r OCD External Bus Interface ADC A ADC B DAC B DAC A AC A0 AC A1 AC B0 AC B1 Port A Port B Event System ctrl Port K Port J Port H Port R Port Q Power Contro l Reset Contro l Watchdog OSC/CLK Contro l BOD POR RTC EVENT ROUTING NETWORK DATA BU S DATA BU S VREF TEMP Port C CPU T/C0:1 USART0:1 TWI SPI Port D Port E Port F T/C0:1 USART0/1 TWI SPI T/C0:1 USART0:1 TWI SPI T/C0:1 USART0:1 TWI SPI[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 4 8067O–AVR–06/2013 Figure 2-2. CBGA-pinout Table 2-1. CBGA-pinout. 1 2 3 4 5 6 7 8 9 10 A PK0 VCC GND PJ3 VCC GND PH1 GND VCC PF7 B PK3 PK2 PK1 PJ4 PH7 PH4 PH2 PH0 PF6 PF5 C VCC PK5 PK4 PJ5 PJ0 PH5 PH3 PF2 PF3 VCC D GND PK6 PK7 PJ6 PJ1 PH6 PF0 PF1 PF4 GND E PQ0 PQ1 PQ2 PJ7 PJ2 PE7 PE6 PE5 PE4 PE3 F PR1 PR0 RESET/ PDI PDI PQ3 PC2 PE2 PE1 PE0 VCC G GND PA1 PA4 PB3 PB4 PC1 PC6 PD7 PD6 GND H AVCC PA2 PA5 PB2 PB5 PC0 PC5 PD5 PD4 PD3 J PA0 PA3 PB0 PB1 PB6 PC3 PC4 PC7 PD2 PD1 K PA6 PA7 GND AVCC PB7 VCC GND VCC GND PD0 A B C D E F G H J K 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K 10 9 8 7 6 5 4 3 2 1 Top view Bottom view[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 5 8067O–AVR–06/2013 3. Overview The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The Atmel AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The AVR XMEGA A1 devices provide the following features: in-system programmable flash with read-while-write capabilities; internal EEPROM and SRAM; four-channel DMA controller, eight-channel event system and programmable multilevel interrupt controller, 78 general purpose I/O lines, 16-bit real-time counter (RTC); eight flexible, 16-bit timer/counters with compare and PWM channels, eight USARTs; four two-wire serial interfaces (TWIs); four serial peripheral interfaces (SPIs); AES and DES cryptographic engine; two 16-channel, 12-bit ADCs with programmable gain; two 2-channel, 12-bit DACs; four Analog Comparators (ACs) with window mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection. The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for boundary scan, on-chip debug and programming. The XMEGA A1 devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The powerdown mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode. Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The device are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can be reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the device can use any interface to download the application program to the flash memory. The boot loader software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. By combining an 8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 6 8067O–AVR–06/2013 3.1 Block Diagram Figure 3-1. XMEGA A1 Block Diagram VBAT Power Supervision Battery Backup Controller Real Time Counter 32.768 kHz XOSC Power Supervision POR/BOD & RESET PORT A (8) PORT B (8) EVENT ROUTING NETWORK DMA Controller BUS Matrix SRAM EBI ADCA DACA ACA DACB ADCB ACB OCD PORT K (8) PORT J (8) PORT H (8) PDI Watchdog Timer Watchdog Oscillator Interrupt Controller DATA BUS Prog/Debug Controller PORT R (2) Oscillator Circuits/ Clock Generation Oscillator Control Real Time Counter Event System Controller JTAG Sleep Controller DES IRCOM PORT G (8) PORT L (8) PORT Q (8) PORT M (8) PORT C (8) TCC0:1 USARTC0:1 SPIC TWIC PORT D (8) TCD0:1 USARTD0:1 SPID TWID TCF0:1 USARTF0:1 SPIF TWIF TCE0:1 USARTE0:1 SPIE TWIE PORT E (8) PORT F (8) EVENT ROUTING NETWORK AES AREFA AREFB PORT N (8) PORT P (8) CPU NVM Controller Flash EEPROM DATA BUS Int. Refs. Tempref Digital function Analog function Bus masters / Programming / Debug Oscillator / Crystal / Clock General Purpose I/O EBI[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 7 8067O–AVR–06/2013 4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading  XMEGA A Manual  XMEGA A Application Notes This device data sheet only contains part specific information and a short description of each peripheral and module. The XMEGA A Manual describes the modules and peripherals in depth. The XMEGA A application notes contain example code and show applied use of the modules and peripherals. The XMEGA A Manual and Application Notes are available from http://www.atmel.com/avr. 5. Capacitive touch sensing The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key events. The QTouch library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the QTouch library user guide - also available for download from the Atmel website. 6. Disclaimer For devices that are not available yet, typical values contained in this datasheet are based on simulations and characterization of other AVR XMEGA microcontrollers manufactured on the same process technology. Min. and Max values will be available after the device is characterized.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 8 8067O–AVR–06/2013 7. AVR CPU 7.1 Features  8/16-bit high performance AVR RISC Architecture  138 instructions  Hardware multiplier  32x8-bit registers directly connected to the ALU  Stack in SRAM  Stack Pointer accessible in I/O memory space  Direct addressing of up to 16M Bytes of program and data memory  True 16/24-bit access to 16/24-bit I/O registers  Support for 8-, 16- and 32-bit Arithmetic  Configuration Change Protection of system critical features 7.2 Overview All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable Multilevel Interrupt Controller” on page 29. 7.3 Architectural Overview In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 9 8067O–AVR–06/2013 Figure 7-1. Block diagram of the AVR CPU architecture. The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data space addressing, enabling efficient address calculations. The memory spaces are linear. The data memory space and the program memory space are two different memory spaces. The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be memory mapped in the data memory. All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F. The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions. The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different addressing modes supported in the AVR architecture. The first SRAM address is 0x2000. Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM. The program memory is divided in two sections, the application program section and the boot program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for selfprogramming of the application flash memory must reside in the boot program section. The application section contains an application table section with separate lock bits for write and read/write protection. The application table section can be used for safe storing of nonvolatile data in the program memory.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 10 8067O–AVR–06/2013 7.4 ALU - Arithmetic Logic Unit The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware multiplier supports signed and unsigned multiplication and fractional format. 7.4.1 Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different variations of signed and unsigned integer and fractional numbers:  Multiplication of unsigned integers  Multiplication of signed integers  Multiplication of a signed integer with an unsigned integer  Multiplication of unsigned fractional numbers  Multiplication of signed fractional numbers  Multiplication of a signed fractional number with an unsigned one A multiplication takes two CPU clock cycles. 7.5 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the flash program memory ‘0.’ The program counter (PC) addresses the next instruction to be fetched. Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format. During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU. 7.6 Status Register The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt. This must be handled by software. The status register is accessible in the I/O memory space. 7.6.1 Stack and Stack Pointer The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded [Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 11 8067O–AVR–06/2013 after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled. During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices with more than 128KB of program memory, the return address is three bytes, and hence the SP is decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the RETI instruction, and from subroutine calls using the RET instruction. The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one when data is popped off the stack using the POP instruction. To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts for up to four instructions or until the next I/O memory write. After reset the stack pointer is initialized to the highest address of the SRAM. See Table 8-2 on page 15. 7.7 Register File The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register file supports the following input/output schemes:  One 8-bit output operand and one 8-bit result input  Two 8-bit output operands and one 8-bit result input  Two 8-bit output operands and one 16-bit result input  One 16-bit output operand and one 16-bit result input Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 12 8067O–AVR–06/2013 8. Memories 8.1 Features  Flash Program Memory  One linear address space  In-System Programmable  Self-Programming and Bootloader support  Application Section for application code  Application Table Section for application code or data storage  Boot Section for application code or bootloader code  Separate lock bits and protection for all sections  Built in fast CRC check of a selectable flash program memory section  Data Memory  One linear address space  Single cycle access from CPU  SRAM  EEPROM  Byte and page accessible  Optional memory mapping for direct load and store  I/O Memory  Configuration and Status registers for all peripherals and modules  16 bit-accessible General Purpose Register for global variables or flags  External Memory support  SRAM  SDRAM  Memory mapped external hardware  Bus arbitration  Safe and deterministic handling of CPU and DMA Controller priority  Separate buses for SRAM, EEPROM, I/O Memory and External Memory access  Simultaneous bus access for CPU and DMA Controller  Production Signature Row Memory for factory programmed data  Device ID for each microcontroller device type  Serial number for each device  Oscillator calibration bytes  ADC, DAC and temperature sensor calibration data  User Signature Row  One flash page in size  Can be read and written from software  Content is kept after chip erase 8.2 Overview The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write operations. This prevents unrestricted access to the application software. A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can only be written by an external programmer.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 13 8067O–AVR–06/2013 The available memory size configurations are shown in “Ordering Information” on page 2. In addition each device has a flash memory signature rows for calibration data, device identification, serial number etc. 8.3 In-System Programmable Flash Program Memory he Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device. All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate when executed from the boot loader section. The application section contains an application table section with separate lock settings. This enables safe storage of nonvolatile data in the program memory. Figure 8-1. Flash Program Memory (Hexadecimal address) 8.3.1 Application Section The Application section is the section of the flash that is used for storing the executable application code. The protection level for the application section can be selected by the boot lock bits for this section. The application section can not store any boot loader code since the SPM instruction cannot be executed from the application section. 8.3.2 Application Table Section The application table section is a part of the application section of the flash memory that can be used for storing data. The size is identical to the boot loader section. The protection level for the application table section can be selected by the boot lock bits for this section. The possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. If this section is not used for data, application code can reside here. 8.3.3 Boot Loader Section While the application section is used for storing the application code, the boot loader software must be located in the boot loader section because the SPM instruction can only initiate programming when executing from this section. The SPM instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code can be stored here. Word Address ATxega128A1 ATxmega64A1 0 0 Application Section (Bytes) (128K/64K) ... EFFF / 77FF F000 / 7800 Application Table Section (Bytes) FFFF / 7FFF (8K/4K) 10000 / 8000 Boot Section (Bytes) 10FFF / 87FF (8K/4K)[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 14 8067O–AVR–06/2013 8.3.4 Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical Characteristics” on page 76. The production signature row also contains an ID that identifies each microcontroller device type and a serial number for each manufactured device. The serial number consists of the production lot number, wafer number, and wafer coordinates for the device. The device ID for the available devices is shown in Table 8-1. The production signature row cannot be written or erased, but it can be read from application software and external programmers. Table 8-1. Device ID bytes. 8.3.5 User Signature Row The user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase operations and on-chip debug sessions. 8.4 Fuses and Lock bits The fuses are used to configure important system functions, and can only be written from an external programmer. The application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and watchdog, startup configuration, JTAG enable, and JTAG user ID. The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels. Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the lock bits are erased after the rest of the flash memory has been erased. An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero. Both fuses and lock bits are reprogrammable like the flash program memory. 8.5 Data Memory The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory if available. The data memory is organized as one continuous memory section, see Figure 8-2 on page 15. To simplify development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA devices. The address space for External Memory will always start at the end of Internal SRAM and end at address 0xFFFFFF. Device Device ID bytes Byte 2 Byte 1 Byte 0 ATxmega64A1 4E 96 1E ATxmega128A1 4C 97 1E[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 15 8067O–AVR–06/2013 Figure 8-2. Data Memory Map (Hexadecimal address) 8.6 EEPROM XMEGA AU devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address 0x1000. 8.7 I/O Memory The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which is used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly. In the address range 0x00 - 0x1F, single- cycle instructions for manipulation and checking of individual bits are available. The I/O memory address for all peripherals and modules in XMEGA A1U is shown in the “Peripheral Module Address Map” on page 62. 8.7.1 General Purpose I/O Registers The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions. 8.8 External Memory Four ports can be used for external memory, supporting external SRAM, SDRAM, and memory mapped peripherals such as LCD displays. Refer to “EBI – External Bus Interface” on page 47. The external memory address space will always start at the end of internal SRAM. 8.9 Data Memory and Bus Arbitration Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller read and DMA controller write, etc.) can access different memory sections at the same time. Byte Address ATxmega128A1 Byte Address ATxmega64A1 0 I/O Registers (4 KB) 0 I/O Registers FFF FFF (4 KB) 1000 EEPROM (2 KB) 1000 EEPROM 17FF 17FF (2 KB) RESERVED RESERVED 2000 Internal SRAM (8 KB) 2000 Internal SRAM 3FFF 2FFF (4 KB) 4000 External Memory (0 to 16 MB) 3000 External Memory FFFFFF FFFFFF (0 to 16 MB)[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 16 8067O–AVR–06/2013 8.10 Memory Timing Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. External memory has multi-cycle read and write. The number of cycles depends on the type of memory and configuration of the external bus interface. Refer to the instruction summary for more details on instructions and instruction timing. 8.11 Device ID and Revision Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A separate register contains the revision number of the device. 8.12 I/O Memory Protection Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers themselves are protected by the configuration change protection mechanism. 8.13 JTAG Disable It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG access to the device until the next device reset or until JTAG is enabled again from the application software. As long as JTAG is disabled, the I/O pins required for JTAG can be used as normal I/O pins. 8.14 Flash and EEPROM Page Size The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the flash and byte accessible for the EEPROM. Table 8-2 shows the Flash Program Memory organization. Flash write and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) gives the page number and the least significant address bits (FWORD) gives the word in the page. Table 8-2. Number of words and Pages in the Flash. Table 8-3 shows EEPROM memory organization for the Atmel AVR XMEGA A1U devices. EEPROM write and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page. Device PC size Flash Page Size FWORD FPAGE Application Boot bits bytes words Size No of pages Size No of pages ATxmega64A1 16 64K + 4K 128 Z[7:1] Z[16:8] 64K 256 4K 16 ATxmega128A1 17 128K+ 8K 256 Z[8:1] Z[17:9] 128K 256 8K 16[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 17 8067O–AVR–06/2013 Table 8-3. Number of Bytes and Pages in the EEPROM. 8.14.1 I/O Memory All peripherals and modules are addressable through I/O memory locations in the data memory space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store (ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the CPU and the I/O Memory. The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instructions on these registers. The I/O memory address for all peripherals and modules in XMEGA A1 is shown in the “Peripheral Module Address Map” on page 62. Device EEPROM Page Size E2BYTE E2PAGE No of pages Size bytes ATxmega64A1 2 KB 32 ADDR[4:0] ADDR[10:5] 64 ATxmega128A1 2 KB 32 ADDR[4:0 ADDR[10:5] 64[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 18 8067O–AVR–06/2013 9. DMAC - Direct Memory Access Controller 9.1 Features  Allows High-speed data transfer  From memory to peripheral  From memory to memory  From peripheral to memory  From peripheral to peripheral  4 Channels  From 1 byte and up to 16M bytes transfers in a single transaction  Multiple addressing modes for source and destination address  Increment  Decrement  Static  1, 2, 4, or 8 byte Burst Transfers  Programmable priority between channels 9.2 Overview The four-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. The four DMA channels enable up to four independent and parallel transfers. The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from communication modules. The DMA controller can also read from memory mapped EEPROM. Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from 1 byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source and destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination addresses can be done after each burst or block transfer, or when a transaction is complete. Application software, peripherals, and events can trigger DMA transfers. The four DMA channels have individual configuration and control settings. This include source, destination, transfer triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a transaction is complete or when the DMA controller detects an error on a DMA channel. To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished, and vice versa.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 19 8067O–AVR–06/2013 10. Event System 10.1 Features  Inter-peripheral communication and signalling with minimum latency  CPU and DMA independent operation  8 Event Channels allows for up to 8 signals to be routed at the same time  Events can be generated by  Timer/Counters (TCxn)  Real Time Counter (RTC)  Analog to Digital Converters (ADCx)  Analog Comparators (ACx)  Ports (PORTx)  System Clock (ClkSYS)  Software (CPU)  Events can be used by  Timer/Counters (TCxn)  Analog to Digital Converters (ADCx)  Digital to Analog Converters (DACx)  Ports (PORTx)  DMA Controller (DMAC)  IR Communication Module (IRCOM)  The same event can be used by multiple peripherals for synchronized timing  Advanced Features  Manual Event Generation from software (CPU)  Quadrature Decoding  Digital Filtering  Functions in Active and Idle mode 10.2 Overview The Event System is a set of features for inter-peripheral communication. It enables the possibility for a change of state in one peripheral to automatically trigger actions in one or more peripherals. These changes in a peripheral that will trigger actions in other peripherals are configurable by software. It is a simple, but powerful system as it allows for autonomous control of peripherals without any use of interrupts, CPU or DMA resources. The indication of a change in a peripheral is referred to as an event, and is usually the same as the interrupt conditions for that peripheral. Events are passed between peripherals using a dedicated routing network called the Event Routing Network. Figure 10-1 on page 20 shows a basic block diagram of the Event System with the Event Routing Network and the peripherals to which it is connected. This highly flexible system can be used for simple routing of signals, pin functions or for sequencing of events. The maximum latency is two CPU clock cycles from when an event is generated in one peripheral, until the actions are triggered in one or more other peripherals. The Event System is functional in both Active and Idle modes.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 20 8067O–AVR–06/2013 Figure 10-1. Event system block diagram. he event routing network consists of eight software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to eight parallel event routing configurations. The maximum routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode. DAC Timer / Counters ADC Real Time Counter Port pins CPU / Software DMA Controller IRCOM Event Routing Network Event System Controller clkPER Prescaler AC[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 21 8067O–AVR–06/2013 11. System Clock and Clock options 11.1 Features  Fast start-up time  Safe run-time clock switching  Internal Oscillators:  32 MHz run-time calibrated RC oscillator  2 MHz run-time calibrated RC oscillator  32.768 kHz calibrated RC oscillator  32 kHz Ultra Low Power (ULP) oscillator with 1 kHz ouput  External clock options  0.4 - 16 MHz Crystal Oscillator  32 kHz Crystal Oscillator  External clock  PLL with internal and external clock options with 1 to 31x multiplication  Clock Prescalers with 1x to 2048x division  Fast peripheral clock running at two and four times the CPU clock speed  Automatic Run-Time Calibration of internal oscillators  Crystal Oscillator failure detection 11.2 Overview Atmel AVR XMEGA devices have a flexible clock system supporting a large number of clock sources. It incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the internal oscillator if the external oscillator or PLL fails. When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and prescalers can be changed from software at any time. Figure 11-1 on page 22 presents the principal clock system in the XMEGA A1U family devices. Not all of the clocks need to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduction registers as described in “Power Management and Sleep Modes” on page 24.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 22 8067O–AVR–06/2013 Figure 11-1. The clock system, clock sources and clock distribution 11.3 Clock Options The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock sources can be directly enabled and disabled from software, while others are automatically enabled or disabled, depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other clock sources and PLL are turned off by default. The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the internal oscillators, refer to the device datasheet. 11.3.1 32 kHz Ultra Low Power Internal Oscillator This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a 1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This oscillator can be selected as the clock source for the RTC. Real Time Counter Peripherals RAM AVR CPU Non-Volatile Memory Watchdog Timer Brown-out Detector System Clock Prescalers System Clock Multiplexer (SCLKSEL) PLLSRC RTCSRC DIV32 32 kHz Int. ULP 32.768 kHz Int. OSC 32.768 kHz TOSC 2 MHz Int. Osc 32 MHz Int. Osc 0.4 – 16 MHz XTAL DIV32 DIV32 DIV4 XOSCSEL PLL TOSC1 TOSC2 XTAL1 XTAL2 clkSYS clkRTC clkPER2 clkPER clkCPU clkPER4[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 23 8067O–AVR–06/2013 11.3.2 32.768 kHz Calibrated Internal Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz output. 11.3.3 32.768 kHz Crystal Oscillator A 32.768kHz crystal oscillator can be connected between the 1 and 2 pins and enables a dedicated low frequency oscillator input circuit. A low power mode with reduced voltage swing on 2 is available. This oscillator can be used as a clock source for the system clock and RTC. 11.3.4 0.4 - 16 MHz Crystal Oscillator This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz. 11.3.5 2 MHz Run-time Calibrated Internal Oscillator The 2MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated during production to provide a default frequency which is close to its nominal frequency. The oscillator can use the 32kHz Calibrated Internal Oscillator or the 32kHz Crystal Oscillator as a source for calibrating the frequency run-time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator. 11.3.6 32 MHz Run-time Calibrated Internal Oscillator The 32MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated during production to provide a default frequency which is close to its nominal frequency. The oscillator can use the 32kHz Calibrated Internal Oscillator or the 32kHz Crystal Oscillator as a source for calibrating the frequency run-time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator. 11.3.7 External Clock input The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator. XTAL1 can be used as input for an external clock signal. The 1 and 2 pins is dedicated to driving a 32.768kHz crystal oscillator. 11.3.8 PLL with Multiplication factor 1 - 31x The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a userselectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 24 8067O–AVR–06/2013 12. Power Management and Sleep Modes 12.1 Features  Power management for adjusting power consumption and functions  5 sleep modes  Idle  Power-down  Power-save  Standby  Extended standby  Power reduction register to disable clock and turn off unused peripherals in active and idle modes 12.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements. This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power. All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to active mode. In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power management than sleep modes alone. 12.3 Sleep Modes Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA microcontrollers have five different sleep modes tuned to match the typical functional stages during application execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution starts. The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will reset, start up, and execute from the reset vector. 12.3.1 Idle Mode In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled interrupt will wake the device. 12.3.2 Power-down Mode In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the twowire interface address match interrupt and asynchronous port interrupts, e.g pin change.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 25 8067O–AVR–06/2013 12.3.3 Power-save Mode Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. 12.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. 12.3.5 Extended Standby Mode Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 26 8067O–AVR–06/2013 13. System Control and Reset 13.1 Features  Multiple reset sources for safe operation and device reset  Power-On Reset  External Reset  Watchdog Reset  Brown-Out Reset  PDI reset  Software reset  Asynchronous reset  No running clock in the device is required for reset  Reset status register 13.2 Overview The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of the accessed location can not be guaranteed. After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to move the reset vector to the lowest address in the boot section. The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software reset feature makes it possible to issue a controlled system reset from the user software. The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows which sources have issued a reset since the last power-on. 13.3 Reset Sequence A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active. When all reset requests are released, the device will go through three stages before the device starts running again:  Reset counter delay  Oscillator startup  Oscillator calibration If another reset requests occurs during this process, the reset sequence will start over again. 13.4 Reset Sources 13.4.1 Power-On Reset TA power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and reaches the POR threshold voltage (VPOT), and this will start the reset sequence. The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level. The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 27 8067O–AVR–06/2013 13.4.2 Brownout Detection The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed, programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and when the PDI is enabled. 13.4.3 External Reset The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor. 13.4.4 Watchdog Reset The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one to two clock cycles of the 2MHz internal oscillator. For more details see “WDT - Watchdog Timer” on page 28. 13.4.5 Software reset The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any instruction from when a software reset is requested until it is issued. 13.4.6 Program and Debug Interface Reset The program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debugging. This reset source is accessible only from external debuggers and programmers.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 28 8067O–AVR–06/2013 13.5 WDT - Watchdog Timer 13.5.1 Features  Issues a device reset if the timer is not reset before its timeout period  Asynchronous operation from dedicated oscillator  1kHz output of the 32kHz ultra low power oscillator  11 selectable timeout periods, from 8ms to 8s  Two operation modes:  Normal mode  Window mode  Configuration lock to prevent unwanted changes 13.6 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application code. The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued. Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution. The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock source, and will continue to operate to issue a system reset even if the main clocks fail. The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For increased safety, a fuse for locking the WDT settings is also available.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 29 8067O–AVR–06/2013 14. Interrupts and Programmable Multilevel Interrupt Controller 14.1 Features  Short and predictable interrupt response time  Separate interrupt configuration and vector address for each interrupt  Programmable multilevel interrupt controller  Interrupt prioritizing according to level and vector address  Three selectable interrupt levels for all interrupts: low, medium and high  Selectable, round-robin priority scheme within low-level interrupts  Non-maskable interrupts for critical functions  Interrupt vectors optionally placed in the application section or the boot loader section 14.2 Overview Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed. All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time. Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions. 14.3 Interrupt vectors The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in each peripheral. The base addresses for the Atmel AVR XMEGA A1U devices are shown in Table 14-1. Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1. The program address is the word address. Table 14-1. Reset and Interrupt vectors Program Address (Base Address) Source Interrupt Description 0x000 RESET 0x002 OSCF_INT_vect Crystal Oscillator Failure Interrupt vector (NMI) 0x004 PORTC_INT_base Port C Interrupt base 0x008 PORTR_INT_base Port R Interrupt base 0x00C DMA_INT_base DMA Controller Interrupt base 0x014 RTC_INT_base Real Time Counter Interrupt base 0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 30 8067O–AVR–06/2013 0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base 0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base 0x030 SPIC_INT_vect SPI on port C Interrupt vector 0x032 USARTC0_INT_base USART 0 on port C Interrupt base 0x038 USARTC1_INT_base USART 1 on port C Interrupt base 0x03E AES_INT_vect AES Interrupt vector 0x040 NVM_INT_base Non-Volatile Memory Interrupt base 0x044 PORTB_INT_base Port B Interrupt base 0x048 ACB_INT_base Analog Comparator on Port B Interrupt base 0x04E ADCB_INT_base Analog to Digital Converter on Port B Interrupt base 0x056 PORTE_INT_base Port E Interrupt base 0x05A TWIE_INT_base Two-Wire Interface on Port E Interrupt base 0x05E TCE0_INT_base Timer/Counter 0 on port E Interrupt base 0x06A TCE1_INT_base Timer/Counter 1 on port E Interrupt base 0x072 SPIE_INT_vect SPI on port E Interrupt vector 0x074 USARTE0_INT_base USART 0 on port E Interrupt base 0x07A USARTE1_INT_base USART 1 on port E Interrupt base 0x080 PORTD_INT_base Port D Interrupt base 0x084 PORTA_INT_base Port A Interrupt base 0x088 ACA_INT_base Analog Comparator on Port A Interrupt base 0x08E ADCA_INT_base Analog to Digital Converter on Port A Interrupt base 0x096 TWID_INT_base Two-Wire Interface on Port D Interrupt base 0x09A TCD0_INT_base Timer/Counter 0 on port D Interrupt base 0x0A6 TCD1_INT_base Timer/Counter 1 on port D Interrupt base 0x0AE SPID_INT_vector SPI on port D Interrupt vector 0x0B0 USARTD0_INT_base USART 0 on port D Interrupt base 0x0B6 USARTD1_INT_base USART 1 on port D Interrupt base 0x0BC PORTQ_INT_base Port Q INT base 0x0C0 PORTH_INT_base Port H INT base 0x0C4 PORTJ_INT_base Port J INT base 0x0C8 PORTK_INT_base Port K INT base 0x0D0 PORTF_INT_base Port F INT base 0x0D4 TWIF_INT_base Two-Wire Interface on Port F INT base Program Address (Base Address) Source Interrupt Description[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 31 8067O–AVR–06/2013 0x0D8 TCF0_INT_base Timer/Counter 0 on port F Interrupt base 0x0E4 TCF1_INT_base Timer/Counter 1 on port F Interrupt base 0x0EC SPIF_INT_vector SPI ion port F Interrupt base 0x0EE USARTF0_INT_base USART 0 on port F Interrupt base 0x0F4 USARTF1_INT_base USART 1 on port F Interrupt base Program Address (Base Address) Source Interrupt Description[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 32 8067O–AVR–06/2013 15. I/O Ports 15.1 Features  78 General purpose input and output pins with individual configuration  Output driver with configurable driver and pull settings:  Totem-pole  Wired-AND  Wired-OR  Bus-keeper  Inverted I/O  Input with synchronous and/or asynchronous sensing with interrupts and events  Sense both edges  Sense rising edges  Sense falling edges  Sense low level  Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations  Optional slew rate control  Asynchronous pin change sensing that can wake the device from all sleep modes  Two port interrupts with pin masking per I/O port  Efficient and safe access to port pins  Hardware read-modify-write through dedicated toggle/clear/set registers  Configuration of multiple pins in a single operation  Mapping of port registers into bit-accessible I/O memory space  Peripheral clocks output on port pin  Real-time counter clock output to port pin  Event channels can be output on port pin  Remapping of digital peripheral pin functions  Selectable USART, SPI, and timer/counter input/output pin locations 15.2 Overview One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, included the modes where no clocks are running. All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other pin. The port pin configuration also controls input and output selection of other device functions. It is possible to have both the peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus application needs. The notation of these ports are PORTA, PORTB, PORTC, PORTD, PORTE, PORTF, PORTH, PORTJ, PORTK, PORTQ and PORTR.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 33 8067O–AVR–06/2013 15.3 Output Driver All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. 15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input) 15.3.3 Pull-up Figure 15-3. I/O configuration - Totem-pole with pull-up (on input) INn OUTn DIRn Pn INn OUTn DIRn Pn INn OUTn DIRn Pn[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 34 8067O–AVR–06/2013 15.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. Figure 15-4. I/O configuration - Totem-pole with bus-keeper 15.3.5 Others Figure 15-5. Output configuration - Wired-OR with optional pull-down Figure 15-6. I/O configuration - Wired-AND with optional pull-up INn OUTn DIRn Pn INn OUTn Pn INn OUTn Pn[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 35 8067O–AVR–06/2013 15.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7 on page 35. Figure 15-7. Input sensing system overview When a pin is configured with inverted I/O the pin value is inverted before the input sensing. 15.5 Port Interrupt Each ports have two interrupts with seperate priority and interrupt vector. All pins on the port can be individually selected as source for each of the interrupts. The interrupts are then triggered according to the input sense configuration for each pin configured as source for the interrupt. 15.6 Alternate Port Functions In addition to the input/output functions on all port pins, most pins have alternate functions. This means that other modules or peripherals connected to the port can use the port pins for their functions, such as communication or pulsewidth modulation. “Pinout and Pin Functions” on page 55 shows which modules on peripherals that enables alternate functions on a pin, and what alternate functions that is available on a pin. INVERTED I/O Interrupt Control IREQ Event Pn D Q R D Q R Synchronizer INn EDGE DETECT Asynchronous sensing Synchronous sensing EDGE DETECT[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 36 8067O–AVR–06/2013 16. T/C - 16-bit Timer/Counter 16.1 Features  Eight 16-bit Timer/Counters  Four Timer/Counters of type 0  Four Timer/Counters of type 1  Four Compare or Capture (CC) Channels in Timer/Counter 0  Two Compare or Capture (CC) Channels in Timer/Counter 1  Double Buffered Timer Period Setting  Double Buffered Compare or Capture Channels  Waveform Generation:  Single Slope Pulse Width Modulation  Dual Slope Pulse Width Modulation  Frequency Generation  Input Capture:  Input Capture with Noise Cancelling  Frequency capture  Pulse width capture  32-bit input capture  Event Counter with Direction Control  Timer Overflow and Timer Error Interrupts and Events  One Compare Match or Capture Interrupt and Event per CC Channel  Supports DMA Operation  Hi-Resolution Extension (Hi-Res)  Advanced Waveform Extension (AWEX) 16.2 Overview Atmel AVR XMEGA devices have a set of eight flexible 16-bit timer/counters (TC). Their capabilities include accurate program execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture. A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC channels can be used together with the base counter to do compare match control, frequency generation, and pulse width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either capture or compare functions, but cannot perform both at the same time. A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system. The event system can also be used for direction control and capture trigger or to synchronize operations. There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0. Only Timer/Counter 0 has the split mode feature that split it into 2 8-bit Timer/Counters with four compare channels each. Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and highside output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins. The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter. This is only available for Timer/Counter 0. See “AWeX - Advanced Waveform Extension” on page 38 for more details.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 37 8067O–AVR–06/2013 The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res - High Resolution Extension” on page 39 for more details. Figure 16-1. Overview of a Timer/Counter and closely related peripherals PORTC, PORTD, PORTE and PORTF each has one Timer/Counter 0 and one Timer/Counter1. Notation of these Timer/Counters are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1, TCE0, TCE1, TCF0, and TCF1, respectively. AWeX Compare/Capture Channel D Compare/Capture Channel C Compare/Capture Channel B Compare/Capture Channel A Waveform Generation Buffer Comparator Hi-Res Fault Protection Capture Control Base Counter Counter Control Logic Timer Period Prescaler DTI Dead-Time Insertion Pattern Generation clkPER4 PORT Event System clkPER Timer/Counter[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 38 8067O–AVR–06/2013 17. AWeX - Advanced Waveform Extension 17.1 Features  Output with complementary output from each Capture channel  Four Dead Time Insertion (DTI) Units, one for each Capture channel  8-bit DTI Resolution  Separate High and Low Side Dead-Time Setting  Double Buffered Dead-Time  Event Controlled Fault Protection  Single Channel Multiple Output Operation (for BLDC motor control)  Double Buffered Pattern Generation 17.2 Overview The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG) modes. It is primarily intended for use with different types of motor control and other power control applications. It enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins. Each of the waveform generator outputs from the Timer/Counter 0 are split into a complimentary pair of outputs when any AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the noninverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override setting. The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition, the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator unit is enabled, the DTI unit is bypassed. The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable the AWeX output. The event system ensures predictable and instant fault reaction, and gives great flexibility in the selection of fault triggers. The AWeX is available for TCC0 and TCE0. The notation of these are AWEXC and AWEXE.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 39 8067O–AVR–06/2013 18. Hi-Res - High Resolution Extension 18.1 Features  Increases Waveform Generator resolution by 2-bits (4x)  Supports Frequency, single- and dual-slope PWM operation  Supports the AWeX when this is enabled and used for the same Timer/Counter 18.2 Overview TThe high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM generation. It can also be used with the AWeX if this is used for the same timer/counter. The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension is enabled. There are four hi-res extensions that each can be enabled for each timer/counters pair on PORTC, PORTD, PORTE and PORTF. The notation of these peripherals are HIRESC, HIRESD, HIRESE and HIRESF, respectively.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 40 8067O–AVR–06/2013 19. RTC - 16-bit Real-Time Counter 19.1 Features  16-bit resolution  Selectable clock source  32.768kHz external crystal  External clock  32.768kHz internal oscillator  32kHz internal ULP oscillator  Programmable 10-bit clock prescaling  One compare register  One period register  Clear counter on period overflow  Optional interrupt/event on overflow and compare match 19.2 Overview The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals. The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal oscillator or the 32kHz internal ULP oscillator. The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period register value. Figure 19-1. Real Time Counter overview 32.768kHz Crystal Osc 32.768kHz Int. Osc TOSC1 TOSC2 External Clock DIV32 DIV32 32kHz int ULP (DIV32) RTCSRC 10-bit prescaler clkRTC CNT PER COMP = = ”match”/ Compare TOP/ Overflow[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 41 8067O–AVR–06/2013 20. TWI - Two-Wire Interface 20.1 Features  Four identical two-wire interface peripherals  Bidirectional two-wire communication interface  Phillips I2C compatible  System Management Bus (SMBus) compatible  Bus master and slave operation supported  Slave operation  Single bus master operation  Bus master in multi-master bus environment  Multi-master arbitration  Flexible slave address match functions  7-bit and general call address recognition in hardware  10-bit addressing supported  Address mask register for dual address match or address range masking  Optional software address recognition for unlimited number of addresses  Slave can operate in all sleep modes, including power-down  Slave address match can wake device from all sleep modes, including power-down  100kHz and 400kHz bus frequency support  Slew-rate limited output drivers  Input filter for bus noise and spike suppression  Support arbitration between start repeated start and data bit (SMBus)  Slave arbitration allows support for address resolve protocol (ARP) (SMBus) 20.2 Overview The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus (SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line. A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol. The TWI module supports master and slave functionality. The master and slave functionality are separated from each other, and can be enabled and configured separately. The master module supports multi-master bus operation and arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command and smart mode can be enabled to auto-trigger operations and reduce software complexity. The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is also supported. A dedicated address mask register can act as a second address match register or as a register for address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address matching to let this be handled in software instead. The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision, and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave modes. [Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 42 8067O–AVR–06/2013 It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by the TWI bus. PORTC, PORTD, PORTE, and PORTF each has one TWI. Notation of these peripherals are TWIC, TWID, TWIE, and TWIF.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 43 8067O–AVR–06/2013 21. SPI - Serial Peripheral Interface 21.1 Features  Four identical SPI peripherals  Full-duplex, three-wire synchronous data transfer  Master or slave operation  Lsb first or msb first data transfer  Eight programmable bit rates  Interrupt flag at the end of transmission  Write collision flag to indicate data collision  Wake up from idle sleep mode  Double speed master mode 21.2 Overview The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several microcontrollers. The SPI supports full-duplex communication. A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions. PORTC, PORTD, PORTE, and PORTF each has one SPI. Notation of these peripherals are SPIC, SPID, SPIE, and SPIF.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 44 8067O–AVR–06/2013 22. USART 22.1 Features  Eight identical USART peripherals  Full-duplex operation  Asynchronous or synchronous operation  Synchronous clock rates up to 1/2 of the device clock frequency  Asynchronous clock rates up to 1/8 of the device clock frequency  Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits  Fractional baud rate generator  Can generate desired baud rate from any system clock frequency  No need for external oscillator with certain frequencies  Built-in error detection and correction schemes  Odd or even parity generation and parity check  Data overrun and framing error detection  Noise filtering includes false start bit detection and digital low-pass filter  Separate interrupts for  Transmit complete  Transmit data register empty  Receive complete  Multiprocessor communication mode  Addressing scheme to address a specific devices on a multidevice bus  Enable unaddressed devices to automatically ignore all frames  Master SPI mode  Double buffered operation  Operation up to 1/2 of the peripheral clock frequency  IRCOM module for IrDA compliant pulse modulation/demodulation 22.2 Overview The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial communication module. The USART supports full-duplex communication and asynchronous and synchronous operation. The USART can be configured to operate in SPI master mode and used for SPI communication. Communication is frame based, and the frame format can be customized to support a wide range of standards. The USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can also be enabled. The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency to achieve a required baud rate. It also supports external clock input in synchronous slave operation. When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes. The registers are used in both modes, but their functionality differs for some control settings. An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2Kbps. PORTC, PORTD, PORTE, and PORTF each has two USARTs. Notation of these peripherals are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0, USARTE1, USARTF0 and USARTF1.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 45 8067O–AVR–06/2013 23. IRCOM - IR Communication Module 23.1 Features  Pulse modulation/demodulation for infrared communication  IrDA compatible for baud rates up to 115.2Kbps  Selectable pulse modulation scheme  3/16 of the baud rate period  Fixed pulse period, 8-bit programmable  Pulse modulation disabled  Built-in filtering  Can be connected to and used by any USART 23.2 Overview Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 46 8067O–AVR–06/2013 24. AES and DES Crypto Engine 24.1 Features  Data Encryption Standard (DES) CPU instruction  Advanced Encryption Standard (AES) crypto module  DES Instruction  Encryption and decryption  DES supported  Encryption/decryption in 16 CPU clock cycles per 8-byte block  AES crypto module  Encryption and decryption  Supports 128-bit keys  Supports XOR data load mode to the state memory  Encryption/decryption in 375 clock cycles per 16-byte block 24.2 Overview The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used standards for cryptography. These are supported through an AES peripheral module and a DES CPU instruction, and the communication interfaces and the CPU can use these for fast, encrypted communication and secure data storage. DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into the register file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block. The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out, and an optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 47 8067O–AVR–06/2013 25. EBI – External Bus Interface 25.1 Features  Supports SRAM up to:  512KB using 3-port EBI configuration  16MB using 3-port EBI configuration  Supports SDRAM up to:  128Mb using 3-port EBI configuration  Four software configurable chip selects  Software configurable wait state insertion  Can run from the 2x peripheral clock frequency for fast access 25.2 Overview The External Bus Interface (EBI) is used to connect external peripherals and memory for access through the data memory space. When the EBI is enabled, data address space outside the internal SRAM becomes available using dedicated EBI pins. The EBI can interface external SRAM, SDRAM, and peripherals, such as LCD displays and other memory mapped devices. The address space for the external memory is selectable from 256 bytes (8-bit) up to 16MB (24-bit). Various multiplexing modes for address and data lines can be selected for optimal use of pins when more or fewer pins are available for the EBI. The complete memory will be mapped into one linear data address space continuing from the end of the internal SRAM. The EBI has four chip selects, each with separate configuration. Each can be configured for SRAM, SRAM low pin count (LPC), or SDRAM. The EBI is clocked from the fast, 2x peripheral clock, running up to two times faster than the CPU. Four-bit and eight-bit SDRAM are supported, and SDRAM configurations, such as CAS latency and refresh rate, are configurable in software.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 48 8067O–AVR–06/2013 26. ADC - 12-bit Analog to Digital Converter 26.1 Features  Two ADCs with 12-bit resolution  2Msps sample rate for each ADC  Signed and unsigned conversions  4 result registers with individual input channel control for each ADC  8 single ended inputs for each ADC  8x4 differential inputs for each ADC  4 internal inputs:  Integrated Temperature Sensor  DAC Output  VCC voltage divided by 10  Bandgap voltage  Software selectable gain of 2, 4, 8, 16, 32 or 64  Software selectable resolution of 8- or 12-bit.  Internal or External Reference selection  Event triggered conversion for accurate timing  DMA transfer of conversion results  Interrupt/Event on compare result 26.2 Overview XMEGA A1 devices have two Analog to Digital Converters (ADC), see Figure 26-1 on page 49. The two ADC modules can be operated simultaneously, individually or synchronized. The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is capable of converting up to 2 million samples per second. The input selection is flexible, and both single-ended and differential measurements can be done. For differential measurements an optional gain stage is available to increase the dynamic range. In addition several internal signal inputs are available. The ADC can provide both signed and unsigned results. This is a pipeline ADC. A pipeline ADC consists of several consecutive stages, where each stage convert one part of the result. The pipeline design enables high sample rate at low clock speeds, and remove limitations on samples speed versus propagation delay. This also means that a new analog voltage can be sampled and a new ADC measurement started while other ADC measurements are ongoing. ADC measurements can either be started by application software or an incoming event from another peripheral in the device. Four different result registers with individual input selection (MUX selection) are provided to make it easier for the application to keep track of the data. Each result register and MUX selection pair is referred to as an ADC Channel. It is possible to use DMA to move ADC results directly to memory or peripherals when conversions are done. Both internal and external analog reference voltages can be used. An accurate internal 1.0V reference is available. An integrated temperature sensor is available and the output from this can be measured with the ADC. The output from the DAC, VCC/10 and the Bandgap voltage can also be measured by the ADC.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 49 8067O–AVR–06/2013 Figure 26-1. ADC overview Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be sampled within 1.5 µs without any intervention by the application other than starting the conversion. The results will be available in the result registers. The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5 µs for 12-bit to 2.5 µs for 8-bit result. ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when the result is represented as a signed integer (signed 16-bit number). PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively. CH1 Result CH0 Result CH2 Result Compare < > Threshold (Int Req) Internal 1.00V Internal VCC/1.6V AREFA AREFB VINP VINN Internal signals Internal signals CH3 Result ADC0 ADC7 ADC4 ADC7 ADC0 ADC3 • • • Int. signals Int. signals Reference Voltage 1x - 64x • • • • • • ADC0 ADC7 • • •[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 50 8067O–AVR–06/2013 27. DAC - 12-bit Digital to Analog Converter 27.1 Features  12-bit resolution  Two independent, continuous-drive output channels  Up to one million samples per second conversion rate  Built-in calibration that removes:  Offset error  Gain error  Multiple conversion trigger sources  On new available data  Events from the event system  High drive capabilities and support for  Resistive loads  Capacitive loads  Combined resistive and capacitive loads  Internal and external reference options  DAC output available as input to analog comparator and ADC  Low-power mode, with reduced drive strength  Optional DMA transfer of data 27.2 Overview The XMEGA A1 devices features two 12-bit, 1 Msps DACs with built-in offset and gain calibration, see Figure 27-1 on page 50. A DAC converts a digital value into an analog signal. The DAC may use an internal 1.0 voltage as the upper limit for conversion, but it is also possible to use the supply voltage or any applied voltage in-between. The external reference input is shared with the ADC reference input. Figure 27-1. DAC overview CH1DATA CH0DATA Trigger Internal 1.00V AREFA AREFB AVCC D A T A DAC CTRL DAC CH0 REFSEL Enable 12 12 ADC DAC DAC CH1 Output Control and Driver[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 51 8067O–AVR–06/2013 Each DAC has one continuous output with high drive capabilities for both resistive and capacitive loads. It is also possible to split the continuous time channel into two Sample and Hold (S/H) channels, each with separate data conversion registers. A DAC conversion may be started from the application software by writing the data conversion registers. The DAC can also be configured to do conversions triggered by the Event System to have regular timing, independent of the application software. DMA may be used for transferring data from memory locations to DAC data registers. The DAC has a built-in calibration system to reduce offset and gain error when loading with a calibration value from software. PORTA and PORTB each has one DAC. Notation of these peripherals are DACA and DACB. respectively.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 52 8067O–AVR–06/2013 28. AC - Analog Comparator 28.1 Features  Four Analog Comparators  Selectable propagation delay versus current consumption  Selectable hysteresis  No  Small  Large  Analog comparator output available on pin  Flexible input selection  All pins on the port  Output from the DAC  Bandgap reference voltage  A 64-level programmable voltage scaler of the internal VCC voltage  Interrupt and event generation on:  Rising edge  Falling edge  Toggle  Window function interrupt and event generation on:  Signal above window  Signal inside window  Signal below window  Constant current source with configurable output pin selection 28.2 Overview The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several different combinations of input change. Two important properties of the analog comparator’s dynamic behavior are: hysteresis and propagation delay. Both of these parameters may be adjusted in order to achieve the optimal operation for each application. The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The analog comparator output state can also be output on a pin for use by external devices. A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example, external resistors used to charge capacitors in capacitive touch sensing applications. The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in window mode to compare a signal to a voltage range instead of a voltage level. PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 53 8067O–AVR–06/2013 Figure 28-1. Analog comparator overview The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 28-2. Figure 28-2. Analog comparator window function ACnMUXCTRL ACnCTRL Interrupt Mode Enable Enable Hysteresis Hysteresis AC1OUT WINCTRL Interrupt Sensititivity Control & Window Function Events Interrupts AC0OUT Pin Input Pin Input Pin Input Pin Input Voltage Scaler DAC Bandgap + - + - AC0 + - AC1 + - Input signal Upper limit of window Lower limit of window Interrupt sensitivity control Interrupts Events[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 54 8067O–AVR–06/2013 29. Programming and Debugging 29.1 Features  Programming  External programming through PDI or JTAG interfaces  Minimal protocol overhead for fast operation  Built-in error detection and handling for reliable operation  Boot loader support for programming through any communication interface  Debugging  Nonintrusive, real-time, on-chip debug system  No software or hardware resources required from device except pin connection  Program flow control  Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor  Unlimited number of user program breakpoints  Unlimited number of user data breakpoints, break on:  Data location read, write, or both read and write  Data location content equal or not equal to a value  Data location content is greater or smaller than a value  Data location content is within or outside a range  No limitation on device clock frequency  Program and Debug Interface (PDI)  Two-pin interface for external programming and debugging  Uses the Reset pin and a dedicated pin  No I/O pins required during programming or debugging  JTAG interface  Four-pin, IEEE Std. 1149.1 compliant interface for programming and debugging  Boundary scan capabilities according to IEEE Std. 1149.1 (JTAG) 29.2 Overview The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip debugging of a device. The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user signature row. Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. Application debug can be done from a C or other high-level language source code level, as well as from an assembler and disassembler level. Programming and debugging can be done through two physical interfaces. The primary one is the PDI physical layer, which is available on all devices. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). A JTAG interface is also available on most devices, and this can be used for programming and debugging through the four-pin JTAG interface. The JTAG interface is IEEE Std. 1149.1 compliant, and supports boundary scan. Any external programmer or on-chip debugger/emulator can be directly connected to either of these interfaces. Unless otherwise stated, all references to the PDI assume access through the PDI physical layer.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 55 8067O–AVR–06/2013 30. Pinout and Pin Functions The pinout of XMEGA A1 is shown in “Pinout/Block Diagram” on page 3. In addition to general I/O functionality, each pin may have several functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate pin functions can be used at time. 30.1 Alternate Pin Function Description The tables below shows the notation for all pin functions available and describes its function. 30.1.1 Operation/Power Supply 30.1.2 Port Interrupt functions 30.1.3 Analog functions 30.1.4 EBI functions VCC Digital supply voltage AVCC Analog supply voltage GND Ground SYNC Port pin with full synchronous and limited asynchronous interrupt function ASYNC Port pin with full synchronous and full asynchronous interrupt function ACn Analog Comparator input pin n AC0OUT Analog Comparator 0 Output ADCn Analog to Digital Converter input pin n DACn Digital to Analog Converter output pin n AREF Analog Reference input pin An Address line n Dn Data line n CSn Chip Select n ALEn Address Latch Enable pin n (SRAM) RE Read Enable (SRAM) WE External Data Memory Write (SRAM /SDRAM) BAn Bank Address (SDRAM) CAS Column Access Strobe (SDRAM) CKE SDRAM Clock Enable (SDRAM)[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 56 8067O–AVR–06/2013 30.1.5 Timer/Counter and AWEX functions 30.1.6 Communication functions 30.1.7 Oscillators, Clock and Event CLK SDRAM Clock (SDRAM) DQM Data Mask Signal/Output Enable (SDRAM) RAS Row Access Strobe (SDRAM) 2P 2 Port Interface 3P 3 Port Interface OCnx Output Compare Channel x for Timer/Counter n OCnx Inverted Output Compare Channel x for Timer/Counter n OCnxLS Output Compare Channel x Low Side for Timer/Counter n OCnxHS Output Compare Channel x High Side for Timer/Counter n SCL Serial Clock for TWI SDA Serial Data for TWI SCLIN Serial Clock In for TWI when external driver interface is enabled SCLOUT Serial Clock Out for TWI when external driver interface is enabled SDAIN Serial Data In for TWI when external driver interface is enabled SDAOUT Serial Data Out for TWI when external driver interface is enabled XCKn Transfer Clock for USART n RXDn Receiver Data for USART n TXDn Transmitter Data for USART n SS Slave Select for SPI MOSI Master Out Slave In for SPI MISO Master In Slave Out for SPI SCK Serial Clock for SPI n Timer Oscillator pin n XTALn Input/Output for inverting Oscillator pin n CLKOUT Peripheral Clock Output EVOUT Event Channel 0 Output[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 57 8067O–AVR–06/2013 30.1.8 Debug/System functions RESET Reset pin PDI_CLK Program and Debug Interface Clock pin PDI_DATA Program and Debug Interface Data pin TCK JTAG Test Clock TDI JTAG Test Data In TDO JTAG Test Data Out TMS JTAG Test Mode Select[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 58 8067O–AVR–06/2013 30.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. Table 30-1. Port A - Alternate functions. Table 30-2. Port B - Alternate functions. Table 30-3. Port C - Alternate functions. PORT A PIN # INTERRUPT ADCA POS ADCA NEG ADCA GAINPOS ADCA GAINNEG ACA POS ACA NEG ACA OUT DACA REFA GND 93 AVCC 94 PA0 95 SYNC ADC0 ADC0 ADC0 AC0 AC0 AREF PA1 96 SYNC ADC1 ADC1 ADC1 AC1 AC1 PA2 97 SYNC/ASYNC ADC2 ADC2 ADC2 AC2 DAC0 PA3 98 SYNC ADC3 ADC3 ADC3 AC3 AC3 DAC1 PA4 99 SYNC ADC4 ADC4 ADC4 AC4 PA5 100 SYNC ADC5 ADC5 ADC5 AC5 AC5 PA6 1 SYNC ADC6 ADC6 ADC6 AC6 PA7 2 SYNC ADC7 ADC7 ADC7 AC7 AC0OUT PORT B PIN # INTERRUPT ADCB POS ADCB NEG ADCB GAINPOS ADCB GAINNEG ACB POS ACB NEG ACB OUT DACB REFB JTAG GND 3 AVCC 4 PB0 5 SYNC ADC0 ADC0 ADC0 AC0 AC0 AREF PB1 6 SYNC ADC1 ADC1 ADC1 AC1 AC1 PB2 7 SYNC/ASYNC ADC2 ADC2 ADC2 AC2 DAC0 PB3 8 SYNC ADC3 ADC3 ADC3 AC3 AC3 DAC1 PB4 9 SYNC ADC4 ADC4 ADC4 AC4 TMS PB5 10 SYNC ADC5 ADC5 ADC5 AC5 AC5 TDI PB6 11 SYNC ADC6 ADC6 ADC6 AC6 TCK PB7 12 SYNC ADC7 ADC7 ADC7 AC7 AC0OUT TDO PORT C PIN # INTERRUPT TCC0 AWEXC TCC1 USARTC0 USARTC1 SPIC TWIC CLOCKOUT EVENTOUT GND 13 VCC 14 PC0 15 SYNC OC0A OC0ALS SDA PC1 16 SYNC OC0B OC0AHS XCK0 SCL PC2 17 SYNC/ASYNC OC0C OC0BLS RXD0[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 59 8067O–AVR–06/2013 Table 30-4. Port D - Alternate functions. Table 30-5. Port E - Alternate functions. Table 30-6. Port F - Alternate functions. PC3 18 SYNC OC0D OC0BHS TXD0 PC4 19 SYNC OC0CLS OC1A SS PC5 20 SYNC OC0CHS OC1B XCK1 MOSI PC6 21 SYNC OC0DLS RXD1 MISO PC7 22 SYNC OC0DHS TXD1 SCK CLKOUT EVOUT PORT D PIN # INTERRUPT TCD0 TCD1 USARTD0 USARTD1 SPID TWID CLOCKOUT EVENTOUT GND 23 VCC 24 PD0 25 SYNC OC0A SDA PD1 26 SYNC OC0B XCK0 SCL PD2 27 SYNC/ASYNC OC0C RXD0 PD3 28 SYNC OC0D TXD0 PD4 29 SYNC OC1A SS PD5 30 SYNC OC1B XCK1 MOSI PD6 31 SYNC RXD1 MISO PD7 32 SYNC TXD1 SCK CLKOUT EVOUT PORT E PIN # INTERRUPT TCE0 AWEXE TCE1 USARTE0 USARTE1 SPIE TWIE CLOCKOUT EVENTOUT GND 33 VCC 34 PE0 35 SYNC OC0A OC0ALS SDA PE1 36 SYNC OC0B OC0AHS XCK0 SCL PE2 37 SYNC/ASYNC OC0C OC0BLS RXD0 PE3 38 SYNC OC0D OC0BHS TXD0 PE4 39 SYNC OC0CLS OC1A SS PE5 40 SYNC OC0CHS OC1B XCK1 MOSI PE6 41 SYNC OC0DLS RXD1 MISO PE7 42 SYNC OC0DHS TXD1 SCK CLKOUT EVOUT PORT F PIN # INTERRUPT TCF0 TCF1 USARTF0 USARTF1 SPIF TWIF GND 43 VCC 44 PF0 45 SYNC OC0A SDA PORT C PIN # INTERRUPT TCC0 AWEXC TCC1 USARTC0 USARTC1 SPIC TWIC CLOCKOUT EVENTOUT[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 60 8067O–AVR–06/2013 Table 30-7. Port H - Alternate functions. Table 30-8. Port J - Alternate functions. PF1 46 SYNC OC0B XCK0 SCL PF2 47 SYNC/ASYNC OC0C RXD0 PF3 48 SYNC OC0D TXD0 PF4 49 SYNC OC1A SS PF5 50 SYNC OC1B XCK1 MOSI PF6 51 SYNC RXD1 MISO PF7 52 SYNC TXD1 SCK PORT H PIN # INTERRUPT SDRAM 3P SRAM ALE1 3P SRAM ALE12 3P LPC ALE1 3P LPC ALE1 2P LPC ALE12 2P GND 53 VCC 54 PH0 55 SYNC WE WE WE WE WE WE PH1 56 SYNC CAS RE RE RE RE RE PH2 57 SYNC/ASYNC RAS ALE1 ALE1 ALE1 ALE1 ALE1 PH3 58 SYNC DQM ALE2 ALE2 PH4 59 SYNC BA0 CS0/A16 CS0 CS0/A16 CS0 CS0/A16 PH5 60 SYNC BA1 CS1/A17 CS1 CS1/A17 CS1 CS1/A17 PH6 61 SYNC CKE CS2/A18 CS2 CS2/A18 CS2 CS2/A18 PH7 62 SYNC CLK CS3/A19 CS3 CS3/A19 CS3 CS3/A19 PORT J PIN # INTERRUPT SDRAM 3P SRAM ALE1 3P SRAM ALE12 3P LPC ALE1 3P LPC ALE1 2P LPC ALE12 2P GND 63 VCC 64 PJ0 65 SYNC D0 D0 D0 D0/A0 D0/A0 D0/A0/A8 PJ1 66 SYNC D1 D1 D1 D1/A1 D1/A1 D1/A1/A9 PJ2 67 SYNC/ASYNC D2 D2 D2 D2/A2 D2/A2 D2/A2/A10 PJ3 68 SYNC D3 D3 D3 D3/A3 D3/A3 D3/A3/A11 PJ4 69 SYNC A8 D4 D4 D4/A4 D4/A4 D4/A4/A12 PJ5 70 SYNC A9 D5 D5 D5/A5 D5/A5 D5/A5/A13 PJ6 71 SYNC A10 D6 D6 D6/A6 D6/A6 D6/A6/A14 PJ7 72 SYNC A11 D7 D7 D7/A7 D7/A7 D7/A7/A15 PORT F PIN # INTERRUPT TCF0 TCF1 USARTF0 USARTF1 SPIF TWIF[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 61 8067O–AVR–06/2013 Table 30-9. Port K - Alternate functions. Table 30-10. Port Q - Alternate functions. Table 30-11. Port R - Alternate functions. PORT K PIN # INTERRUPT SDRAM 3P SRAM ALE1 3P SRAM ALE12 3P LPC ALE1 3P LPC ALE1 2P LPC ALE12 2P GND 73 VCC 74 PK0 75 SYNC A0 A0/A8 A0/A8/A16 A8 PK1 76 SYNC A1 A1/A9 A1/A9/A17 A9 PK2 77 SYNC/ASYNC A2 A2/A10 A2/A10/A18 A10 PK3 78 SYNC A3 A3/A11 A3/A11/A19 A11 PK4 79 SYNC A4 A4/A12 A4/A12/A20 A12 PK5 80 SYNC A5 A5/A13 A5/A13/A21 A13 PK6 81 SYNC A6 A6/A14 A6/A14/A22 A14 PK7 82 SYNC A7 A7/A15 A7/A15/A23 A15 PORT Q PIN # INTERRUPT VCC 83 GND 84 PQ0 85 SYNC TOSC1 (Input) PQ1 86 SYNC TOSC2 (Output) PQ2 87 SYNC/ASYNC PQ3 88 SYNC PORT R PIN # INTERRUPT PDI XTAL PDI 89 PDI_DATA RESET 90 PDI_CLOCK PRO 91 SYNC XTAL2 PR1 92 SYNC XTAL1[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 62 8067O–AVR–06/2013 31. Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA A1. For complete register description and summary for each peripheral module, refer to the XMEGA A Manual. Table 31-1. Peripheral Module Address Map Base Address Name Description 0x0000 GPIO General Purpose IO Registers 0x0010 VPORT0 Virtual Port 0 0x0014 VPORT1 Virtual Port 1 0x0018 VPORT2 Virtual Port 2 0x001C VPORT3 Virtual Port 3 0x0030 CPU CPU 0x0040 CLK Clock Control 0x0048 SLEEP Sleep Controller 0x0050 OSC Oscillator Control 0x0060 DFLLRC32M DFLL for the 32 MHz Internal RC Oscillator 0x0068 DFLLRC2M DFLL for the 2 MHz RC Oscillator 0x0070 PR Power Reduction 0x0078 RST Reset Controller 0x0080 WDT Watch-Dog Timer 0x0090 MCU MCU Control 0x00A0 PMIC Programmable Multilevel Interrupt Controller 0x00B0 PORTCFG Port Configuration 0x00C0 AES AES Module 0x0100 DMA DMA Controller 0x0180 EVSYS Event System 0x01C0 NVM Non Volatile Memory (NVM) Controller 0x0200 ADCA Analog to Digital Converter on port A 0x0240 ADCB Analog to Digital Converter on port B 0x0300 DACA Digital to Analog Converter on port A 0x0320 DACB Digital to Analog Converter on port B 0x0380 ACA Analog Comparator pair on port A 0x0390 ACB Analog Comparator pair on port B 0x0400 RTC Real Time Counter 0x0440 EBI External Bus Interface 0x0480 TWIC Two Wire Interface on port C 0x0490 TWID Two Wire Interface on port D[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 63 8067O–AVR–06/2013 0x04A0 TWIE Two Wire Interface on port E 0x04B0 TWIF Two Wire Interface on port F 0x0600 PORTA Port A 0x0620 PORTB Port B 0x0640 PORTC Port C 0x0660 PORTD Port D 0x0680 PORTE Port E 0x06A0 PORTF Port F 0x06E0 PORTH Port H 0x0700 PORTJ Port J 0x0720 PORTK Port K 0x07C0 PORTQ Port Q 0x07E0 PORTR Port R 0x0800 TCC0 Timer/Counter 0 on port C 0x0840 TCC1 Timer/Counter 1 on port C 0x0880 AWEXC Advanced Waveform Extension on port C 0x0890 HIRESC High Resolution Extension on port C 0x08A0 USARTC0 USART 0 on port C 0x08B0 USARTC1 USART 1 on port C 0x08C0 SPIC Serial Peripheral Interface on port C 0x08F8 IRCOM Infrared Communication Module 0x0900 TCD0 Timer/Counter 0 on port D 0x0940 TCD1 Timer/Counter 1 on port D 0x0990 HIRESD High Resolution Extension on port D 0x09A0 USARTD0 USART 0 on port D 0x09B0 USARTD1 USART 1 on port D 0x09C0 SPID Serial Peripheral Interface on port D 0x0A00 TCE0 Timer/Counter 0 on port E 0x0A40 TCE1 Timer/Counter 1 on port E 0x0A80 AWEXE Advanced Waveform Extension on port E 0x0A90 HIRESE High Resolution Extension on port E 0x0AA0 USARTE0 USART 0 on port E 0x0AB0 USARTE1 USART 1 on port E 0x0AC0 SPIE Serial Peripheral Interface on port E 0x0B00 TCF0 Timer/Counter 0 on port F Base Address Name Description[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 64 8067O–AVR–06/2013 0x0B40 TCF1 Timer/Counter 1 on port F 0x0B90 HIRESF High Resolution Extension on port F 0x0BA0 USARTF0 USART 0 on port F 0x0BB0 USARTF1 USART 1 on port F 0x0BC0 SPIF Serial Peripheral Interface on port F Base Address Name Description[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 65 8067O–AVR–06/2013 32. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks Arithmetic and Logic Instructions ADD Rd, Rr Add without Carry Rd  Rd + Rr Z,C,N,V,S,H 1 ADC Rd, Rr Add with Carry Rd  Rd + Rr + C Z,C,N,V,S,H 1 ADIW Rd, K Add Immediate to Word Rd  Rd + 1:Rd + K Z,C,N,V,S 2 SUB Rd, Rr Subtract without Carry Rd  Rd - Rr Z,C,N,V,S,H 1 SUBI Rd, K Subtract Immediate Rd  Rd - K Z,C,N,V,S,H 1 SBC Rd, Rr Subtract with Carry Rd  Rd - Rr - C Z,C,N,V,S,H 1 SBCI Rd, K Subtract Immediate with Carry Rd  Rd - K - C Z,C,N,V,S,H 1 SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd  Rd + 1:Rd - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Rd  Rd  Rr Z,N,V,S 1 ANDI Rd, K Logical AND with Immediate Rd  Rd  K Z,N,V,S 1 OR Rd, Rr Logical OR Rd  Rd v Rr Z,N,V,S 1 ORI Rd, K Logical OR with Immediate Rd  Rd v K Z,N,V,S 1 EOR Rd, Rr Exclusive OR Rd  Rd  Rr Z,N,V,S 1 COM Rd One’s Complement Rd  $FF - Rd Z,C,N,V,S 1 NEG Rd Two’s Complement Rd  $00 - Rd Z,C,N,V,S,H 1 SBR Rd,K Set Bit(s) in Register Rd  Rd v K Z,N,V,S 1 CBR Rd,K Clear Bit(s) in Register Rd  Rd  ($FFh - K) Z,N,V,S 1 INC Rd Increment Rd  Rd + 1 Z,N,V,S 1 DEC Rd Decrement Rd  Rd - 1 Z,N,V,S 1 TST Rd Test for Zero or Minus Rd  Rd  Rd Z,N,V,S 1 CLR Rd Clear Register Rd  Rd  Rd Z,N,V,S 1 SER Rd Set Register Rd  $FF None 1 MUL Rd,Rr Multiply Unsigned R1:R0  Rd x Rr (UU) Z,C 2 MULS Rd,Rr Multiply Signed R1:R0  Rd x Rr (SS) Z,C 2 MULSU Rd,Rr Multiply Signed with Unsigned R1:R0  Rd x Rr (SU) Z,C 2 FMUL Rd,Rr Fractional Multiply Unsigned R1:R0  Rd x Rr<<1 (UU) Z,C 2 FMULS Rd,Rr Fractional Multiply Signed R1:R0  Rd x Rr<<1 (SS) Z,C 2 FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0  Rd x Rr<<1 (SU) Z,C 2 DES K Data Encryption if (H = 0) then R15:R0 else if (H = 1) then R15:R0   Encrypt(R15:R0, K) Decrypt(R15:R0, K) 1/2 Branch Instructions RJMP k Relative Jump PC  PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC(15:0) PC(21:16)   Z, 0 None 2 EIJMP Extended Indirect Jump to (Z) PC(15:0) PC(21:16)   Z, EIND None 2 JMP k Jump PC  k None 3[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 66 8067O–AVR–06/2013 RCALL k Relative Call Subroutine PC  PC + k + 1 None 2 / 3(1) ICALL Indirect Call to (Z) PC(15:0) PC(21:16)   Z, 0 None 2 / 3(1) EICALL Extended Indirect Call to (Z) PC(15:0) PC(21:16)   Z, EIND None 3(1) CALL k call Subroutine PC  k None 3 / 4(1) RET Subroutine Return PC  STACK None 4 / 5(1) RETI Interrupt Return PC  STACK I 4 / 5(1) CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC  PC + 2 or 3 None 1 / 2 / 3 CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1 CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1 CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC  PC + 2 or 3 None 1 / 2 / 3 SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC  PC + 2 or 3 None 1 / 2 / 3 SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC  PC + 2 or 3 None 2 / 3 / 4 SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC  PC + 2 or 3 None 2 / 3 / 4 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC  PC + k + 1 None 1 / 2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC  PC + k + 1 None 1 / 2 BREQ k Branch if Equal if (Z = 1) then PC  PC + k + 1 None 1 / 2 BRNE k Branch if Not Equal if (Z = 0) then PC  PC + k + 1 None 1 / 2 BRCS k Branch if Carry Set if (C = 1) then PC  PC + k + 1 None 1 / 2 BRCC k Branch if Carry Cleared if (C = 0) then PC  PC + k + 1 None 1 / 2 BRSH k Branch if Same or Higher if (C = 0) then PC  PC + k + 1 None 1 / 2 BRLO k Branch if Lower if (C = 1) then PC  PC + k + 1 None 1 / 2 BRMI k Branch if Minus if (N = 1) then PC  PC + k + 1 None 1 / 2 BRPL k Branch if Plus if (N = 0) then PC  PC + k + 1 None 1 / 2 BRGE k Branch if Greater or Equal, Signed if (N  V= 0) then PC  PC + k + 1 None 1 / 2 BRLT k Branch if Less Than, Signed if (N  V= 1) then PC  PC + k + 1 None 1 / 2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC  PC + k + 1 None 1 / 2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC  PC + k + 1 None 1 / 2 BRTS k Branch if T Flag Set if (T = 1) then PC  PC + k + 1 None 1 / 2 BRTC k Branch if T Flag Cleared if (T = 0) then PC  PC + k + 1 None 1 / 2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC  PC + k + 1 None 1 / 2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC  PC + k + 1 None 1 / 2 BRIE k Branch if Interrupt Enabled if (I = 1) then PC  PC + k + 1 None 1 / 2 BRID k Branch if Interrupt Disabled if (I = 0) then PC  PC + k + 1 None 1 / 2 Data Transfer Instructions MOV Rd, Rr Copy Register Rd  Rr None 1 MOVW Rd, Rr Copy Register Pair Rd+1:Rd  Rr+1:Rr None 1 Mnemonics Operands Description Operation Flags #Clocks[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 67 8067O–AVR–06/2013 LDI Rd, K Load Immediate Rd  K None 1 LDS Rd, k Load Direct from data space Rd  (k) None 2(1)(2) LD Rd, X Load Indirect Rd  (X) None 1(1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd X   (X) X + 1 None 1(1)(2) LD Rd, -X Load Indirect and Pre-Decrement X  X - 1, Rd  (X)   X - 1 (X) None 2(1)(2) LD Rd, Y Load Indirect Rd  (Y)  (Y) None 1(1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd Y   (Y) Y + 1 None 1(1)(2) LD Rd, -Y Load Indirect and Pre-Decrement Y Rd   Y - 1 (Y) None 2(1)(2) LDD Rd, Y+q Load Indirect with Displacement Rd  (Y + q) None 2(1)(2) LD Rd, Z Load Indirect Rd  (Z) None 1(1)(2) LD Rd, Z+ Load Indirect and Post-Increment Rd Z   (Z), Z+1 None 1(1)(2) LD Rd, -Z Load Indirect and Pre-Decrement Z Rd   Z - 1, (Z) None 2(1)(2) LDD Rd, Z+q Load Indirect with Displacement Rd  (Z + q) None 2(1)(2) STS k, Rr Store Direct to Data Space (k)  Rd None 2(1) ST X, Rr Store Indirect (X)  Rr None 1(1) ST X+, Rr Store Indirect and Post-Increment (X) X   Rr, X + 1 None 1(1) ST -X, Rr Store Indirect and Pre-Decrement X (X)   X - 1, Rr None 2(1) ST Y, Rr Store Indirect (Y)  Rr None 1(1) ST Y+, Rr Store Indirect and Post-Increment (Y) Y   Rr, Y + 1 None 1(1) ST -Y, Rr Store Indirect and Pre-Decrement Y (Y)   Y - 1, Rr None 2(1) STD Y+q, Rr Store Indirect with Displacement (Y + q)  Rr None 2(1) ST Z, Rr Store Indirect (Z)  Rr None 1(1) ST Z+, Rr Store Indirect and Post-Increment (Z) Z   Rr Z + 1 None 1(1) ST -Z, Rr Store Indirect and Pre-Decrement Z  Z - 1 None 2(1) STD Z+q,Rr Store Indirect with Displacement (Z + q)  Rr None 2(1) LPM Load Program Memory R0  (Z) None 3 LPM Rd, Z Load Program Memory Rd  (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Increment Rd Z   (Z), Z + 1 None 3 ELPM Extended Load Program Memory R0  (RAMPZ:Z) None 3 ELPM Rd, Z Extended Load Program Memory Rd  (RAMPZ:Z) None 3 ELPM Rd, Z+ Extended Load Program Memory and PostIncrement Rd Z   (RAMPZ:Z), Z + 1 None 3 SPM Store Program Memory (RAMPZ:Z)  R1:R0 None - Mnemonics Operands Description Operation Flags #Clocks[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 68 8067O–AVR–06/2013 SPM Z+ Store Program Memory and Post-Increment by 2 (RAMPZ:Z) Z   R1:R0, Z + 2 None - IN Rd, A In From I/O Location Rd  I/O(A) None 1 OUT A, Rr Out To I/O Location I/O(A)  Rr None 1 PUSH Rr Push Register on Stack STACK  Rr None 1(1) POP Rd Pop Register from Stack Rd  STACK None 2(1) Bit and Bit-test Instructions LSL Rd Logical Shift Left Rd(n+1) Rd(0) C    Rd(n), 0, Rd(7) Z,C,N,V,H 1 LSR Rd Logical Shift Right Rd(n) Rd(7) C    Rd(n+1), 0, Rd(0) Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0) Rd(n+1) C    C, Rd(n), Rd(7) Z,C,N,V,H 1 ROR Rd Rotate Right Through Carry Rd(7) Rd(n) C    C, Rd(n+1), Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n)  Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)  Rd(7..4) None 1 BSET s Flag Set SREG(s)  1 SREG(s) 1 BCLR s Flag Clear SREG(s)  0 SREG(s) 1 SBI A, b Set Bit in I/O Register I/O(A, b)  1 None 1 CBI A, b Clear Bit in I/O Register I/O(A, b)  0 None 1 BST Rr, b Bit Store from Register to T T  Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b)  T None 1 SEC Set Carry C  1 C 1 CLC Clear Carry C  0 C 1 SEN Set Negative Flag N  1 N 1 CLN Clear Negative Flag N  0 N 1 SEZ Set Zero Flag Z  1 Z 1 CLZ Clear Zero Flag Z  0 Z 1 SEI Global Interrupt Enable I  1 I 1 CLI Global Interrupt Disable I  0 I 1 SES Set Signed Test Flag S  1 S 1 CLS Clear Signed Test Flag S  0 S 1 SEV Set Two’s Complement Overflow V  1 V 1 CLV Clear Two’s Complement Overflow V  0 V 1 SET Set T in SREG T  1 T 1 CLT Clear T in SREG T  0 T 1 SEH Set Half Carry Flag in SREG H  1 H 1 CLH Clear Half Carry Flag in SREG H  0 H 1 Mnemonics Operands Description Operation Flags #Clocks[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 69 8067O–AVR–06/2013 Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. 2. One extra cycle must be added when accessing Internal SRAM. MCU Control Instructions BREAK Break (See specific descr. for BREAK) None 1 NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep) None 1 WDR Watchdog Reset (see specific descr. for WDR) None 1 Mnemonics Operands Description Operation Flags #Clocks[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 70 8067O–AVR–06/2013 33. Packaging information 33.1 100A 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 100A D 2010-10-20 PIN 1 IDENTIFIER 0°~7° PIN 1 L C A1 A2 A D1 D e E1 E B A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 Note 2 B 0.17 – 0.27 C 0.09 – 0.20 L 0.45 – 0.75 e 0.50 TYP Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 71 8067O–AVR–06/2013 33.2 100C1 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 100C1, 100-ball, 9 x 9 x 1.2 mm Body, Ball Pitch 0.80 mm Chip Array BGA Package (CBGA) 100C1 A 5/25/06 TOP VIEW SIDE VIEW BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 1.10 – 1.20 A1 0.30 0.35 0.40 D 8.90 9.00 9.10 E 8.90 9.00 9.10 D1 7.10 7.20 7.30 E1 7.10 7.20 7.30 Øb 0.35 0.40 0.45 e 0.80 TYP Marked A1 Identifier 8 7 6 5 4 3 2 1 A B C D E 9 F G H I J 10 0.90 TYP 0.90 TYP A1 Corner 0.12 Z E D e e Øb A A1 E1 D1[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 72 8067O–AVR–06/2013 33.3 100C2 TITLE GPC DRAWING NO. REV. Package Drawing Contact: packagedrawings@atmel.com CIF A 100C2 100C2, 100-ball (10 x 10 Array), 0.65 mm Pitch, 7.0 x 7.0 x 1.0 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) 12/23/08 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 1.00 A1 0.20 – – A2 0.65 – – D 6.90 7.00 7.10 D1 5.85 BSC E 6.90 7.00 7.10 E1 5.85 BSC b 0.30 0.35 0.40 e 0.65 BSC TOP VIEW SIDE VIEW A1 BALL ID J I H G F E D C B A 12 3 4 5 6 7 8 9 10 A A1 A2 D E 0.10 E1 D1 100 - Ø0.35 ± 0.05 e A1 BALL CORNER BOTTOM VIEW b e[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 73 8067O–AVR–06/2013 34. Electrical Characteristics 34.1 Absolute Maximum Ratings* 34.2 DC Characteristics Table 34-1. Current consumption. Operating Temperature . . . . . . . . . . . -55C to +125C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature . . . . . . . . . . . . . -65C to +150°C Voltage on any Pin with respect to Ground-0.5V to VCC+0.5V Maximum Operating Voltage . . . . . . . . . . . . . . . . 3.6V DC Current per I/O Pin. . . . . . . . . . . . . . . . . . 20.0 mA DC Current VCC and GND Pins . . . . . . . . . . 200.0 mA Symbol Parameter Condition Min Typ Max Units ICC Active mode(1) 1 MHz, Ext. Clk VCC = 1.8V 365 µA VCC = 3.0V 790 2 MHz, Ext. Clk VCC = 1.8V 690 800 VCC = 3.0V 1400 1600 32 MHz, Ext. Clk VCC = 3.0V 18.35 20 mA Idle mode(1) 1 MHz, Ext. Clk VCC = 1.8V 135 µA VCC = 3.0V 255 2 MHz, Ext. Clk VCC = 1.8V 270 380 VCC = 3.0V 510 650 32 MHz, Ext. Clk VCC = 3.0V 8.15 9.2 mA Power-down mode All Functions Disabled VCC = 3.0V 0.1 µA All Functions Disabled, T = 85°C VCC = 3.0V 2 5 ULP, WDT, Sampled BOD VCC = 1.8V 0.5 VCC = 3.0V 0.6 ULP, WDT, Sampled BOD, T=85°C VCC = 3.0V 3 10 Power-save mode RTC 1 kHz from Low Power 32 kHz VCC = 1.8V 0.52 VCC = 3.0V 0.55 µA RTC from Low Power 32 kHz VCC = 3.0V 1.16[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 74 8067O–AVR–06/2013 Note: 1. All Power Reduction Registers set. Typical numbers measured at T = 25°C if nothing else is specified. 2. with no prescaling Module current consumption(2) ICC RC32M 395 µA RC32M w/DFLL Internal 32.768 kHz oscillator as DFLL source TBD RC2M 120 RC2M w/DFLL Internal 32.768 kHz oscillator as DFLL source 155 RC32K 30 PLL Multiplication factor = 10x 195 Watchdog normal mode TBD BOD Continuous mode 120 BOD Sampled mode 1 Internal 1.00 V ref 85 Temperature reference 80 RTC with int. 32 kHz RC as source No prescaling 30 RTC with ULP as source No prescaling 1 ADC 250 kS/s - Int. 1V Ref 3.6 DAC Normal Mode 1000 kS/s, Single channel, Int. 1V Ref 1.8 mA DAC Low-Power Mode 1000 KS/s, Single channel, Int. 1V Ref 1 AC High-speed 220 µA AC Low-power 110 USART Rx and Tx enabled, 9600 BAUD 7.5 DMA 180 Timer/Counter Prescaler DIV1 18 AES 195 Flash/EEPROM Programming Vcc = 2V 20 mA Vcc = 3V 30 Symbol Parameter Condition Min Typ Max Units[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 75 8067O–AVR–06/2013 34.3 Speed Table 34-2. Operating voltage and frequency. The maximum CPU clock frequency of the XMEGA A1 devices is depending on VCC. As shown in Figure 34-1 on page 75 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 34-1. Maximum Frequency vs. Vcc Symbol Parameter Condition Min Typ Max Units ClkCPU CPU clock frequency VCC = 1.6V 0 12 MHz VCC = 1.8V 0 12 VCC = 2.7V 0 32 VCC = 3.6V 0 32 1.8 12 32 MHz 1.6 2.7 3.6 V Safe Operating Area[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 76 8067O–AVR–06/2013 34.4 Flash and EEPROM Memory Characteristics Table 34-3. Endurance and data retention. Table 34-4. Programming time. Notes: 1. Programming is timed from the internal 2 MHz oscillator. 2. EEPROM is not erased if the EESAVE fuse is programmed. 34.5 ADC Characteristics Table 34-5. ADC characteristics Symbol Parameter Condition Min Typ Max Units Flash Write/Erase cycles 25°C 10K Cycle 85°C 10K Data retention 25°C 100 Year 55°C 25 EEPROM Write/Erase cycles 25°C 80K Cycle 85°C 30K Data retention 25°C 100 Year 55°C 25 Symbol Parameter Condition Min Typ(1) Max Units Chip Erase Flash, EEPROM(2) and SRAM Erase 40 ms Flash Page Erase 4 Page Write 6 Page WriteAutomatic Page Erase and Write 12 EEPROM Page Erase 4 Page Write 6 Page Write Automatic Page Erase and Write 12 Symbol Parameter Condition Min Typ Max Units RES Resolution Programmable: 8/12 8 12 12 Bits INL Integral Non-Linearity 500 kS/s -5 <±1 5 LSB DNL Differential Non-Linearity 500 kS/s < ±0.75 LSB Gain Error ±10 mV Offset Error ±2 mV ADCclk ADC Clock frequency Max is 1/4 of Peripheral Clock VCC2.0V 2000 kHz VCC<2.0V 500[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 77 8067O–AVR–06/2013 Table 34-6. ADC gain stage characteristics. Conversion rate VCC2.0V 2000 ksps VCC<2.0V 500 Conversion time (propagation delay) (RES+2)/2+GAIN RES = 8 or 12, GAIN = 0 or 1 5 7 8 ADCclk cycles Sampling Time 1/2 ADCclk cycle 0.25 µS Conversion range 0 VREF V AVCC Analog Supply Voltage Vcc-0.3 Vcc+0.3 V VREF Reference voltage 1.0 Vcc-0.6 V Input bandwidth VCC2.0V 2000 kHz VCC<2.0V 500 INT1V Internal 1.00V reference 1.00 V INTVCC Internal VCC/1.6 VCC/1.6 V SCALEDVCC Scaled internal VCC/10 input VCC/10 V RAREF Reference input resistance >10 M Start-up time 12 24 ADCclk cycles Internal input sampling speed Temp. sensor, VCC/10, Bandgap 100 ksps Symbol Parameter Condition Min Typ Max Units Gain error 1 to 64 gain < ±1 % Offset error < ±1 mV Vrms Noise level at input 64x gain VREF = Int. 1V 0.12 mV VREF = Ext. 2V 0.06 Clock rate Same as ADC 1000 kHz Symbol Parameter Condition Min Typ Max Units[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 78 8067O–AVR–06/2013 34.6 DAC Characteristics Table 34-7. DAC characteristics. 34.7 Analog Comparator Characteristics Table 34-8. Analog Comparator characteristics. 34.8 Bandgap Characteristics Table 34-9. Bandgap voltage characteristics. Symbol Parameter Condition Min Typ Max Units INL Integral Non-Linearity VCC = 1.6-3.6V VREF = Ext. ref 5 LSB DNL Differential Non-Linearity VCC = 1.6-3.6V VREF = Ext. ref 0.6 <±1 LSB VREF= AVCC 0.6 Fclk Conversion rate 1000 ksps AREF External reference voltage 1.1 AVCC-0.6 V Reference input impedance >10 M Max output voltage Rload=100k AVCC*0.98 V Min output voltage Rload=100k 0.01 V Symbol Parameter Condition Min Typ Max Units Voff Input Offset Voltage VCC = 1.6 - 3.6V <±5 mV Ilk Input Leakage Current VCC = 1.6 - 3.6V < 1000 pA Vhys1 Hysteresis, No VCC = 1.6 - 3.6V 0 mV Vhys2 Hysteresis, Small VCC = 1.6 - 3.6V mode = HS 25 mV Vhys3 Hysteresis, Large VCC = 1.6 - 3.6V mode = HS 50 mV tdelay Propagation delay VCC = 3.0V, T= 85°C mode = HS 100 V ns CC = 1.6 - 3.6V mode = HS 70 VCC = 1.6 - 3.6V mode = LP 140 Symbol Parameter Condition Min Typ Max Units Bandgap startup time As reference for ADC or DAC 1 Clk_PER + 2.5µs µs Bandgap voltage 1.1 V[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 79 8067O–AVR–06/2013 34.9 Brownout Detection Characteristics Table 34-10. Brownout Detection characteristics. Note: 1. BOD is calibrated to BOD level 0 at 85°C, and BOD level 0 is the default level. 34.10 PAD Characteristics Table 34-11. PAD characteristics. ADC/DAC ref T= 85°C, After calibration 0.99 1.01 V 1 Variation over voltage and temperature VCC = 1.6 - 3.6V, T = -40C to 85C ±5 % Symbol Parameter Condition Min Typ Max Units Symbol Parameter Condition Min Typ Max Units BOD level 0 falling Vcc 1.6 V BOD level 1 falling Vcc 1.9 BOD level 2 falling Vcc 2.1 BOD level 3 falling Vcc 2.4 BOD level 4 falling Vcc 2.6 BOD level 5 falling Vcc 2.9 BOD level 6 falling Vcc 3.2 BOD level 7 falling Vcc 3.4 Hysteresis BOD level 0-5 2 % Symbol Parameter Condition Min Typ Max Units VIH Input High Voltage VCC = 2.4 - 3.6V 0.7*VCC VCC+0.5 V VCC = 1.6 - 2.4V 0.8*VCC VCC+0.5 VIL Input Low Voltage VCC = 2.4 - 3.6V -0.5 0.3*VCC V VCC = 1.6 - 2.4V -0.5 0.2*VCC VOL Output Low Voltage GPIO IOL = 15 mA, VCC = 3.3V 0.45 0.76 IOL = 10 mA, VCC = 3.0V 0.3 0.64 V IOL= 5 mA, VCC = 1.8V 0.2 0.46[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 80 8067O–AVR–06/2013 34.11 POR Characteristics Table 34-12. Power-on Reset characteristics. 34.12 Reset Characteristics Table 34-13. Reset characteristics. 34.13 Oscillator Characteristics Table 34-14. Internal 32.768kHz oscillator characteristics. VOH Output High Voltage GPIO IOH = -8 mA, VCC = 3.3V 2.6 3 IOH = -6 mA, VCC = 3.0V 2.1 2.2 V IOH = -2 mA, VCC = 1.8V 1.4 1.6 IIL Input Leakage Current I/O pin <0.001 1 µA IIH Input Leakage Current I/O pin <0.001 1 µA RP I/O pin Pull/Buss keeper Resistor 20 k RRST Reset pin Pull-up Resistor 20 k Input hysteresis 0.5 V Symbol Parameter Condition Min Typ Max Units Symbol Parameter Condition Min Typ Max Units VPOT- POR threshold voltage falling Vcc 1 V VPOT+ POR threshold voltage rising Vcc 1.4 V Symbol Parameter Condition Min Typ Max Units Minimum reset pulse width 90 ns Reset threshold voltage VCC = 2.7 - 3.6V 0.45*VCC V VCC = 1.6 - 2.7V 0.42*VCC Symbol Parameter Condition Min Typ Max Units Accuracy T = 85C, VCC = 3V, After production calibration -0.5 0.5 %[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 81 8067O–AVR–06/2013 Table 34-15. Internal 2MHz oscillator characteristics. Table 34-16. Internal 32MHz oscillator characteristics. Table 34-17. Internal 32kHz, ULP oscillator characteristics. Table 34-18. Maximum load capacitance (CL) and ESR recommendation for 32.768kHz crystal. Table 34-19. Device wake-up time from sleep. Notes: 1. Non-prescaled System Clock source. 2. Time from pin change on external interrupt pin to first available clock cycle. Additional interrupt response time is minimum 5 system clock source cycles. Symbol Parameter Condition Min Typ Max Units Accuracy T = 85C, VCC = 3V, After production calibration -1.5 1.5 % DFLL Calibration step size T = 25C, VCC = 3V 0.175 % Symbol Parameter Condition Min Typ Max Units Accuracy T = 85C, VCC = 3V, After production calibration -1.5 1.5 % DFLL Calibration stepsize T = 25C, VCC = 3V 0.2 % Symbol Parameter Condition Min Typ Max Units Output frequency 32 kHz ULP OSC T = 85C, VCC = 3.0V 26 kHz Crystal CL [pF] Max ESR [k] 6.5 60 9 35 Symbol Parameter Condition(1) Min Typ(2) Max Units Idle Sleep, Standby and Extended Standby sleep mode Int. 32.768 kHz RC 130 µS Int. 2 MHz RC 2 Ext. 2 MHz Clock 2 Int. 32 MHz RC 0.17 Power-save and Power-down Sleep mode Int. 32.768 kHz RC 320 Int. 2 MHz RC 10.3 Ext. 2 MHz Clock 4.5 Int. 32 MHz RC 5.8[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 82 8067O–AVR–06/2013 35. Typical Characteristics 35.1 Active Supply Current Figure 35-1. Active Supply Current vs. Frequency fSYS = 1 - 32 MHz, T = 25°C Figure 35-2. Active Supply Current vs. VCC fSYS = 1.0 MHz 3.3V 3.0V 2.7V 0 5 10 15 20 25 0 4 8 12 16 20 24 28 32 Frequency [MHz] Icc [mA] 1.8V 2.2V 85°C 25°C -40°C 0 200 400 600 800 1000 1200 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Icc [uA][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 83 8067O–AVR–06/2013 35.2 Idle Supply Current Figure 35-3. Idle Supply Current vs. Frequency fSYS = 1 - 32 MHz, T = 25°C Figure 35-4. Active Supply Current vs. VCC fSYS = 1.0 MHz , 3.3V 3.0V 2.7V 0 1 2 3 4 5 6 7 8 9 10 0 4 8 12 16 20 24 28 32 Frequency [MHz] Icc [mA] 1.8V 2.2V 85°C 25°C -40°C 0 50 100 150 200 250 300 350 400 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Icc [uA][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 84 8067O–AVR–06/2013 35.3 Power-down Supply Current Figure 35-5. Power-down Supply Current vs. Temperature 35.4 Power-save Supply Current Figure 35-6. Power-save Supply Current vs. Temperature Sampled BOD, WDT, RTC from ULP enabled 3.3V 3.0V 2.7V 2.2V 1.8V 0 0.5 1 1.5 2 2.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Icc [uA] 3.3V 2.7V 2.2V 1.8V 0 0.5 1 1.5 2 2.5 3 3.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Icc [uA][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 85 8067O–AVR–06/2013 35.5 Pin Pull-up Figure 35-7. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 1.8V Figure 35-8. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 3.0V 85 °C 25 °C -40 °C 0 20 40 60 80 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 vreset [V] Ireset [uA] 85 °C 25 °C -40 °C 0 20 40 60 80 100 120 140 160 180 0 0.5 1 1.5 2 2.5 vreset [V] Ireset [uA][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 86 8067O–AVR–06/2013 Figure 35-9. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 3.3V 35.6 Pin Thresholds and Hysteresis Figure 35-10.I/O Pin Input Threshold Voltage vs. VCC VIH - I/O Pin Read as “1” 85 °C 25 °C -40 °C 0 20 40 60 80 100 120 140 160 180 0 0.5 1 1.5 2 2.5 3 vreset [V] Ireset [uA] 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Vthreshold [V][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 87 8067O–AVR–06/2013 Figure 35-11.I/O Pin Input Threshold Voltage vs. VCC VIL - I/O Pin Read as “0” Figure 35-12.I/O Pin Input Hysteresis vs. VCC. 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Vthreshold [V] 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Vthreshold [V][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 88 8067O–AVR–06/2013 Figure 35-13.Reset Input Threshold Voltage vs. VCC VIH - I/O Pin Read as “1” Figure 35-14.Reset Input Threshold Voltage vs. VCC VIL - I/O Pin Read as “0” 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Vthreshold [V] 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Vthreshold [V][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 89 8067O–AVR–06/2013 35.7 Bod Thresholds Figure 35-15.BOD Thresholds vs. Temperature BOD Level = 1.6V Figure 35-16.BOD Thresholds vs. Temperature BOD Level = 2.9V Rising Vcc Falling Vcc 1.602 1.608 1.614 1.62 1.626 1.632 1.638 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] VBOT [V] Rising Vcc Falling Vcc 2.905 2.92 2.935 2.95 2.965 2.98 2.995 3.01 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] VBOT [V][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 90 8067O–AVR–06/2013 35.8 Bandgap Figure 35-17.Internal 1.00V Reference vs. Temperature. 35.9 Analog Comparator Figure 35-18.Analog Comparator Hysteresis vs. VCC High-speed, Small hysteresis 3.0V 1.8V 0.999 0.9995 1 1.0005 1.001 1.0015 1.002 1.0025 1.003 1.0035 1.004 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] VREF [V] 25°C 0 5 10 15 20 25 30 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Hysteresis [mV][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 91 8067O–AVR–06/2013 Figure 35-19.Analog Comparator Hysteresis vs. VCC, High-speed Large hysteresis Figure 35-20.Analog Comparator Propagation Delay vs. VCC High-speed 25°C 0 10 20 30 40 50 60 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Hysteresis [mV] 25°C 0 20 40 60 80 100 120 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Propagation Delay [ns][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 92 8067O–AVR–06/2013 35.10 Oscillators and Wake-up Time Figure 35-21.Internal 32.768 kHz Oscillator Frequency vs. Temperature 1.024 kHz output Figure 35-22.Ultra Low-Power (ULP) Oscillator Frequency vs. Temperature 1 kHz output p 3.0 V 1.8 V 0.99 0.995 1 1.005 1.01 1.015 1.02 1.025 1.03 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 T [°C] f [kHz] p 3.0 V 1.8 V 0.87 0.88 0.89 0.9 0.91 0.92 0.93 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 T [°C] f1kHz output [kHz][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 93 8067O–AVR–06/2013 Figure 35-23.Internal 2 MHz Oscillator CalA Calibration Step Size T = -40 to 85C, VCC = 3V Figure 35-24.Internal 2 MHz Oscillator CalB Calibration Step Size T = -40 to 85C, VCC = 3V 0 0.001 0.002 0.003 0.004 0.005 0.006 0 20 40 60 80 100 120 140 CALA [LSB] Step size: f [MHz] 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0 10 20 30 40 50 60 70 CALB [LSB] Step size: f [MHz][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 94 8067O–AVR–06/2013 Figure 35-25.Internal 32 MHz Oscillator CalA Calibration Step Size T = -40 to 85C, VCC = 3V Figure 35-26.Internal 32 MHz Oscillator CalB Calibration Step Size T = -40 to 85C, VCC = 3V 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0 20 40 60 80 100 120 140 CALA Step size: f [MHz] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 10 20 30 40 50 60 70 CALB Step size: f [MHz][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 95 8067O–AVR–06/2013 35.11 PDI Speed Figure 35-27.PDI Speed vs. VCC 25 °C 0 5 10 15 20 25 30 35 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] fMAX [MHz][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 96 8067O–AVR–06/2013 36. Errata 36.1 ATxmega64A1and ATxmega128A1 rev. H  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  The ADC has up to ±2 LSB inaccuracy  ADC gain stage output range is limited to 2.4 V  Sampling speed limited to 500 ksps for supply voltage below 2.0V  ADC Event on compare match non-functional  Bandgap measurement with the ADC is non-functional when VCC is below 2.7V  Accuracy lost on first three samples after switching input to ADC gain stage  The input difference between two succeeding ADC samples is limited by VREF  Increased noise when using internal 1.0V reference at low temperature  Configuration of PGM and CWCM not as described in XMEGA A Manual  PWM is not restarted properly after a fault in cycle-by-cycle mode  BOD will be enabled at any reset  BODACT fuse location is not correct  Sampled BOD in Active mode will cause noise when bandgap is used as reference  DAC has up to ±10 LSB noise in Sampled Mode  DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V  DAC refresh may be blocked in S/H mode  Conversion lost on DAC channel B in event triggered mode  Both DFLLs and both oscillators have to be enabled for one to work  Access error when multiple bus masters are accessing SDRAM  EEPROM page buffer always written when NVM DATA0 is written  Pending full asynchronous pin change interrupts will not wake the device  Pin configuration does not affect Analog Comparator Output  Low level interrupt triggered when pin input is disabled  JTAG enable does not override Analog Comparator B output  NMI Flag for Crystal Oscillator Failure automatically cleared  Flash Power Reduction Mode can not be enabled when entering sleep  Some NVM Commands are non-functional  Crystal start-up time required after power-save even if crystal is source for RTC  Setting PRHIRES bit makes PWM output unavailable  Accessing EBI address space with PREBI set will lock Bus Master  RTC Counter value not correctly read after sleep  Pending asynchronous RTC-interrupts will not wake up device  TWI, the minimum I2C SCL low time could be violated in Master Read mode  TWI address-mask feature is non-functional  TWI, a general address call will match independent of the R/W-bit value  TWI Transmit collision flag not cleared on repeated start  Clearing TWI Stop Interrupt Flag may lock the bus[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 97 8067O–AVR–06/2013  TWI START condition at bus timeout will cause transaction to be dropped  TWI Data Interrupt Flag erroneously read as set  WDR instruction inside closed window will not issue reset 1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1 µs and could potentially give a wrong comparison result. Problem fix/Workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. VCC voltage scaler for AC is non-linear The 6-bit VCC voltage scaler in the Analog Comparators is non-linear. Figure 36-1. Analog Comparator Voltage Scaler vs. Scalefac T = 25°C Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. The ADC has up to ±2 LSB inaccuracy The ADC will have up to ±2 LSB inaccuracy, visible as a saw-tooth pattern on the input voltage/ output value transfer function of the ADC. The inaccuracy increases with increasing voltage reference reaching ±2 LSB with 3V reference. 3.3 V 2.7 V 1.8 V 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC VSCALE [V][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 98 8067O–AVR–06/2013 Problem fix/Workaround None, the actual ADC resolution will be reduced with up to ±2 LSB. 4. ADC gain stage output range is limited to 2.4 V The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of: Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V. 5. Sampling speed limited to 500 ksps for supply voltage below 2.0V The sampling frequency is limited to 500 ksps for supply voltage below 2.0V. At higher sampling rate the INL error will be several hundred LSB. Problem fix/Workaround None. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE. Problem fix/Workaround Enable and use interrupt on compare match when using the compare function. 7. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V The ADC can not be used to do bandgap measurements when VCC is below 2.7V. Problem fix/Workaround – 1x gain: 2.4 V – 2x gain: 1.2 V – 4x gain: 0.6 V – 8x gain: 300 mV – 16x gain: 150 mV – 32x gain: 75 mV – 64x gain: 38 mV[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 99 8067O–AVR–06/2013 None. 8. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/Workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 9. The input difference between two succeeding ADC samples is limited by VREF If the difference in input between two samples changes more than the size of the reference, the ADC will not be able to convert the data correctly. Two conversions will be required before the conversion is correct. Problem fix/Workaround Discard the first conversion if input is changed more than VREF, or ensure that the input never changes more then VREF. 10. Increased noise when using internal 1.0V reference at low temperature When operating at below 0C and using internal 1.0V reference the RMS noise will be up 4 LSB, Peak-to-peak noise up to 25 LSB. Problem fix/Workaround Use averaging to remove noise. 11. Configuration of PGM and CWCM not as described in XMEGA A Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. Problem fix/Workaround 12 PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 100 8067O–AVR–06/2013 Problem fix/Workaround Do a write to any AWeX I/O register to re-enable the output. 13. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed BOD level even if the BOD is disabled. Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 14. BODACT fuse location is not correct The fuses for enabling BOD in active mode (BODACT) are located at FUSEBYTE2, bit 2 and 3 and not in FUSEBYTE 5 as described in the XMEGA A Manual. Problem fix/Workaround Access the fuses in FUSEBYTE2. 15. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/Workaround If the bandgap is used as reference for either the ADC, DAC or Analog Comparator, the BOD must not be set in sampled mode. 16. DAC has up to ±10 LSB noise in Sampled Mode The DAC has noise of up to ±10 LSB in Sampled Mode for entire operation range. Problem fix/Workaround Use the DAC in continuous mode. 17. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate output when converting codes that give below 0.75V output:  ±10 LSB for continuous mode  ±200 LSB for Sample and Hold mode Problem fix/Workaround None.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 101 8067O–AVR–06/2013 18. DAC has up to ±10 LSB noise in Sampled Mode If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this will block refresh signals to the second channel. Problem fix/Workaround When using the DAC in S/H mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 19. Conversion lost on DAC channel B in event triggered mode If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1 conversions are occasionally lost. This means that not all data-values written to the Channel 1 data register are converted. Problem fix/Workaround Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Peripheral clock frequency so the conversion internal never is shorter than 1.5 µs. 20. Both DFLLs and both oscillators have to be enabled for one to work In order to use the automatic runtime calibration for the 2 MHz or the 32 MHz internal oscillators, the DFLL for both oscillators and both oscillators have to be enabled for one to work. Problem fix/Workaround Enable both DFLLs and both oscillators when using automatic runtime calibration for either of the internal oscillators. 21. Access error when multiple bus masters are accessing SDRAM If one bus master (CPU and DMA channels) is using the EBI to access an SDRAM in burst mode and another bus master is accessing the same row number in a different BANK of the SDRAM in the cycle directly after the burst access is complete, the access for the second bus master will fail. Problem fix/Workaround Do not put stack pointer in SDRAM and use DMA Controller in 1 byte burst mode if CPU and DMA Controller are required to access SDRAM at the same time. 22. EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/Workaround Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set. 23. Pending full asynchronous pin change interrupts will not wake the device[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 102 8067O–AVR–06/2013 Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/Workaround None. 24. Pin configuration does not affect Analog Comparator Output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output function. Problem fix/Workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. 25. Low level interrupt triggered when pin input is disabled If a pin input is disabled, but pin is configured to trigger on low level, interrupt request will be sent. Problem fix/Workaround Ensure that Interrupt mask for the disabled pin is cleared. 26. JTAG enable does not override Analog Comparator B output When JTAG is enabled this will not override the Analog Comparator B (ACB) output, AC0OUT on pin 7 if this is enabled. Problem fix/Workaround Use Analog Comparator output for ACA when JTAG is used, or use the PDI as debug interface. 27. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 28. Flash Power Reduction Mode can not be enabled when entering sleep If Flash Power Reduction Mode is enabled when entering Power-save or Extended Standby sleep mode, the device will only wake up on every fourth wake-up request. If Flash Power Reduction Mode is enabled when entering Idle sleep mode, the wake-up time will vary with up to 16 CPU clock cycles.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 103 8067O–AVR–06/2013 Problem fix/Workaround Disable Flash Power Reduction mode before entering sleep mode. 29. Some NVM Commands are non-functional The following NVM commands are non-functional: Problem fix/Workaround None for Flash Range CRC Use separate programming commands for accessing application and boot section. 30. Crystal start-up time required after power-save even if crystal is source for RTC Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscillator Selection" in XMEGA A Manual. If BOD is used in active mode, the BOD will be on during this period (0.5s). Problem fix/Workaround If faster start-up is required, go to sleep with internal oscillator as system clock. 31. Setting PRHIRES bit makes PWM output unavailable Setting the HIRES Power Reduction (PR) bit for PORTx will make any Frequency or PWM output for the corresponding Timer/Counters (TCx0 and TCx1) unavailable on the pin even if the Hi-Res is not used. Problem fix/Workaround Do not write the HIRES PR bit on PORTx when frequency or PWM output from TCx0/1 is used. – 0x2B Erase Flash Page – 0x2E Write Flash Page – 0x2F Erase & Write Flash Page – 0x3A Flash Range CRC – 0x22 Erase Application Section Page – 0x24 Write Application Section Page – 0x25 Erase & Write Application Section Page – 0x2A Erase Boot Loader Section Page – 0x2C Write Boot Loader Section Page – 0x2D Erase & Write Boot Loader Section Page[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 104 8067O–AVR–06/2013 32. Accessing EBI address space with PREBI set will lock Bus Master If EBI Power Reduction Bit is set while EBI is enabled, accessing external memory could result in bus hang-up, blocking all further access to all data memory. Problem fix/Workaround Ensure that EBI is disabled before setting EBI Power Reduction bit. 33. RTC Counter value not correctly read after sleep If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will be the same as the value in the register when entering sleep. The same applies if RTC Compare Match is used as wake-up source. Problem fix/Workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 34. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. Problem fix/Workaround None. 35. TWI, the minimum I2 C SCL low time could be violated in Master Read mode If the TWI is in Master Read mode and issues a Repeated Start on the bus, this will immediately release the SCL line even if one complete SCL low period has not passed. This means that the minimum SCL low time in the I2C specification could be violated. Problem fix/Workaround If this is a problem in the application, ensure in software that the Repeated Start is never issued before one SCL low time has passed. 36. TWI address-mask feature is non-functional The address-mask feature is non-functional, so the TWI can not perform hardware address match on more than one address. Problem fix/Workaround If the TWI must respond to multiple addresses, enable Promiscuous Mode for the TWI to respond to all address and implement the address-mask function in software.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 105 8067O–AVR–06/2013 37. TWI, a general address call will match independent of the R/W-bit value When the TWI is in Slave mode and a general address call is issued on the bus, the TWI Slave will get an address match regardless of the received R/W bit. Problem fix/Workaround Use software to check the R/W-bit on general call address match. 38. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/Workaround Clear the flag in software after address interrupt. 39. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. Problem fix/Workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code: /* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; }[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 106 8067O–AVR–06/2013 40. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/Workaround None. 41. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set. Problem fix/Workaround Add one NOP instruction before checking DIF. 42. WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/Workaround Wait at least one ULP clock cycle before executing a WDR instruction.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 107 8067O–AVR–06/2013 36.2 ATxmega64A1 and ATxmega128A1 rev. G  Bootloader Section in Flash is non-functional  Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously  DAC is nonlinear and inaccurate when reference is above 2.4V  ADC gain stage output range is limited to 2.4 V  The ADC has up to ±2 LSB inaccuracy  TWI, a general address call will match independent of the R/W-bit value  TWI, the minimum I2 C SCL low time could be violated in Master Read mode  Setting HIRES PR bit makes PWM output unavailable  EEPROM erase and write does not work with all System Clock sources  BOD will be enabled after any reset  Propagation delay analog Comparator increasing to 2 ms at -40C  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Default setting for SDRAM refresh period too low  Flash Power Reduction Mode can not be enabled when entering sleep mode  Enabling Analog Comparator B output will cause JTAG failure  JTAG enable does not override Analog Comparator B output  Bandgap measurement with the ADC is non-functional when VCC is below 2.7V  DAC refresh may be blocked in S/H mode  Inverted I/O enable does not affect Analog Comparator Output  Both DFLLs and both oscillators has to be enabled for one to work 1. Bootloader Section in Flash is non-functional The Bootloader Section is non-functional, and bootloader or application code cannot reside in this part of the Flash. Problem fix/Workaround None, do not use the Bootloader Section. 2. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for the another AC, the first comparator will be affected for up to 1 us and could potentially give a wrong comparison result. Problem fix/Workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 3. DAC is nonlinear and inaccurate when reference is above 2.4V Using the DAC with a reference voltage above 2.4V give inaccurate output when converting codes that give below 0.75V output:  ±20 LSB for continuous mode[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 108 8067O–AVR–06/2013  ±200 LSB for Sample and Hold mode Problem fix/Workaround None, avoid using a voltage reference above 2.4V. 4. ADC gain stage output range is limited to 2.4 V The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of: Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V. 5. The ADC has up to ±2 LSB inaccuracy The ADC will have up to ±2 LSB inaccuracy, visible as a saw-tooth pattern on the input voltage/ output value transfer function of the ADC. The inaccuracy increases with increasing voltage reference reaching ±2 LSB with 3V reference. Problem fix/Workaround None, the actual ADC resolution will be reduced with up to ±2 LSB. 6. TWI, a general address call will match independent of the R/W-bit value When the TWI is in Slave mode and a general address call is issued on the bus, the TWI Slave will get an address match regardless of the R/W-bit (ADDR[0] bit) value in the Slave Address Register. Problem fix/Workaround Use software to check the R/W-bit on general call address match. – 1x gain: 2.4 V – 2x gain: 1.2 V – 4x gain: 0.6 V – 8x gain: 300 mV – 16x gain: 150 mV – 32x gain: 75 mV – 64x gain: 38 mV[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 109 8067O–AVR–06/2013 7. TWI, the minimum I2 C SCL low time could be violated in Master Read mode When the TWI is in Master Read mode and issuing a Repeated Start on the bus, this will immediately release the SCL line even if one complete SCL low period has not passed. This means that the minimum SCL low time in the I 2 C specification could be violated. Problem fix/Workaround If this causes a potential problem in the application, software must ensure that the Repeated Start is never issued before one SCL low time has passed. 8. Setting HIRES PR bit makes PWM output unavailable Setting the HIRES Power Reduction (PR) bit for PORTx will make any Frequency or PWM output for the corresponding Timer/Counters (TCx0 and TCx1) unavailable on the pin. Problem fix/Workaround Do not write the HIRES PR bit on PORTx when frequency or PWM output from TCx0/1 is used. 9. EEPROM erase and write does not work with all System Clock sources When doing EEPROM erase or Write operations with other clock sources than the 2 MHz RCOSC, Flash will be read wrongly for one or two clock cycles at the end of the EEPROM operation. Problem fix/Workaround Alt 1: Use the internal 2 MHz RCOSC when doing erase or write operations on EEPROM. Alt 2: Ensure to be in sleep mode while completing erase or write on EEPROM. After starting erase or write operations on EEPROM, other interrupts should be disabled and the device put to sleep. 10. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed BOD level even if the BOD is disabled. Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 11. Propagation delay analog Comparator increasing to 2 ms at -40 °C When the analog comparator is used at temperatures reaching down to -40 °C, the propagation delay will increase to ~2 ms. Problem fix/Workaround None[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 110 8067O–AVR–06/2013 12. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC and DAC. Problem fix/Workaround If the bandgap is used as reference for either the ADC or the DAC, the BOD must not be set in sampled mode. 13. Default setting for SDRAM refresh period too low If the SDRAM refresh period is set to a value less then 0x20, the SDRAM content may be corrupted when accessing through On-Chip Debug sessions. Problem fix/Workaround The SDRAM refresh period (REFRESHH/L) should not be set to a value less then 0x20. 14. Flash Power Reduction Mode can not be enabled when entering sleep mode If Flash Power Reduction Mode is enabled when entering Power-save or Extended Standby sleep mode, the device will only wake up on every fourth wake-up request. If Flash Power Reduction Mode is enabled when entering Idle sleep mode, the wake-up time will vary with up to 16 CPU clock cycles. Problem fix/Workaround Disable Flash Power Reduction mode before entering sleep mode. 15. JTAG enable does not override Analog Comparator B output When JTAG is enabled this will not override the Anlog Comparator B (ACB)ouput, AC0OUT on pin 7 if this is enabled. Problem fix/Workaround AC0OUT for ACB should not be enabled when JTAG is used. Use only analog comparator output for ACA when JTAG is used, or use the PDI as debug interface. 16. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V The ADC cannot be used to do bandgap measurements when VCC is below 2.7V. Problem fix/Workaround If internal voltages must be measured when VCC is below 2.7V, measure the internal 1.00V reference instead of the bandgap.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 111 8067O–AVR–06/2013 17. DAC refresh may be blocked in S/H mode If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this will block refresh signals to the second channel. Problem fix/Workarund When using the DAC in S/H mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 18. Inverted I/O enable does not affect Analog Comparator Output The inverted I/O pin function does not affect the Analog Comparator output function. Problem fix/Workarund Configure the analog comparator setup to give a inverted result (i.e. connect positive input to the negative AC input and vice versa), or use and externel inverter to change polarity of Analog Comparator Output. 19. Both DFLLs and both oscillators has to be enabled for one to work In order to use the automatic runtime calibration for the 2 MHz or the 32 MHz internal oscilla-tors, the DFLL for both oscillators and both oscillators has to be enabled for one to work. Problem fix/Workarund Enabled both DFLLs and oscillators when using automatic runtime calibration for one of the internal oscillators. [Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 112 8067O–AVR–06/2013 37. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 37.1 8067O – 06/2013 37.2 8067N – 03/2013 37.3 8067M – 09/2010 37.4 8067L – 08/2010 1. Not recommended for new designs - Use XMEGA A1U series. 1. Removed all references to ATxmega192A1, ATxmega256A1 and ATxmega384A1. 2. Updated module description. Based on the XMEGA A1U device datasheet. 3. Updated analog comparator (AC) overview, Figure 28-1 on page 53. 4. Updated “ADC Characteristics” on page 76. 5 Updated page erase time in “Flash and EEPROM Memory Characteristics” on page 76. 6 Updated Output low voltage conditions from IOH to IOL in “PAD Characteristics” on page 79. 7. Removed TBDs from: “DC Characteristics” on page 73. “DAC Characteristics” on page 78. “Bandgap Characteristics” on page 78. 8. Updated “Errata” on page 96 to be valid for both ATxmega64A1 and ATxmega128A1. 9. Removed Boundary Scan Order table. 1. Updated Errata “ATxmega64A1and ATxmega128A1 rev. H” on page 96 1. Removed Footnote 3 of Figure 2-1 on page 3 2. Updated “Features” on page 32. Event Channel 0 output on port pin 7 3. Updated “DC Characteristics” on page 73, by adding ICC for Flash/EEPROM Programming. 4. Added AVCC in “ADC Characteristics” on page 76. 5. Updated Start up time in “ADC Characteristics” on page 76. [Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 113 8067O–AVR–06/2013 37.5 8067K – 02/2010 37.6 8067J – 02/2010 37.7 8067I – 04/2009 37.8 8067H – 04/2009 6. Updated “DAC Characteristics” on page 78. Removed DC output impedance. 7. Fixed typo in “Packaging information” section. 8. Fixed typo in “Errata” section. 1. Added “PDI Speed vs. VCC” on page 95. 1. Removed JTAG Reset from the datasheet. 2. Updated “Timer/Counter and AWEX functions” on page 56. 3. Updated “Alternate Pin Functions” on page 58. 3. Updated all “Electrical Characteristics” on page 73. 4. Updated “PAD Characteristics” on page 79. 5. Changed Internal Oscillator Speed to “Oscillators and Wake-up Time” on page 92. 6. Updated “Errata” on page 96 1. Updated “Ordering Information” on page 2. 2. Updated “PAD Characteristics” on page 79. 1. Editorial updates. 2. Updated “Overview” on page 54. 3. Updated Table 29-9 on page 54. 4. Updated “Peripheral Module Address Map” on page 62. IRCOM has address map: 0x08F8. 5. Updated “Electrical Characteristics” on page 73. 6. Updated “PAD Characteristics” on page 79. 7. Updated “Typical Characteristics” on page 82.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 114 8067O–AVR–06/2013 37.9 8067G – 11/2008 37.10 8067F – 09/2008 37.11 8067E – 08/2008 37.12 8067D – 07/2008 1. Updated “Block Diagram” on page 6. 2. Updated feature list in “Memories” on page 12. 3. Updated “Programming and Debugging” on page 54. 4. Updated “Peripheral Module Address Map” on page 62. IRCOM has address 0x8F0. 5. Added “Electrical Characteristics” on page 73. 6. Added “Typical Characteristics” on page 82. 7. Added “ATxmega64A1and ATxmega128A1 rev. H” on page 96. 8. Updated “ATxmega64A1 and ATxmega128A1 rev. G” on page 107. 1. Updated “Features” on page 1 2. Updated “Ordering Information” on page 2 3. Updated Figure 7-1 on page 11 and Figure 7-2 on page 11. 4. Updated Table 7-2 on page 15. 5. Updated “Features” on page 48 and “Overview” on page 48. 6. Removed “Interrupt Vector Summary” section from datasheet. 1. Changed Figure 2-1’s title to “Block diagram and pinout” on page 3. 2. Updated Figure 2-2 on page 4. 3. Updated Table 29-2 on page 51 and Table 29-3 on page 52. 1. Updated “Ordering Information” on page 2. 2. Updated “Peripheral Module Address Map” on page 62. 3. Inserted “Interrupt Vector Summary” on page 56.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 115 8067O–AVR–06/2013 37.13 8067C – 06/2008 37.14 8067B – 05/2008 37.15 8067A – 02/2008 1. Updated the Front page and “Features” on page 1. 2. Updated the “DC Characteristics” on page 73. 3. Updated Figure 3-1 on page 6. 4. Added “Flash and EEPROM Page Size” on page 15. 5. Updated Table 33-6 on page 72 with new data: Gain Error, Offset Error and Signal -to-Noise Ratio (SNR). 6. Updated Errata “ATxmega64A1 and ATxmega128A1 rev. G” on page 107. 1. Updated “Pinout/Block Diagram” on page 3 and “Pinout and Pin Functions” on page 55. 2. Added XMEGA A1 Block Diagram, Figure 3-1 on page 6. 3. Updated “Overview” on page 5 included the XMEGA A1 explanation text on page 6. 4. Updated AVR CPU “Features” on page 8. 5. Updated Event System block diagram, Figure 10-1 on page 20. 6. Updated “Interrupts and Programmable Multilevel Interrupt Controller” on page 29. 7. Updated “AC - Analog Comparator” on page 52. 8. Updated “Alternate Pin Function Description” on page 55. 9. Updated “Alternate Pin Functions” on page 58. 10. Updated “Typical Characteristics” on page 82. 11. Updated “Ordering Information” on page 2. 12. Updated “Overview” on page 5. 13. Updated Figure 6-1 on page 8. 14. Inserted a new Figure 16-1 on page 37. 15. Updated Speed grades in “Speed” on page 75. 16. Added a new ATxmega384A1 device in “Features” on page 1, updated “Ordering Information” on page 2 and “Memories” on page 12. 17. Replaced the Figure 3-1 on page 6 by a new XMEGA A1 detailed block diagram. 18. Inserted Errata “ATxmega64A1 and ATxmega128A1 rev. G” on page 107. 1. Initial revision.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 116 8067O–AVR–06/2013[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 1 8067O–AVR–06/2013 Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 Recommended reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5. Capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6. Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7. AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.3 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.4 ALU - Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.5 Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.7 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.3 In-System Programmable Flash Program Memory. . . . . . . . . . . . . . . . . . . . . 13 8.4 Fuses and Lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.5 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.6 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.7 I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.8 External Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.9 Data Memory and Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.10 Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.11 Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.12 I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.13 JTAG Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.14 Flash and EEPROM Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9. DMAC - Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . 18 9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10. Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11. System Clock and Clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 2 8067O–AVR–06/2013 11.3 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . 24 12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 12.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 12.3 Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 13. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13.3 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13.4 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13.5 WDT - Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 13.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . 29 14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.3 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 15. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 15.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 15.3 Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 15.4 Input sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 15.5 Port Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 15.6 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 16. T/C - 16-bit Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 16.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 17. AWeX - Advanced Waveform Extension . . . . . . . . . . . . . . . . . . . . . 38 17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 17.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 18. Hi-Res - High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . . 39 18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 18.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 19. RTC - 16-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 19.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 20. TWI - Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 20.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 21. SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 21.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 22. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 3 8067O–AVR–06/2013 22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 22.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 23. IRCOM - IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . 45 23.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 23.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 24. AES and DES Crypto Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 24.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 25. EBI – External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 25.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 25.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 26. ADC - 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . 48 26.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 26.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 27. DAC - 12-bit Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . . 50 27.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 27.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 28. AC - Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 28.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 28.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 29. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 29.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 29.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 30. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 30.1 Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 30.2 Alternate Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 31. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 32. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 33. Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 33.1 100A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 33.2 100C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 33.3 100C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 34. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 34.1 Absolute Maximum Ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 34.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 34.3 Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 34.4 Flash and EEPROM Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 76 34.5 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 34.6 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 34.7 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 34.8 Bandgap Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 34.9 Brownout Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 4 8067O–AVR–06/2013 34.10 PAD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 34.11 POR Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 34.12 Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 34.13 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 35. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 35.1 Active Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 35.2 Idle Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 35.3 Power-down Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 35.4 Power-save Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 35.5 Pin Pull-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 35.6 Pin Thresholds and Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 35.7 Bod Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 35.8 Bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 35.9 Analog Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 35.10 Oscillators and Wake-up Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 35.11 PDI Speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 36. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 36.1 ATxmega64A1and ATxmega128A1 rev. H. . . . . . . . . . . . . . . . . . . . . . . . . . . 96 36.2 ATxmega64A1 and ATxmega128A1 rev. G . . . . . . . . . . . . . . . . . . . . . . . . . 107 37. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 37.1 8067O – 06/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 37.2 8067N – 03/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 37.3 8067M – 09/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 37.4 8067L – 08/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 37.5 8067K – 02/2010. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 37.6 8067J – 02/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 37.7 8067I – 04/2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 37.8 8067H – 04/2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 37.9 8067G – 11/2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 37.10 8067F – 09/2008. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 37.11 8067E – 08/2008. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 37.12 8067D – 07/2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 37.13 8067C – 06/2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 37.14 8067B – 05/2008. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 37.15 8067A – 02/2008. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 5 8067O–AVR–06/2013Atmel Corporation 1600 Technology Drive San Jose, CA 95110 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 www.atmel.com Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Roa Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg 1-6-4 Osaki, Shinagawa-ku Tokyo 141-0032 JAPAN Tel: (+81) (3) 6417-0300 Fax: (+81) (3) 6417-0370 © 2013 Atmel Corporation. All rights reserved. / Rev.: 8067O–AVR–06/2013 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 USER GUIDE Atmel SAM4S Xplained Pro Preface The Atmel® SAM4S Xplained Pro evaluation kit is a hardware platform to evaluate the ATSAM4SD32C microcontroller. Supported by the Atmel Studio integrated development platform, the kit provides easy access to the features of the Atmel ATSAM4SD32C and explains how to integrate the device in a custom design. The Xplained Pro MCU series evaluation kits include an on-board Embedded Debugger, and no external tools are necessary to program or debug the ATSAM4SD32C. The Xplained Pro extension series evaluation kits offers additional peripherals to extend the features of the board and ease the development of custom designs.Atmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 2 Table of Contents Preface .......................................................................................... 1 1. Introduction .............................................................................. 3 1.1. Features .............................................................................. 3 1.2. Kit overview ......................................................................... 3 2. Getting started ......................................................................... 5 2.1. Quick-start ........................................................................... 5 2.2. Connecting the kit ................................................................. 5 2.3. Design documentation and related links ..................................... 5 3. Xplained Pro ............................................................................ 6 3.1. Embedded Debugger ............................................................. 6 3.2. Hardware identification system ................................................. 6 3.3. Power supply ....................................................................... 7 3.3.1. Measuring SAM4S power consumption ......................... 7 3.4. Standard headers and connectors ............................................ 7 3.4.1. Xplained Pro extension header .................................... 7 3.4.2. Xplained Pro LCD connector ....................................... 8 3.4.3. Power header ......................................................... 10 4. Hardware user guide ............................................................ 11 4.1. Connectors ......................................................................... 11 4.1.1. I/O extension headers .............................................. 11 4.1.2. LCD extension connector .......................................... 12 4.1.3. Other headers ........................................................ 14 4.2. Peripherals ......................................................................... 14 4.2.1. NAND Flash ........................................................... 14 4.2.2. SD Card connector .................................................. 15 4.2.3. Crystals ................................................................. 15 4.2.4. Mechanical buttons .................................................. 16 4.2.5. LED ...................................................................... 16 4.2.6. Analog reference ..................................................... 16 4.3. Embedded Debugger implementation ...................................... 16 4.3.1. Serial Wire Debug ................................................... 16 4.3.2. Virtual COM port ..................................................... 16 4.3.3. Atmel Data Gateway Interface ................................... 17 5. Hardware revision history and known issues ........................ 18 5.1. Identifying product ID and revision .......................................... 18 5.2. Revision 5 .......................................................................... 18 5.3. Revision 4 .......................................................................... 18 6. Document revision history ..................................................... 19 7. Evaluation board/kit important notice .................................... 20Atmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 3 1. Introduction 1.1 Features ● Atmel ATSAM4SD32C microcontroller ● Embedded debugger (EDBG) ● USB interface ● Programming and debugging (target) through Serial Wire Debug (SWD) ● Virtual COM-port interface to target via UART ● Atmel Data Gateway Interface (DGI) to target via synchronous SPI or TWI ● Four GPIOs connected to target for code instrumentation ● Digital I/O ● Two mechanical buttons (user and reset button) ● One user LED ● Three extension headers ● LCD display header ● USB interface for host and device function (target) ● 2Gb NAND Flash for non-volatile storage ● SD card connector ● Adjustable analog reference ● Three possible power sources ● External power ● Embedded debugger USB ● Target USB ● 12MHz crystal ● 32kHz crystal 1.2 Kit overview The Atmel SAM4S Xplained Pro evaluation kit is a hardware platform to evaluate the Atmel ATSAM4SD32C. The kit offers a set of features that enables the ATSAM4SD32C user to get started using the ATSAM4SD32C peripherals right away and to get an understanding of how to integrate the device in their own design.Atmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 4 Figure 1.1. SAM4S Xplained Pro evaluation kit overviewAtmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 5 2. Getting started 2.1 Quick-start 3 Steps to start exploring the Atmel Xplained Pro Platform ● Download and install Atmel Studio1 . ● Launch Atmel Studio. ● Connect an USB cable to the DEBUG USB port. 2.2 Connecting the kit When connecting Atmel SAM4S Xplained Pro to your computer for the first time, the operating system will do a driver software installation. The driver file supports both 32-bit and 64-bit versions of Microsoft® Windows® XP and Windows 7. Once connected the green power LED will be lit and Atmel Studio will autodetect which Xplained Pro evaluation- and extension kit(s) that's connected. You'll be presented with relevant information like datasheets and kit documentation. You also have the option to launch Atmel Software Framework (ASF) example applications. The target device is programmed and debugged by the on-board Embedded Debugger and no external programmer or debugger tool is needed. Please refer to the Atmel Studio user guide2 for information regarding how to compile and program the kit. 2.3 Design documentation and related links The following list contains links to the most relevant documents and software for SAM4S Xplained Pro. 1. Xplained Pro products 3 - Atmel Xplained Pro is a series of small-sized and easy-to-use evaluation kits for 8- and 32-bit Atmel microcontrollers. It consists of a series of low cost MCU boards for evaluation and demonstration of features and capabilities of different MCU families. 2. SAM4S Xplained Pro User Guide 4 - PDF version of this User Guide. 3. SAM4S Xplained Pro Design Documentation 5 - Package containing schematics, BOM, assembly drawings, 3D plots, layer plots etc. 4. Atmel Studio 6 - Free Atmel IDE for development of C/C++ and assembler code for Atmel microcontrollers. 5. IAR Embedded Workbench® 7 for ARM®. This is a commercial C/C++ compiler that is available for ARM. There is a 30 day evaluation version as well as a code size limited kick-start version available from their website. The code size limit is 16K for devices with M0, M0+ and M1 cores and 32K for devices with other cores. 6. Atmel sample store 8 - Atmel sample store where you can order samples of devices. 1 http://www.atmel.com/atmelstudio 2 http://www.atmel.com/atmelstudio 3 http://www.atmel.com/XplainedPro 4 http://www.atmel.com/Images/Atmel-42075-SAM4S-Xplained-Pro_User-Guide.pdf 5 http://www.atmel.com/Images/Atmel-42075-SAM4S-Xplained-Pro_User-Guide.zip 6 http://www.atmel.com/atmelstudio 7 http://www.iar.com/en/Products/IAR-Embedded-Workbench/ARM/ 8 http://www.atmel.com/system/samplesstoreAtmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 6 3. Xplained Pro Xplained Pro is an evaluation platform that provides the full Atmel microcontroller experience. The platform consists of a series of Microcontroller (MCU) boards and extension boards that are integrated with Atmel Studio, have Atmel Software Framework (ASF) drivers and demo code, support data streaming and more. Xplained Pro MCU boards support a wide range of Xplained Pro extension boards that are connected through a set of standardized headers and connectors. Each extension board has an identification (ID) chip to uniquely identify which boards are mounted on a Xplained Pro MCU board. This information is used to present relevant user guides, application notes, datasheets and example code through Atmel Studio. Available Xplained Pro MCU and extension boards can be purchased in the Atmel Web Store 1 . 3.1 Embedded Debugger The SAM4S Xplained Pro contains the Atmel® Embedded Debugger (EDBG) for on-board debugging. The EDBG is a composite USB device of 3 interfaces; a debugger, Virtual COM Port and Data Gateway Interface (DGI). In conjunction with Atmel Studio, the EDBG debugger interface can program and debug the ATSAM4SD32C. On the SAM4S Xplained Pro, the SWD interface is connected between the EDBG and the ATSAM4SD32C. The Virtual COM Port is connected to a UART port on the ATSAM4SD32C (see section “Embedded Debugger implementation” on page 16 for pinout), and provides an easy way to communicate with the target application through a simple terminal software. It offers variable baud rate, parity and stop bit settings. Note that the settings on the target device UART must match the settings given in the terminal software. The DGI consists of several physical data interfaces for communication with the host computer. Please, see section “Embedded Debugger implementation” on page 16 for available interfaces and pinout. Communication over the interfaces are bidirectional. It can be used to send events and values from the ATSAM4SD32C, or as a generic printf-style data channel. Traffic over the interfaces can be timestamped on the EDBG for more accurate tracing of events. Note that timestamping imposes an overhead that reduces maximal throughput. The DGI uses a proprietary protocol, and is thus only compatible with Atmel Studio. The EDBG controls two LEDs on SAM4S Xplained Pro, a power LED and a status LED. Table 3.1, “EDBG LED control” shows how the LEDs are controlled in different operation modes. Table 3.1. EDBG LED control Operation mode Power LED Status LED Normal operation Power LED is lit when power is applied to the board. Activity indicator, LED flashes every time something happens on the EDBG. Bootloader mode (idle) The power LED and the status LED blinks simultaneously. Bootloader mode (firmware upgrade) The power LED and the status LED blinks in an alternating pattern. For further documentation on the EDBG, see the EDBG User Guide. 3.2 Hardware identification system All Xplained Pro compatible extension boards have an Atmel ATSHA204 crypto authentication chip mounted. This chip contains information that identifies the extension with its name and some extra data. When an Xplained Pro extension board is connected to an Xplained Pro MCU board the information is read and sent to Atmel Studio. The Atmel Kits extension, installed with Atmel Studio, will give relevant information, code examples and links to relevant documents. Table 3.2, “Xplained Pro ID chip content” shows the data fields stored in the ID chip with example content. Table 3.2. Xplained Pro ID chip content Data Field Data Type Example Content Manufacturer ASCII string Atmel’\0’ Product Name ASCII string Segment LCD1 Xplained Pro’\0’ Product Revision ASCII string 02’\0’ Product Serial Number ASCII string 1774020200000010’\0’ Minimum Voltage [mV] uint16_t 3000 1 http://store.atmel.com/CBC.aspx?q=c:100113Atmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 7 Data Field Data Type Example Content Maximum Voltage [mV] uint16_t 3600 Maximum Current [mA] uint16_t 30 3.3 Power supply The SAM4S Xplained Pro kit can be powered either by USB or by an external power source through the 4- pin power header, marked PWR. This connector is described in “Power header” on page 10. The available power sources and specifications are listed in Table 3.3, “Power sources for SAM4S Xplained Pro”. Table 3.3. Power sources for SAM4S Xplained Pro Power input Voltage requirements Current requirements Connector marking External power 5 V +/- 2 % (+/- 100 mV) for USB host operation. 4.3 V to 5.5 V if USB host operation is not required Recommended minimum is 1A to be able to provide enough current for connected USB devices and the board itself. Recommended maximum is 2A due to the input protection maximum current specification. PWR Embedded debugger USB 4.4V to 5.25V (according to USB spec) 500 mA (according to USB spec) DEBUG USB Target USB 4.4V to 5.25V (according to USB spec) 500 mA (according to USB spec) TARGET USB The kit will automatically detect which power sources are available and choose which one to use according to the following priority: 1. External power 2. Embedded debugger USB 3. Target USB Note External power is required when the 500mA through the USB connector is not enough to power a connected USB device in a USB host application. 3.3.1 Measuring SAM4S power consumption As part of an evaluation of the SAM4S it can be of interest to measure its power consumption. Because the device has a separate power plane (VCC_MCU_P3V3) on this board it is possible to measure the current consumption by measuring the current that is flowing into this plane. The VCC_MCU_P3V3 plane is connected via a jumper to the main power plane (VCC_TARGET_P3V3) and by replacing the jumper with an ampere meter it is possible to determine the current consumption. To locate the current measurement header, please refer to Figure 1.1, “SAM4S Xplained Pro evaluation kit overview”. Warning Do not power the board without having the jumper or an ampere meter mounted. This can cause the SAM4S to be powered through its I/O pins and cause undefined operation of the device. 3.4 Standard headers and connectors 3.4.1 Xplained Pro extension header All Xplained Pro kits have one or more dual row, 20 pin, 100mil extension headers. Xplained Pro MCU boards have male headers while Xplained Pro extensions have their female counterparts. Note that all pins are not always connected. However, all the connected pins follow the defined pin-out described in Table 3.4, “Xplained Pro extension header”. The extension headers can be used to connect a wide variety of Xplained ProAtmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 8 extensions to Xplained Pro MCU boards and to access the pins of the target MCU on Xplained Pro MCU board directly. Table 3.4. Xplained Pro extension header Pin number Name Description 1 ID Communication line to the ID chip on extension board. 2 GND Ground 3 ADC(+) Analog to digital converter , alternatively positive part of differential ADC 4 ADC(-) Analog to digital converter , alternatively negative part of differential ADC 5 GPIO1 General purpose IO 6 GPIO2 General purpose IO 7 PWM(+) Pulse width modulation , alternatively positive part of differential PWM 8 PWM(-) Pulse width modulation , alternatively positive part of differential PWM 9 IRQ/GPIO Interrupt request line and/or general purpose IO. 10 SPI_SS_B/GPIO Slave select for SPI and/or general purpose IO. 11 TWI_SDA Data line for two wire interface. Always implemented, bus type. 12 TWI_SCL Clock line for two wire interface. Always implemented, bus type. 13 USART_RX Receiver line of Universal Synchronous and Asynchronous serial Receiver and Transmitter 14 USART_TX Transmitter line of Universal Synchronous and Asynchronous serial Receiver and Transmitter 15 SPI_SS_A Slave select for SPI. Should be unique if possible. 16 SPI_MOSI Master out slave in line of Serial peripheral interface. Always implemented, bus type 17 SPI_MISO Master in slave out line of Serial peripheral interface. Always implemented, bus type 18 SPI_SCK Clock for Serial peripheral interface. Always implemented, bus type 19 GND Ground 20 VCC Power for extension board 3.4.2 Xplained Pro LCD connector The LCD connector provides the ability to connect to display extensions that have a parallel interface. The connector implements signals for a MCU parallel bus interface and a LCD controller interface as well as signals for a touchcontroller. The connector pin-out definition is shown in Table 3.5, “Xplained Pro LCD connector”. Note that usually only one display interface is implemented, either LCD controller or the MCU bus interface. A FPC/FFC connector with 50 pins and 0.5mm pitch is used for the LCD connector. The connector (XF2M-5015-1A) from Omron is used on several designs and can be used as a reference. Table 3.5. Xplained Pro LCD connector Pin number Name RGB interface description MCU interface description 1 ID Communication line to ID chip on extension board. 2 GND Ground 3 D0 Data line 4 D1 Data line 5 D2 Data line 6 D3 Data lineAtmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 9 Pin number Name RGB interface description MCU interface description 7 GND Ground 8 D4 Data line 9 D5 Data line 10 D6 Data line 11 D7 Data line 12 GND Ground 13 D8 Data line 14 D9 Data line 15 D10 Data line 16 D11 Data line 17 GND Ground 18 D12 Data line 19 D12 Data line 20 D14 Data line 21 D15 Data line 22 GND Ground 23 D16 Data line 24 D17 Data line 25 D18 Data line 26 D19 Data line 27 GND Ground 28 D20 Data line 29 D21 Data line 30 D22 Data line 31 D23 Data line 32 GND Ground 33 PCLK / CMD_DATA_SEL Pixel clock Command and data select. One address line of the MCU for displays where it is possible to select either the register or the data interface. 34 VSYNC / CS Vertical synchronization Chip select 35 HSYNC / WE Horizontal synchronization Write enable signal 36 DATA ENABLE / RE Data enable signal Read enable signal 37 SPI SCK Clock for Serial peripheral interface 38 SPI MOSI Master out slave in line of Serial peripheral interface 39 SPI MISO Master in slave out line of Serial peripheral interface 40 SPI SS Slave select for SPI. Should be unique if possible 41 ENABLE Display enable signal 42 TWI SDA I2C data line (maxTouch) 43 TWI SCL I2C clock line (maxTouch) 44 IRQ1 maxTouch interrupt lineAtmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 10 Pin number Name RGB interface description MCU interface description 45 IRQ2 Interrupt line for other I2C devices 46 PWM Backlight control 47 RESET Reset for both display and maxTouch 48 VCC 3.3V power supply for extension board 49 VCC 3.3V power supply for extension board 50 GND Ground 3.4.3 Power header The power header can be used to connect external power to the SAM4S Xplained Pro kit. The kit will automatically detect and switch to the external power if supplied. The power header can also be used as supply for external peripherals or extension boards. Care must be taken not to exceed the total current limitation of the on-board regulator for the 3.3V regulated output. To locate the current measurement header, please refer to Figure 1.1, “SAM4S Xplained Pro evaluation kit overview” Table 3.6. Power header PWR Pin number PWR header Pin name Description 1 VEXT_P5V0 External 5V input 2 GND Ground 3 VCC_P5V0 Unregulated 5V (output, derived from one of the input sources) 4 VCC_P3V3 Regulated 3.3V (output, used as main power for the kit) Note If the board is powered from a battery source it is recommended to use the PWR header. If there is a power source connected to EDBG USB, the EDBG is activated and it will consume more power.Atmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 11 4. Hardware user guide 4.1 Connectors This chapter describes the implementation of the relevant connectors and headers on SAM4S Xplained Pro and their connection to the ATSAM4SD32C. The tables of connections in this chapter also describes which signals are shared between the headers and on-board functionality. 4.1.1 I/O extension headers The SAM4S Xplained Pro headers EXT1, EXT2 and EXT3 offers access to the I/O of the microcontroller in order to expand the board e.g. by connecting extensions to the board. These headers all comply with the standard extension header specified in Xplained Pro Standard Extension Header. All headers have a pitch of 2.54 mm. Table 4.1. Extension header EXT1 Pin on EXT1 SAM4S pin Function Shared functionality 1 - - Communication line to ID chip on extension board. 2 - - GND 3 PA17 AD[0] 4 PA18 AD[1] 5 PA24 GPIO PIOD Interface Header 6 PA25 GPIO PIOD Interface Header 7 PA23 PWMH0 PIOD Interface Header 8 PA19 PWML0 9 PA1 WKUP1/GPIO 10 PA6 GPIO DGI_GPIO0 on EDBG 11 PA3 TWD0 EXT2 and EDBG 12 PA4 TWCK0 EXT2 and EDBG 13 PA21 USART1/RXD1 EXT2 14 PA22 USART1/TXD1 EXT2 15 PA11 SPI/NPCS[0] 16 PA13 SPI/MOSI EXT2, EXT3, LCD connector (EXT4) and EDBG 17 PA12 SPI/MISO EXT2, EXT3, LCD connector (EXT4) and EDBG 18 PA14 SPI/SPCK EXT2, EXT3, LCD connector (EXT4) and EDBG 19 - - GND 20 - - VCC Table 4.2. Extension header EXT2 Pin on EXT2 SAM4S pin Function Shared functionality 1 - - Communication line to ID chip on extension board. 2 - - GND 3 PB0 AD[4] 4 PB1 AD[5] 5 PC24 GPIO DGI_GPIO2 on EDBG 6 PC25 GPIO DGI_GPIO3 on EDBG 7 PC19 PWMH1Atmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 12 Pin on EXT2 SAM4S pin Function Shared functionality 8 PA20 PWML1 9 PC26 GPIO 10 PC27 GPIO 11 PA3 TWD0 EXT1 and EDBG 12 PA4 TWCK0 EXT1 and EDBG 13 PA21 USART1/RXD1 EXT1 14 PA22 USART1/TXD1 EXT1 15 PA9 SPI/NPCS[1] LCD connector (EXT4) 16 PA13 SPI/MOSI EXT1, EXT3, LCD connector (EXT4) and EDBG 17 PA12 SPI/MISO EXT1, EXT3, LCD connector (EXT4) and EDBG 18 PA14 SPI/SPCK EXT1, EXT3, LCD connector (EXT4) and EDBG 19 - - GND 20 - - VCC Table 4.3. Extension header EXT3 Pin on EXT3 SAM4S pin Function Shared functionality 1 - - Communication line to ID chip on extension board. 2 - - GND 3 PC29 AD[13] 4 PC30 AD[14] 5 PC21 GPIO 6 PC22 GPIO DGI_GPIO1 on EDBG 7 PC20 PWMH2 8 PA16 PWML2 PIOD Header 9 PA0 WKUP0/GPIO LCD connector (EXT4) 10 PC31 GPIO 11 PB4 TWD1 LCD connector (EXT4) 12 PB5 TWCK1 LCD connector (EXT4) 13 PB2 USART1/RXD1 CDC UART 14 PB3 USART1/TXD1 CDC UART 15 PA10 SPI/NPCS[2] LCD connector (EXT4) 16 PA13 SPI/MOSI EXT1, EXT2, LCD connector (EXT4) and EDBG 17 PA12 SPI/MISO EXT1, EXT2, LCD connector (EXT4) and EDBG 18 PA14 SPI/SPCK EXT1, EXT2, LCD connector (EXT4) and EDBG 19 - - GND 20 - - VCC 4.1.2 LCD extension connector Extension connector EXT4 is a special connector for LCD displays. The physical connector is an Omron Electronics XF2M-5015-1A FPC connector.Atmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 13 Table 4.4. LCD display connector EXT4 Pin on EXT4 SAM4S pin Function Shared functionality 1 - - Communication line to ID chip on extension board. 2 - - GND 3 PC0 D0 NAND Flash 4 PC1 D1 NAND Flash 5 PC2 D2 NAND Flash 6 PC3 D3 NAND Flash 7 - - GND 8 PC4 D4 NAND Flash 9 PC5 D5 NAND Flash 10 PC6 D6 NAND Flash 11 PC7 D7 NAND Flash 12 - - GND 13 - - 14 - - 15 - - 16 - - 17 - - GND 18 - - 19 - - 20 - - 21 - - 22 - - GND 23 - - 24 - - 25 - - 26 - - 27 - - GND 28 - - 29 - - 30 - - 31 - - 32 - - GND 33 PC18 A0 34 PC15 NPCS[1] 35 PC8 NWE 36 PC11 NRD 37 38 39 40 41 PB14 GPIO 42 PB4 TWD1/SDA EXT3Atmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 14 Pin on EXT4 SAM4S pin Function Shared functionality 43 PB5 TWCK1/SCL EXT3 44 PA0 WKUP0 EXT3 45 - - 46 PA15 PWML3 PIOD Interface header 47 PC28 GPIO 48 - VCC_P3V3 49 - VCC_P3V3 EXT2 50 - GND 4.1.3 Other headers In addition to the “I/O extension headers” on page 11, SAM4S Xplained Pro has two additional headers with spare signals that offers access to the I/O of the microcontroller which are otherwise not easily available elsewhere or might be favourable to have collected toghether. All headers have a pitch of 2.54mm. Table 4.5. SPARE SIGNALS header Pin on header SAM4S pin Function Shared functionality 1 PA2 DATRG User button, SW0 2 PA9 PWMF10 EXT2 3 PA26 TI0A2 SD Card and PIOD Interface header 4 PA27 TI0B2 SD Card and PIOD Interface header 5 PA28 TCLK1 SD Card and PIOD Interface header 6 PA29 TCLK2 SD Card and PIOD Interface header 7 PA31 PCK2 SD Card and PIOD Interface header 8 PB0 RTCOUT0 EXT2 9 PB1 RTCOUT1 EXT2 10 PB13 DAC0 11 PB14 DAC1 12 - - GND Table 4.6. PIOD INTERFACE header Pin on header SAM4S pin Function Shared functionality 1 PA15 PIODCEN1 LCD connector 2 PA16 PIODCEN2 EXT3 3 PA23 PIODCCLK EXT1 4 PA24 PIODC0 EXT1 5 PA25 PIODC1 EXT1 6 PA26 PIODC2 SD Card and SPARE Signals header 7 PA27 PIODC3 SD Card and SPARE Signals header 8 PA28 PIODC4 SD Card and SPARE Signals header 9 PA29 PIODC5 SD Card and SPARE Signals header 10 PA30 PIODC6 SD Card 11 PA31 PIODC7 SD Card and SPARE Signals header 12 - - GND 4.2 Peripherals 4.2.1 NAND Flash The SAM4S Xplained Pro kit has one 2Gb NAND Flash connected to the external bus interface of the SAM4S.Atmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 15 Table 4.7. NAND Flash connections SAM4S pin Function NAND Flash function Shared functionality PC0 D0 IO0 LCD connector PC1 D1 IO1 LCD connector PC2 D2 IO2 LCD connector PC3 D3 IO3 LCD connector PC4 D4 IO4 LCD connector PC5 D5 IO5 LCD connector PC6 D6 IO6 LCD connector PC7 D7 IO7 LCD connector PC9 NANDOE RE (active low) PC10 NANDWE WE (active low) PC13 GPIO R (active high)/ B (active low) PC14 NCS[0] CE (active low) PC16 NANDALE ALE (active low) PC17 NANDCLE CLE 4.2.2 SD Card connector The SAM4S Xplained Pro kit has one SD card connector which is connected to High Speed Multimedia Card Interface (HSMCI) of the SAM4S Table 4.8. SD Card connections SAM4S pin Function SD Card function Shared functionality PA26 MCDA2 DAT2 SPARE Signal and PIOD Interface headers PA27 MCDA3 DAT3 SPARE Signal and PIOD Interface headers PA28 MCCDA CMD SPARE Signal and PIOD Interface headers PA29 MCCK CLK SPARE Signal and PIOD Interface headers PA30 MCDA0 DAT0 PIOD Interface header PA31 MCDA1 DAT1 SPARE Signal and PIOD Interface headers PC12 GPIO Card Detect 4.2.3 Crystals The SAM4S Xplained Pro kit contains two crystals that can be used as clock sources for the SAM4S device. Each crystal has a cut-strap next to it that can be used to measure the oscillator safety factor. This is done by cutting the strap and adding a resistor across the strap. More information about oscillator allowance and safety factor can be found in appnote AVR4100 1 . Table 4.9. External 32.768kHz crystals Pin on SAM4S Function PA49 XIN32 PA48 XOUT32 1 http://www.atmel.com/images/doc8333.pdfAtmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 16 Table 4.10. External 12MHz crystals Pin on SAM4S Function PB9 XIN0 PB8 XOUT0 4.2.4 Mechanical buttons SAM4S Xplained Pro contains two mechanical buttons. One button is the RESET button connected to the SAM4S reset line and the other is a generic user configurable button. When a button is pressed it will drive the I/O line to GND. Table 4.11. Mechanical buttons Pin on SAM4S Silkscreen text NRST RESET PC24 SW0 4.2.5 LED There is one yellow LED available on the SAM4S Xplained Pro board that can be turned on and off. The LED can be activated by driving the connected I/O line to GND. Table 4.12. LED connections Pin on SAM4S LED PC23 Yellow LED0 4.2.6 Analog reference An adjustable voltage reference is implemented on the kit to have a reference for the ADC or DAC. The reference can be adjusted with the on-board multiturn trimmer potentiometer. Next to the potentiometer, a 2-pin header is available to measure the reference voltage for the AREF pin of the SAM4S. The voltage output range for the reference is 0V - 3.36V. 4.3 Embedded Debugger implementation SAM4S Xplained Pro contains an Embedded Debugger (EDBG) that can be used to program and debug the ATSAM4SD32C using Serial Wire Debug (SWD). The Embedded Debugger also include a Virtual Com port interface over UART, an Atmel Data Gateway Interface over SPI and TWI and it monitors four of the SAM4S GPIOs. Atmel Studio can be used as a front end for the Embedded Debugger. 4.3.1 Serial Wire Debug The Serial Wire Debug (SWD) use two pins to communicate with the target. For further information on how to use the programming and debugging capabilities of the EDBG, see “Embedded Debugger” on page 6. Table 4.13. SWD connections Pin on SAM4S Function PB7 SWD clock PB6 SWD data PB5 SWD trace output PB12 Erase 4.3.2 Virtual COM port The Embedded Debugger act as a Virtual Com Port gateway by using one of the ATSAM4SD32C UARTs. For further information on how to use the Virtual COM port see “Embedded Debugger” on page 6. Table 4.14. Virtual COM port connections Pin on SAM4S Function PB3 UART TXD (SAM4S TX line)Atmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 17 Pin on SAM4S Function PB2 UART RXD (SAM4S RX line) 4.3.3 Atmel Data Gateway Interface The Embedded Debugger features an Atmel Data Gateway Interface (DGI) by using either a SPI or TWI port. The DGI can be used to send a variety of data from the SAM4S to the host PC. For further information on how to use the DGI interface see “Embedded Debugger” on page 6. Table 4.15. DGI interface connections when using SPI Pin on SAM4S Function PA5 Slave select (SAM4S is Master) PA12 SPI MISO (Master In, Slave Out) PA13 SPI MOSI (Master Out, Slave in) PA14 SPI SCK (Clock Out) Table 4.16. DGI interface connections when using TWI Pin on SAM4S Function PA3 SDA (Data line) PA4 SCL (Clock line) Four GPIO lines are connected to the Embedded Debugger. The EDBG can monitor these lines and time stamp pin value changes. This makes it possible to accurately time stamp events in the SAM4S application code. For further information on how to configure and use the GPIO monitoring features see “Embedded Debugger” on page 6. Table 4.17. GPIO lines connected to the EDBG Pin on SAM4S Function PA6 GPIO0 PA22 GPIO1 PA24 GPIO2 PA25 GPIO3Atmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 18 5. Hardware revision history and known issues 5.1 Identifying product ID and revision The revision and product identifier of Xplained Pro boards can be found in two ways, through Atmel Studio or by looking at the sticker on the bottom side of the PCB. By connecting a Xplained Pro MCU board to a computer with Atmel Studio running, an information window will pop up. The first 6 digits of the serial number, which is listed under kit details, contain the product identifier and revision. Information about connected Xplained Pro extension boards will also appear in the Atmel Kits window. The same information can be found on the sticker on the bottom side of the PCB. Most kits will print the identifier and revision in plain text as A09-nnnn\rr where nnnn is the identifier and rr is the revision. Boards with limited space have a sticker with only a QR-code which contains a serial number string. The serial number string has the following format: "nnnnrrssssssssss" n = product identifier r = revision s = serial number The kit identifier for SAM4S Xplained Pro is 1803. 5.2 Revision 5 On this revision, the SPI clock net is improved to reduce any issues that might be caused by reflections. The SPI has been removed from the LCD (EXT4 connector) to reduce load on the clock net. The remaining clock lines have been divided into four terminated nets for each SPI source (EXT1, EXT2, EXT3, and EDBG) and routed in a star like layout. A series terminator resistor of 43ohm is placed on each clock net, close to the SPI clock pin. This reduces any issues that might be caused by reflections comming back from unterminated/ unused clock lines. It also reduces the rise/fall time of the clock edges and that will also help to reduce any reflection issues. 5.3 Revision 4 Known issues ● SAM4S has an on-die series termination of the SPI CLK which makes this signal not usable for a multi drop clock distribution because all devices along the line will see a fraction of VCC until the signal is reflected from the end of the transmission line. On the SAM4S Xplained Pro revision 4 this signal is routed to each extension connector with EXT1 at the end of the line. That means extensions that are connected along the transission line e.g. EXT3 header is likely to fail due to a non-monotinic edge caused by relections and the fraction of VCC that is present for a short time until the reflection comes back from the end of the line. Workaround: ● By slowing down the clock rise time with a capacitor, and thus effectively increasing the line length at which point it becomes a transmission line, it is possible to remove the clock issue. A 56pF capacitor has been mounted on the bottom side of the board between the SPI clock and GND. This however reduces the maximum SPI clock speed and it is recommended to not run this faster than 30MHz (this also depends on how much additional capacitance is added by connected extensions and needs to be checked case by case). The capacitor was added on revision 4 on the bottom side of the EXT3 header.Atmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 19 6. Document revision history Doc. Rev. Date Comment B 15/03/2013 Added information about changes done on rev 5 A 11/02/2013 First releaseAtmel SAM4S Xplained Pro [USER GUIDE] Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 20 7. Evaluation board/kit important notice This evaluation board/kit is intended for use for FURTHER ENGINEERING, DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY. It is not a finished product and may not (yet) comply with some or any technical or legal requirements that are applicable to finished products, including, without limitation, directives regarding electromagnetic compatibility, recycling (WEEE), FCC, CE or UL (except as may be otherwise noted on the board/kit). Atmel supplied this board/kit "AS IS," without any warranties, with all faults, at the buyer's and further users' sole risk. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies Atmel from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user's responsibility to take any and all appropriate precautions with regard to electrostatic discharge and any other technical or legal concerns. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER USER NOR ATMEL SHALL BE LIABLE TO EACH OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. No license is granted under any patent right or other intellectual property right of Atmel covering or relating to any machine, process, or combination in which such Atmel products or services might be or are used. Mailing Address: Atmel Corporation 1600 Technology Drive San Jose, CA 95110 USAAtmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2013 Atmel Corporation. All rights reserved. / Rev.: Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013 Atmel®, Atmel logo and combinations thereof, AVR®, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Windows® is a registered trademark of Microsoft Corporation in U.S. and or other countries. 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APPLICATION NOTE Atmel AVR600: STK600 Expansion, Routing and Socket Boards Atmel Microcontrollers Introduction This application note describes the process of developing new routing, socket and expansion cards for the Atmel STK® 600. It also describes the physical parameters for creating such cards. The STK600 starter kit from Atmel has a sandwich design to match a specific part package and pin out to the generic pin headers. It also features an expansion area where most part pins are available. While the variety of IC packages is relatively limited, the number of possible pinouts increases rapidly with the number of pins. I.e. a 6-pin IC can have 720 (6!) different pinouts! The routing / socket card design provides a lowcost solution to support upcoming devices as the socket is the cost driving factor. STK600 users might also want to create their own routing cards to include specialized hardware to prototype their own design. Figure 1. STK600 router and socket card. 8170C−AVR−03/2013Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 2 Table of Contents 1. Routing Cards ...................................................................................... 3 1.1 Connector footprints .......................................................................................... 3 1.2 Physical dimensions and component placement .............................................. 4 1.3 Atmel STK600 socket connectors pinout .......................................................... 5 1.3.1 Signal descriptions .............................................................................. 8 2. Socket Cards ..................................................................................... 10 2.1 Power design issues ....................................................................................... 10 2.2 Connector MPN ............................................................................................... 10 2.3 Physical dimensions and component placement ............................................ 10 3. Expansion Cards ................................................................................ 11 3.1 Connector MPN ............................................................................................... 11 3.2 Physical dimensions and component placement ............................................ 12 3.3 Atmel STK600 expansion connectors pinout .................................................. 13 4. ID System .......................................................................................... 17 4.1 Signal usage ................................................................................................... 17 4.2 ID functions ..................................................................................................... 18 4.3 Examples ........................................................................................................ 19 5. Design Example ................................................................................. 20 6. Revision History ................................................................................. 22Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 3 1. Routing Cards The routing cards sit between the generic socket card and the Atmel STK600. It has one pair of electric pads underneath to mate with the STK600 spring loaded connector, and one pair of pads on top where the socket card connector connects. A part specific card with the target IC soldered on can be viewed as a routing card without the top pads. 1.1 Connector footprints A routing card should have pads to mate with the following spring loaded connectors: Table 1-1. Router card connectors. Manufacturer and MPN Quantity Comment SAMTEC, FSI-140-03-G-D-AD 2 80-pins to socket card (top) SAMTEC, FSI-150-03-G-D-AD 2 100-pins to STK600 (bottom) Figure 1-1. PCB land pattern for mating to FSI connectors. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 4 1.2 Physical dimensions and component placement Figure 1-2. Routing card connector pad placement and dimensions. Figure 1-3. Clip hole dimensions. The board thickness should be 1.6mm to be compatible with the clips. Note: Components on the main board might conflict with through hole mounted or secondary side mounted components. Areas with such components are highlighted in Figure 1-4. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 5 Figure 1-4. Height restricted areas due to main board components. 1.3 Atmel STK600 socket connectors pinout Figure 1-5 shows the pinout for the STK600 headers. This corresponds to the routing card connectors J1 and J2. Figure 1-5. STK600 socket connectors’ pinout. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 6 Table 1-2. Atmel STK600 J201 left, routing card connector J1 pinout. Signal name Pin number Signal name VTG 2 1 GND PA1 4 3 PA0 PA3 6 5 PA2 PA5 8 7 PA4 PA7 10 9 PA6 VTG 12 11 GND PB1 14 13 PB0 PB3 16 15 PB2 PB5 18 17 PB4 PB7 20 19 PB6 VTG 22 21 GND PC1 24 23 PC0 PC3 26 25 PC2 PC5 28 27 PC4 PC7 30 29 PC6 VTG 32 31 GND PD1 34 33 PD0 PD3 36 35 PD2 PD5 38 37 PD4 PD7 40 39 PD6 VTG 42 41 GND PE1 44 43 PE0 PE3 46 45 PE2 PE5 48 47 PE4 PE7 50 49 PE6 VTG 52 51 GND PF1 54 53 PF0 PF3 56 55 PF2 PF5 58 57 PF4 PF7 60 59 PF6 VTG 62 61 GND PG1 64 63 PG0 PG3 66 65 PG2 PG5 68 67 PG4 PG7 70 69 PG6 VTG 72 71 GND PH1 74 73 PH0 PH3 76 75 PH2 PH5 78 77 PH4 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 7 PH7 80 79 PH6 VTG 82 81 GND AREF0 84 83 XTAL1 AREF1 86 85 XTAL2 TGT_MOSI 88 87 GND TGT_MISO 90 89 TOSC1 TGT_SCK 92 91 TOSC2 TDI 94 93 TGT_RESET TDO 96 95 GND TMS 98 97 Vext TCK 100 99 Vcc Table 1-3. Atmel STK600 J202 right, routing card connector J2 pinout. Signal name Pin number Signal name VTG 2 1 GND PJ1 4 3 PJ0 PJ3 6 5 PJ2 PJ5 8 7 PJ4 PJ7 10 9 PJ6 VTG 12 11 GND PK1 14 13 PK0 PK3 16 15 PK2 PK5 18 17 PK4 PK7 20 19 PK6 VTG 22 21 GND PL1 24 23 PL0 PL3 26 25 PL2 PL5 28 27 PL4 PL7 30 29 PL6 VTG 32 31 GND PM1 34 33 PM0 PM3 36 35 PM2 PM5 38 37 PM4 PM7 40 39 PM6 VTG 42 41 GND PN1 44 43 PN0 PN3 46 45 PN2 PN5 48 47 PN4 PN7 50 49 PN6 VTG 52 51 GND PP1 54 53 PP0 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 8 PP3 56 55 PP2 PP5 58 57 PP4 PP7 60 59 PP6 VTG 62 61 GND PQ1 64 63 PQ0 PQ3 66 65 PQ2 PQ5 68 67 PQ4 PQ7 70 69 PQ6 VBUST 72 71 DP UVCON 74 73 DN Vcc 76 75 UID Vext 78 77 GND TGT_PDATA1 80 79 TGT_PDATA0 TGT_PDATA3 82 81 TGT_PDATA2 TGT_PDATA5 84 83 TGT_PDATA4 TGT_PDATA7 86 85 TGT_PDATA6 TGT_PCTRL1 88 87 TGT_PCTRL0 TGT_PCTRL3 90 89 TGT_PCTRL2 TGT_PCTRL5 92 91 TGT_PCTRL4 TGT_PCTRL7 94 93 TGT_PCTRL6 BOARD_ID1 96 95 BOARD_ID0 BOARD_ID3 98 97 BOARD_ID2 BOARD_ID5 100 99 BOARD_ID4 1.3.1 Signal descriptions Table 1-4. Socket card connector pin description. Atmel STK600 signal name MCU Comment PAx, PBx etc PAx, PBx etc 1-to-1 MCU pin mapping VTG Vcc Target supply rail controlled by Atmel AVR Studio® / STK600 GND GND AREFx AREF Analog reference voltage, controlled by AVR Studio / STK600 XTALx XTALx Clock pins connected to oscillator on STK600 TGT_SCK, TGT_MISO, TGT_MOSI ISP pins ISP programming interface TGT_TDI, TGT_TDO, TGT_TMS, TGT_TCK JTAG pins JTAG programming interface VBUST VBUS VBUS (sense) for USB UID UID ID pin for USB OTG UVCON UVCON USB VBUS generation control for USB OTG. A low level on this signal enables VBUS generation DP, DN DP, DN USB differential pair TGT_PDATA(0-7) (HV) data pins Data pins for high voltage (PP/HVSP) programming Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 9 TGT_CTRL0 (HV) BS2 Control signals for High voltage Parallel Programming / Serial Programming. Refer to AVR datasheet for further information. On AVRs with common XA1/BS2, XA1 is used. On AVRs with common BS1/PAGEL, BS1 is used. TGT_CTRL1 (HV) Ready/Busy TGT_CTRL2 (HV) /OE TGT_CTRL3 (HV) /WR TGT_CTRL4 (HV) BS1 TGT_CTRL5 (HV) XA0 TGT_CTRL6 (HV) XA1 TGT_CTRL7 (HV) PAGEL BOARD_IDn none ID system for router / socket / expansion cards, see Chapter 4 - ID System Notes: 1. Not all AVR will have every pin (ex. two aref pins, tosc or usb). 2. A MCU pin will fan-out to both Pnx pin and to the programming interface(s) located at that pin. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 10 2. Socket Cards Socket cards route each pin from the IC socket to separate pins on the spring loaded connectors on the bottom side, facing the routing card. 2.1 Power design issues As all routing is handled by the routing card, even power lines and power decoupling is ignored at the socket card. This produces less than ideal power design, which may lead to unwanted noise, ground bounce, and other effects. It should therefore be expected that heavily loaded designs cannot run at full speed on the Atmel STK600. Likewise, such power design is not recommended for custom designs. 2.2 Connector MPN Table 2-1. Socket card connector. Manufacturer and MPN Quantity Comment SAMTEC, FSI-140-03-G-D-AD 2 Spring loaded 80-pin connector 2.3 Physical dimensions and component placement Figure 2-1. Socket card connector placement and dimensions. ST1 J1 J2 45° Note! 105mm 94mm 66mm 7mm The board thickness should be 1.6mm to be compatible with the clips. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 11 3. Expansion Cards The Atmel STK600 features an expansion area where cards for custom peripherals like memory expansion, LCD etc can be placed. STK600 routes all part pins and power to the expansion card connectors. 3.1 Connector MPN Table 3-1. Expansion card connector. Manufacturer and MPN Quantity Comment FCI, 61082-101402LF 2 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 12 3.2 Physical dimensions and component placement Figure 3-1. Expansion card connector placement and dimensions. There is no requirement to board thickness. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 13 3.3 Atmel STK600 expansion connectors pinout Figure 3-2. Pinout for expansion connectors. Table 3-2. STK600 J301 “expand0” connector pinout. Signal name Pin number Signal name VTG 2 1 GND PA1 4 3 PA0 PA3 6 5 PA2 PA5 8 7 PA4 PA7 10 9 PA6 VTG 12 11 GND PB1 14 13 PB0 PB3 16 15 PB2 PB5 18 17 PB4 PB7 20 19 PB6 VTG 22 21 GND PC1 24 23 PC0 PC3 26 25 PC2 PC5 28 27 PC4 PC7 30 29 PC6 VTG 32 31 GND PD1 34 33 PD0 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 14 PD3 36 35 PD2 PD5 38 37 PD4 PD7 40 39 PD6 VTG 42 41 GND PE1 44 43 PE0 PE3 46 45 PE2 PE5 48 47 PE4 PE7 50 49 PE6 VTG 52 51 GND PF1 54 53 PF0 PF3 56 55 PF2 PF5 58 57 PF4 PF7 60 59 PF6 VTG 62 61 GND PG1 64 63 PG0 PG3 66 65 PG2 PG5 68 67 PG4 PG7 70 69 PG6 VTG 72 71 GND PH1 74 73 PH0 PH3 76 75 PH2 PH5 78 77 PH4 PH7 80 79 PH6 VTG 82 81 GND AREF0 84 83 XTAL1 AREF1 86 85 XTAL2 TGT_MOSI 88 87 GND TGT_MISO 90 89 TOSC1 TGT_SCK 92 91 TOSC2 TDI 94 93 TGT_RESET TDO 96 95 Vcc6 TMS 98 97 GND TCK 100 99 Vcc6 Table 3-3. Atmel STK600 J302 “expand1” connector pinout. Signal name Pin number Signal name VTG 2 1 GND PJ1 4 3 PJ0 PJ3 6 5 PJ2 PJ5 8 7 PJ4 PJ7 10 9 PJ6 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 15 VTG 12 11 GND PK1 14 13 PK0 PK3 16 15 PK2 PK5 18 17 PK4 PK7 20 19 PK6 VTG 22 21 GND PL1 24 23 PL0 PL3 26 25 PL2 PL5 28 27 PL4 PL7 30 29 PL6 VTG 32 31 GND PM1 34 33 PM0 PM3 36 35 PM2 PM5 38 37 PM4 PM7 40 39 PM6 VTG 42 41 GND PN1 44 43 PN0 PN3 46 45 PN2 PN5 48 47 PN4 PN7 50 49 PN6 VTG 52 51 GND PP1 54 53 PP0 PP3 56 55 PP2 PP5 58 57 PP4 PP7 60 59 PP6 VTG 62 61 GND PQ1 64 63 PQ0 PQ3 66 65 PQ2 PQ5 68 67 PQ4 PQ7 70 69 PQ6 Vext 72 71 GND Vext 74 73 GND GND 76 75 Vcc GND 78 77 Vcc TGT_PDATA1 80 79 TGT_PDATA0 TGT_PDATA3 82 81 TGT_PDATA2 TGT_PDATA5 84 83 TGT_PDATA4 TGT_PDATA7 86 85 TGT_PDATA6 TGT_PCTRL1 88 87 TGT_PCTRL0 TGT_PCTRL3 90 89 TGT_PCTRL2 TGT_PCTRL5 92 91 TGT_PCTRL4 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 16 TGT_PCTRL7 94 93 TGT_PCTRL6 Vcc3 96 95 GND BOARD_ID1 98 97 BOARD_ID0 BOARD_ID7 100 99 BOARD_ID6 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 17 4. ID System The Atmel STK600 features an ID system to identify which routing, socket and expansion card is attached. The STK600 can impose voltage limitations based on the IDs, and Atmel AVR Studio will notify the user if the combination is incorrect. The ID system consists of two common output and two board unique input signals. Each input is one of sixteen possible values based in the input signals – giving a total ID space of 256. Three IDs are reserved for custom use and can be implemented without use of ICs. Table 4-1. IDs reserved for custom use. Type ID Board limited to 1.8V 0xCA Board limited to 3.3V 0xCC No limit on voltage 0xCF The ID 0xff indicates no board present. 4.1 Signal usage Table 4-2. ID system signal usage. Name Direction Function BOARD_ID0 Output (A) Common output to functions BOARD_ID1 Output (B) Common output to functions BOARD_ID2 Input Input from routing card BOARD_ID3 Input Input from routing card BOARD_ID4 Input Input from socket card BOARD_ID5 Input Input from socket card BOARD_ID6 Input Input from expansion card BOARD_ID7 Input Input from expansion card Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 18 4.2 ID functions The functions and their output according to input A and B: B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Functions as logic expressions: Function Expression ID 0 0 0x0 1 A + B 0x1 2 AB 0x2 3 B 0x3 4 AB 0x4 5 A 0x5 6 ⊕ BA 0x6 7 AB 0x7 8 AB 0x8 9 ⊕ BA 0x9 10 A 0xA 11 B + AB 0xB 12 B 0xC 13 B A⋅+ B 0xD 14 A + B 0xE 15 1 0xF Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 19 4.3 Examples For a socket card to report the ID 0xCA: Route BOARD_ID1 to BOARD_ID4 and BOARD_ID0 to BOARD_ID5 Figure 4-1. Socket card ID example. For an expansion card to report the ID 0xCF: Route BOARD_ID0 to BOARD_ID6 and VCC to BOARD_ID7 Figure 4-2. Expansion card ID example. For a router card to report the ID 0xCC: Route BOARD_ID1 to both BOARD_ID2 and BOARD_ID3. Figure 4-3. Routing card ID example. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 20 5. Design Example To support a new package type one would typically start with designing the socket card. The pinout between the socket card and routing card is not defined and left to the designer. An example is given in Figure 5-1. Next is the design of the routing card (Figure 5-3). The routing card’s role is to connect each pin from the socket card to the corresponding pin on the Atmel STK600. In addition to decoupling etc, the routing card should also fan-out the correct signals to programming headers. Each card in the stack has its own board_id pins; the routing card is responsible for passing on the signal to the socket card. Figure 5-1. Schema capture of socket card. Both the socket and routing card must also include the clip holes: Figure 5-2. Clip holes included in schematic. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 21 Figure 5-3. Schema capture of routing card. Copyright © 2008, Atmel Corporation Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013 22 6. Revision History Doc. Rev. Date Comments 8170C 03/2013 Example schematics for the ID system are updated 8170B 12/2010 8170A 10/2008 Initial document release Atmel Corporation 1600 Technology Drive San Jose, CA 95110 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan G.K. 16F Shin-Osaki Kangyo Building 1-6-4 Osaki, Shinagawa-ku Tokyo 141-0032 JAPAN Tel: (+81)(3) 6417-0300 Fax: (+81)(3) 6417-0370 © 2013 Atmel Corporation. All rights reserved. / Rev.: 8170C−AVR−03/2013 Atmel®, Atmel logo and combinations thereof, AVR®, AVR Studio®, Enabling Unlimited Possibilities®, STK®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. 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Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. 8159E–AVR–02/2013 Features • High-performance, Low-power Atmel®AVR® 8-bit Microcontroller • Advanced RISC Architecture – 130 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16MIPS Throughput at 16MHz – On-chip 2-cycle Multiplier • High Endurance Non-volatile Memory segments – 8KBytes of In-System Self-programmable Flash program memory – 512Bytes EEPROM – 1KByte Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85C/100 years at 25C(1) – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – Programming Lock for Software Security • Atmel QTouch® library support – Capacitive touch buttons, sliders and wheels – Atmel QTouch and QMatrix acquisition – Up to 64 sense channels • Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Three PWM Channels – 8-channel ADC in TQFP and QFN/MLF package • Eight Channels 10-bit Accuracy – 6-channel ADC in PDIP package • Six Channels 10-bit Accuracy – Byte-oriented Two-wire Serial Interface – Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby • I/O and Packages – 23 Programmable I/O Lines – 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V – 0 - 16MHz • Power Consumption at 4MHz, 3V, 25C – Active: 3.6mA – Idle Mode: 1.0mA – Power-down Mode: 0.5µA 8-bit Atmel Microcontroller with 8KB In-System Programmable Flash ATmega8AATmega8A [DATASHEET] 2 8159E–AVR–02/2013 1. Pin Configurations Figure 1-1. Pinout ATmega8A 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 (INT1) PD3 (XCK/T0) PD4 GND VCC GND VCC (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 PC1 (ADC1) PC0 (ADC0) ADC7 GND AREF ADC6 AVCC PB5 (SCK) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 (OC1A) PB1 (SS/OC1B) PB2 (MOSI/OC2) PB3 (MISO) PB4 PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) TQFP Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (RESET) PC6 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (XCK/T0) PD4 VCC GND (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) PC1 (ADC1) PC0 (ADC0) GND AREF AVCC PB5 (SCK) PB4 (MISO) PB3 (MOSI/OC2) PB2 (SS/OC1B) PB1 (OC1A) PDIP 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 MLF Top View (INT1) PD3 (XCK/T0) PD4 GND VCC GND VCC (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 PC1 (ADC1) PC0 (ADC0) ADC7 GND AREF ADC6 AVCC PB5 (SCK) (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 (OC1A) PB1 (SS/OC1B) PB2 (MOSI/OC2) PB3 (MISO) PB4 PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) NOTE: The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure good mechanical stability. If the center pad is left unconneted, the package might loosen from the PCB.ATmega8A [DATASHEET] 3 8159E–AVR–02/2013 2. Overview The Atmel®AVR® ATmega8A is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8A achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram INTERNAL OSCILLATOR OSCILLATOR WATCHDOG TIMER MCU CTRL. & TIMING OSCILLATOR TIMERS/ COUNTERS INTERRUPT UNIT STACK POINTER EEPROM SRAM STATUS REGISTER USART PROGRAM COUNTER PROGRAM FLASH INSTRUCTION REGISTER INSTRUCTION DECODER PROGRAMMING LOGIC SPI ADC INTERFACE COMP. INTERFACE PORTC DRIVERS/BUFFERS PORTC DIGITAL INTERFACE GENERAL PURPOSE REGISTERS X Y Z ALU + - PORTB DRIVERS/BUFFERS PORTB DIGITAL INTERFACE PORTD DIGITAL INTERFACE PORTD DRIVERS/BUFFERS XTAL1 XTAL2 CONTROL LINES VCC GND MUX & ADC AGND AREF PC0 - PC6 PB0 - PB7 PD0 - PD7 AVR CPU TWI RESETATmega8A [DATASHEET] 4 8159E–AVR–02/2013 The Atmel®AVR® AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega8A provides the following features: 8K bytes of In-System Programmable Flash with Read-WhileWrite capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with 10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash Section will continue to run while the Application Flash Section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The Atmel AVR ATmega8A is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program simulators and evaluation kits. 2.2 Pin Descriptions 2.2.1 VCC Digital supply voltage. 2.2.2 GND Ground. 2.2.3 Port B (PB7:PB0) – XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.ATmega8A [DATASHEET] 5 8159E–AVR–02/2013 The various special features of Port B are elaborated in “Alternate Functions of Port B” on page 56 and “System Clock and Clock Options” on page 24. 2.2.4 Port C (PC5:PC0) Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. 2.2.5 PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 26-3 on page 228. Shorter pulses are not guaranteed to generate a Reset. The various special features of Port C are elaborated on page 59. 2.2.6 Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega8A as listed on page 61. 2.2.7 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 26-3 on page 228. Shorter pulses are not guaranteed to generate a reset. 2.2.8 AVCC AVCC is the supply voltage pin for the A/D Converter, Port C (3:0), and ADC (7:6). It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that Port C (5:4) use digital supply voltage, VCC. 2.2.9 AREF AREF is the analog reference pin for the A/D Converter. 2.2.10 ADC7:6 (TQFP and QFN/MLF Package Only) In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels.ATmega8A [DATASHEET] 6 8159E–AVR–02/2013 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 6. Capacitive touch sensing The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR® microcontrollers. The QTouch Library includes support for the QTouch and QMatrix® acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website.ATmega8A [DATASHEET] 7 8159E–AVR–02/2013 7. AVR CPU Core 7.1 Overview This section discusses the Atmel®AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1. Block Diagram of the AVR MCU Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registrers ALU Status and Control I/O Lines EEPROM Data Bus 8-bit Data SRAM Direct Addressing Indirect Addressing Interrupt Unit SPI Unit Watchdog Timer Analog Comparator i/O Module 2 i/O Module1 i/O Module nATmega8A [DATASHEET] 8 8159E–AVR–02/2013 The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. The Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot program section and the Application program section. Both sections have dedicated Lock Bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. 7.2 Arithmetic Logic Unit – ALU The high-performance Atmel®AVR® ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 7.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 7.3.1 SREG – The AVR Status Register Bit 7 6 5 4 3 2 1 0 I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 9 8159E–AVR–02/2013 • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the Instruction Set Reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 7.4 General Purpose Register File The Register File is optimized for the Atmel®AVR® Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input. • Two 8-bit output operands and one 8-bit result input. • Two 8-bit output operands and one 16-bit result input. • One 16-bit output operand and one 16-bit result input. Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.ATmega8A [DATASHEET] 10 8159E–AVR–02/2013 Figure 7-2. AVR CPU General Purpose Working Registers Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 7-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file. 7.4.1 The X-register, Y-register and Z-register The registers R26:R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as described in Figure 7-3. Figure 7-3. The X-, Y- and Z-Registers In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set Reference for details). 7.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte 15 XH XL 0 X-register 7 0 7 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 7 0 7 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z-register 7 0 7 0 R31 (0x1F) R30 (0x1E)ATmega8A [DATASHEET] 11 8159E–AVR–02/2013 locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Figure 8-2 on page 16. See Table 7-1 for Stack Pointer details. The Atmel®AVR® Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 7.5.1 SPH and SPL – Stack Pointer High and Low Register 7.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The Atmel®AVR®CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Table 7-1. Stack Pointer instructions Instruction Stack pointer Description PUSH Decremented by 1 Data is pushed onto the stack CALL ICALL RCALL Decremented by 2 Return address is pushed onto the stack with a subroutine call or interrupt POP Incremented by 1 Data is popped from the stack RET RETI Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt Bit 15 14 13 12 11 10 9 8 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 76543210 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 00000000ATmega8A [DATASHEET] 12 8159E–AVR–02/2013 Figure 7-4. The Parallel Instruction Fetches and Instruction Executions Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 7-5. Single Cycle ALU Operation 7.7 Reset and Interrupt Handling The Atmel®AVR® provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 207 for details. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of Vectors is shown in “Interrupts” on page 44. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the boot Flash section by setting the Interrupt Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 44 for more information. The Reset Vector can also be moved to the start of the boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 194. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt clk 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back T1 T2 T3 T4 clkCPUATmega8A [DATASHEET] 13 8159E–AVR–02/2013 handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in the following example. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1< xxx :. :. :. Table 12-2. Reset and Interrupt Vectors Placement BOOTRST(1) IVSEL Reset Address Interrupt Vectors Start Address 1 0 0x000 0x001 1 1 0x000 Boot Reset Address + 0x001 0 0 Boot Reset Address 0x001 0 1 Boot Reset Address Boot Reset Address + 0x001ATmega8A [DATASHEET] 46 8159E–AVR–02/2013 When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code Comments $000 rjmp RESET ; Reset handler ; $001 RESET:ldi r16,high(RAMEND); Main program start $002 out SPH,r16 ; Set Stack Pointer to top of RAM $003 ldi r16,low(RAMEND) $004 out SPL,r16 $005 sei ; Enable interrupts $006 xxx ; .org $c01 $c01 rjmp EXT_INT0 ; IRQ0 Handler $c02 rjmp EXT_INT1 ; IRQ1 Handler :. :. :. ; $c12 rjmp SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST Fuse is programmed and the boot section size set to 2K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code Comments .org $001 $001 rjmp EXT_INT0 ; IRQ0 Handler $002 rjmp EXT_INT1 ; IRQ1 Handler :. :. :. ; $012 rjmp SPM_RDY ; Store Program Memory Ready Handler ; .org $c00 $c00 rjmp RESET ; Reset handler ; $c01 RESET:ldi r16,high(RAMEND); Main program start $c02 out SPH,r16 ; Set Stack Pointer to top of RAM $c03 ldi r16,low(RAMEND) $c04 out SPL,r16 $c05 sei ; Enable interrupts $c06 xxxATmega8A [DATASHEET] 47 8159E–AVR–02/2013 When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes, and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code Comments ; .org $c00 $c00 rjmp RESET ; Reset handler $c01 rjmp EXT_INT0 ; IRQ0 Handler $c02 rjmp EXT_INT1 ; IRQ1 Handler :. :. :. ; $c12 rjmp SPM_RDY ; Store Program Memory Ready Handler $c13 RESET: ldi r16,high(RAMEND); Main program start $c14 out SPH,r16 ; Set Stack Pointer to top of RAM $c15 ldi r16,low(RAMEND) $c16 out SPL,r16 $c17 sei ; Enable interrupts $c18 xxx 12.1.1 Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. 12.2 Register Description 12.2.1 GICR – General Interrupt Control Register • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the boot Flash section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 194 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 194 for details on Boot Lock Bits. Bit 7 6 5 4 3 2 1 0 INT1 INT0 – – – – IVSEL IVCE GICR Read/Write R/W R/W R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 48 8159E–AVR–02/2013 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1< CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. 16.4 External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 16-1 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 16-1. T1/T0 Pin Sampling The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Tn_sync (To Clock Select Logic) Synchronization Edge Detector D Q D Q LE Tn D Q clkI/OATmega8A [DATASHEET] 72 8159E–AVR–02/2013 Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 16-2. Prescaler for Timer/Counter0 and Timer/Counter1(1) Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 16-1. 16.5 Register Description 16.5.1 SFIOR – Special Function IO Register • Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. PSR10 Clear clkT1 clkT0 T1 T0 clkI/O Synchronization Synchronization Bit 7 6 5 4 3 2 1 0 – – – – ACME PUD PSR2 PSR10 SFIOR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 73 8159E–AVR–02/2013 17. 16-bit Timer/Counter1 17.1 Features • True 16-bit Design (i.e., allows 16-bit PWM) • Two Independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period • Frequency Generator • External Event Counter • Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1) 17.2 Overview The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 17-1. For the actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 92.ATmega8A [DATASHEET] 74 8159E–AVR–02/2013 Figure 17-1. 16-bit Timer/Counter Block Diagram(1) Note: 1. Refer to “Pin Configurations” on page 2, Table 13-2 on page 56, and Table 13-8 on page 61 for Timer/Counter1 pin placement and description. 17.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the section “Accessing 16-bit Registers” on page 75. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT1). The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC1A/B). See “Output Compare Units” on page 81. The Compare Match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. Clock Select Timer/Counter DATA BUS OCRnA OCRnB ICRn = = TCNTn Waveform Generation Waveform Generation OCnA OCnB Noise Canceler ICPn = Fixed TOP Values Edge Detector Control Logic = 0 TOP BOTTOM Count Clear Direction TOVn (Int. Req.) OCFnA (Int. Req.) OCFnB (Int.Req.) ICFn (Int.Req.) TCCRnA TCCRnB ( From Analog Comparator Ouput ) Tn Edge Detector ( From Prescaler ) clkTnATmega8A [DATASHEET] 75 8159E–AVR–02/2013 The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICP1) or on the Analog Comparator pins (see “Analog Comparator” on page 179). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used as an alternative, freeing the OCR1A to be used as PWM output. 17.2.2 Definitions The following definitions are used extensively throughout the document: 17.2.3 Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: • All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers. • Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers. • Interrupt Vectors. • The following control bits have changed name, but have same functionality and register location: • PWM10 is changed to WGM10. • PWM11 is changed to WGM11. • CTC1 is changed to WGM12. The following bits are added to the 16-bit Timer/Counter Control Registers: • FOC1A and FOC1B are added to TCCR1A. • WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. 17.3 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. The 16-bit timer has a single 8-bit register for temporary storing of the High byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within the 16-bit timer. Accessing the Low byte triggers the 16-bit read or write operation. When the Low byte of a 16-bit register is written by the CPU, the High byte stored in the temporary register, and the Low byte written are both copied into the 16-bit register in the same clock cycle. When the Low byte of a 16-bit register is read by the CPU, the High byte of the 16-bit register is copied into the temporary register in the same clock cycle as the Low byte is read. Table 17-1. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x0000. MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation.ATmega8A [DATASHEET] 76 8159E–AVR–02/2013 Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCR1A/B 16-bit registers does not involve using the temporary register. To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the Low byte must be read before the High byte. The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. Note: 1. See “About Code Examples” on page 6. The assembly code example returns the TCNT1 value in the r17:r16 Register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. Assembly Code Example(1) :. ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H :. C Code Example(1) unsigned int i; :. /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; :.ATmega8A [DATASHEET] 77 8159E–AVR–02/2013 The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Note: 1. See “About Code Examples” on page 6. The assembly code example returns the TCNT1 value in the r17:r16 Register pair. Assembly Code Example(1) TIM16_ReadTCNT1: ; Save Global Interrupt Flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore Global Interrupt Flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save Global Interrupt Flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore Global Interrupt Flag */ SREG = sreg; return i; }ATmega8A [DATASHEET] 78 8159E–AVR–02/2013 The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Note: 1. See “About Code Examples” on page 6. The assembly code example requires that the r17:r16 Register pair contains the value to be written to TCNT1. 17.3.1 Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the High byte is the same for all registers written, then the High byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. 17.4 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS12:0) bits located in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 71. 17.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 17-2 shows a block diagram of the counter and its surroundings. Assembly Code Example(1) TIM16_WriteTCNT1: ; Save Global Interrupt Flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore Global Interrupt Flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save Global Interrupt Flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore Global Interrupt Flag */ SREG = sreg; }ATmega8A [DATASHEET] 79 8159E–AVR–02/2013 Figure 17-2. Counter Unit Block Diagram Signal description (internal signals): count Increment or decrement TCNT1 by 1. direction Select between increment and decrement. clear Clear TCNT1 (set all bits to zero). clkT1 Timer/Counter clock. TOP Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU accesses the High byte temporary register (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the clock select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare Outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 84. The Timer/Counter Overflow (TOV1) fLag is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 17.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a timestamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the Analog Comparator unit. The time-stamps can then be used to calculate freTEMP (8-bit) DATA BUS (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) Control Logic count clear direction TOVn (Int. Req.) Clock Select TOP BOTTOM Tn Edge Detector ( From Prescaler ) clkTnATmega8A [DATASHEET] 80 8159E–AVR–02/2013 quency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 17-3. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number. Figure 17-3. Input Capture Unit Block Diagram When a change of the logic level (an event) occurs on the Input Capture Pin (ICP1), alternatively on the Analog Comparator Output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (TICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the Low byte (ICR1L) and then the High byte (ICR1H). When the Low byte is read the High byte is copied into the High byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the High byte must be written to the ICR1H I/O location before the Low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 75. 17.6.1 Input Capture Pin Source The main trigger source for the Input Capture unit is the Input Capture Pin (ICP1). Timer/Counter 1 can alternatively use the Analog Comparator Output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator ICFn (Int. Req.) Analog Comparator WRITE ICRn (16-bit Register) ICRnH (8-bit) Noise Canceler ICPn Edge Detector TEMP (8-bit) DATA BUS (8-bit) ICRnL (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) ACO* ACIC* ICNC ICESATmega8A [DATASHEET] 81 8159E–AVR–02/2013 Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture Pin (ICP1) and the Analog Comparator Output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 16-1 on page 71). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 to define TOP. An Input Capture can be triggered by software by controlling the port of the ICP1 pin. 17.6.2 Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. 17.6.3 Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 17.7 Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (See “Modes of Operation” on page 84.) A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e. counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the waveform generator.ATmega8A [DATASHEET] 82 8159E–AVR–02/2013 Figure 17-4 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 17-4. Output Compare Unit, Block Diagram The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the High byte temporary register (TEMP). However, it is a good practice to read the Low byte first as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16-bit is done continuously. The High byte (OCR1xH) has to be written first. When the High byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the Low byte (OCR1xL) is written to the lower eight bits, the High byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 75. 17.7.1 Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC1x) bit. Forcing Compare Match will not set the OCF1x Flag or reload/clear the timer, but the OC1x pin will be updated as if a real Compare Match had occurred (the COM1x1:0 bits settings define whether the OC1x pin is set, cleared or toggled). OCFnx (Int.Req.) = (16-bit Comparator ) OCRnx Buffer (16-bit Register) OCRnxH Buf. (8-bit) OCnx TEMP (8-bit) DATA BUS (8-bit) OCRnxL Buf. (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) WGMn3:0 COMnx1:0 OCRnx (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) Waveform Generator TOP BOTTOMATmega8A [DATASHEET] 83 8159E–AVR–02/2013 17.7.2 Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled. 17.7.3 Using the Output Compare Unit Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT1 when using any of the Output Compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the Compare Match will be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The Compare Match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting. The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC1x value is to use the Force Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 17.8 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The waveform generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare Match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 17-5 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a System Reset occur, the OC1x Register is reset to “0”. Figure 17-5. Compare Match Output Unit, Schematic PORT DDR D Q D Q OCnx OCnx Pin D Q Waveform Generator COMnx1 COMnx0 0 1 DATABUS FOCnx clkI/OATmega8A [DATASHEET] 84 8159E–AVR–02/2013 The general I/O port function is overridden by the Output Compare (OC1x) from the waveform generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 17-2, Table 17-3 and Table 17-4 for details. The design of the Output Compare Pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 92. The COM1x1:0 bits have no effect on the Input Capture unit. 17.8.1 Compare Output Mode and Waveform Generation The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the waveform generator that no action on the OC1x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 17-2 on page 93. For fast PWM mode refer to Table 17-3 on page 93, and for phase correct and phase and frequency correct PWM refer to Table 17-4 on page 93. A change of the COM1x1:0 bits state will have effect at the first Compare Match after the bits are written. For nonPWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. 17.9 Modes of Operation The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or toggle at a Compare Match. See “Compare Match Output Unit” on page 83. For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 91. 17.9.1 Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 17.9.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for theATmega8A [DATASHEET] 85 8159E–AVR–02/2013 counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 17-6. The counter value (TCNT1) increases until a Compare Match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 17-6. CTC Mode, Timing Diagram An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered. For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined by the following equation: The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. 17.9.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare Output mode output is set on Compare Match and cleared at BOTTOM. Due to the singleslope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM TCNTn OCnA (Toggle) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) Period 1 2 3 4 (COMnA1:0 = 1) f OCnA f clk_I/O 2   N   1 + OCRnA = --------------------------------------------------ATmega8A [DATASHEET] 86 8159E–AVR–02/2013 mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 17-7. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs. Figure 17-7. Fast PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OCF1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the Compare Match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. The OCR1A Register, however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle RFPWM log  TOP + 1 log  2 = ----------------------------------- TCNTn OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) Period 1 2 3 4 5 6 7 8 OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3)ATmega8A [DATASHEET] 87 8159E–AVR–02/2013 the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to 3. See Table 17-3 on page 93. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COM1x1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A to toggle its logical level on each Compare Match (COM1A1:0 = 1). This applies only if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 17.9.4 Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 17-8. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent f OCnxPWM f clk_I/O N    1 + TOP = ----------------------------------- RPCPWM log  TOP + 1 log  2 = -----------------------------------ATmega8A [DATASHEET] 88 8159E–AVR–02/2013 compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs. Figure 17-8. Phase Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR1x Registers are written. As the third period shown in Figure 17-8 illustrates, changing the TOP actively while the Timer/Counter is running in the Phase Correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the Phase and Frequency Correct mode instead of the Phase Correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to 3. See Table 17-4 on page 93. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at Compare Match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) 1 2 3 4 TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn Period OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) f OCnxPCPWM f clk_I/O 2   N TOP = ----------------------------ATmega8A [DATASHEET] 89 8159E–AVR–02/2013 The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WMG13:0 = 11) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 17.9.5 Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x while upcounting, and set on the Compare Match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 17-8 and Figure 17-9). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 17-9. The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs. RPFCPWM log  TOP + 1 log  2 = -----------------------------------ATmega8A [DATASHEET] 90 8159E–AVR–02/2013 Figure 17-9. Phase and Frequency Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP. The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will never occur between the TCNT1 and the OCR1x. As Figure 17-9 shows the output generated is, in contrast to the Phase Correct mode, symmetrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to 3. See Table 17-4 on page 93. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at Compare Match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) 1 2 3 4 TCNTn Period OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) f OCnxPFCPWM f clk_I/O 2   N TOP = ----------------------------ATmega8A [DATASHEET] 91 8159E–AVR–02/2013 If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 17.10 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 17-10 shows a timing diagram for the setting of OCF1x. Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling Figure 17-11 shows the same timing data, but with the prescaler enabled. Figure 17-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) Figure 17-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. clkTn (clkI/O/1) OCFnx clkI/O OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clkI/O clkTn (clkI/O/8)ATmega8A [DATASHEET] 92 8159E–AVR–02/2013 Figure 17-12. Timer/Counter Timing Diagram, no Prescaling Figure 17-13 shows the same timing data, but with the prescaler enabled. Figure 17-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) 17.11 Register Description 17.11.1 TCCR1A – Timer/Counter 1 Control Register A • Bit 7:6 – COM1A1:0: Compare Output Mode for channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for channel B The COM1A1:0 and COM1B1:0 control the Output Compare Pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clkTn (clkI/O/1) clkI/O TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8) Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 TCCR1A Read/Write R/W R/W R/W R/W W W R/W R/W Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 93 8159E–AVR–02/2013 pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits setting. Table 17-2 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode (non-PWM). Table 17-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the Compare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 85. for more details. Table 17-4 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See “Phase Correct PWM Mode” on page 87. for more details. Table 17-2. Compare Output Mode, Non-PWM COM1A1/ COM1B1 COM1A0/ COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 Toggle OC1A/OC1B on Compare Match 1 0 Clear OC1A/OC1B on Compare Match (Set output to low level) 1 1 Set OC1A/OC1B on Compare Match (Set output to high level) Table 17-3. Compare Output Mode, Fast PWM(1) COM1A1/ COM1B1 COM1A0/ COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at BOTTOM, (non-inverting mode) 1 1 Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at BOTTOM, (inverting mode) Table 17-4. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/ COM1B1 COM1A0/ COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 9 or 14: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OC1A/OC1B on Compare Match when up-counting. Set OC1A/OC1B on Compare Match when downcounting. 1 1 Set OC1A/OC1B on Compare Match when up-counting. Clear OC1A/OC1B on Compare Match when downcounting.ATmega8A [DATASHEET] 94 8159E–AVR–02/2013 • Bit 3 – FOC1A: Force Output Compare for channel A • Bit 2 – FOC1B: Force Output Compare for channel B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate Compare Match is forced on the waveform generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 17-5. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 84.) Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. Table 17-5. Waveform Generation Mode Bit Description Mode WGM13 WGM12 (CTC1) WGM11 (PWM11) WGM10 (PWM10) Timer/Counter Mode of Operation(1) TOP Update of OCR1x TOV1 Flag Set on 0 0 0 0 0 Normal 0xFFFF Immediate MAX 1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM 2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 0 CTC OCR1A Immediate MAX 5 0 1 0 1 Fast PWM, 8-bit 0x00FF BOTTOM TOP 6 0 1 1 0 Fast PWM, 9-bit 0x01FF BOTTOM TOP 7 0 1 1 1 Fast PWM, 10-bit 0x03FF BOTTOM TOP 8 1 0 0 0 PWM, Phase and Frequency Correct ICR1 BOTTOM BOTTOM 9 1 0 0 1 PWM, Phase and Frequency Correct OCR1A BOTTOM BOTTOM 10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM 11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM 12 1 1 0 0 CTC ICR1 Immediate MAX 13 1 1 0 1 (Reserved) – – – 14 1 1 1 0 Fast PWM ICR1 BOTTOM TOP 15 1 1 1 1 Fast PWM OCR1A BOTTOM TOPATmega8A [DATASHEET] 95 8159E–AVR–02/2013 17.11.2 TCCR1B – Timer/Counter 1 Control Register B • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. • Bit 6 – ICES1: Input Capture Edge Select This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description. • Bit 2:0 – CS12:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see Figure 17-10 and Figure 17-11. If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 17-6. Clock Select Bit Description CS12 CS11 CS10 Description 0 0 0 No clock source. (Timer/Counter stopped) 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge.ATmega8A [DATASHEET] 96 8159E–AVR–02/2013 17.11.3 TCNT1H and TCNT1L – Timer/Counter 1 The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and Low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 75. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a Compare Match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the Compare Match on the following timer clock for all compare units. 17.11.4 OCR1AH and OCR1AL– Output Compare Register 1 A 17.11.5 OCR1BH and OCR1BL – Output Compare Register 1 B The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare Interrupt, or to generate a waveform output on the OC1x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and Low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 75. 17.11.6 ICR1H and ICR1L – Input Capture Register 1 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator Output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High byte Register Bit 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCR1A[15:8] OCR1AH OCR1A[7:0] OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCR1B[15:8] OCR1BH OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 97 8159E–AVR–02/2013 (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 75. 17.11.7 TIMSK(1) – Timer/Counter Interrupt Mask Register Note: 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. • Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture Interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 44) is executed when the ICF1 Flag, located in TIFR, is set. • Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 44) is executed when the OCF1A Flag, located in TIFR, is set. • Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 44) is executed when the OCF1B Flag, located in TIFR, is set. • Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 44) is executed when the TOV1 Flag, located in TIFR, is set. 17.11.8 TIFR(1) – Timer/Counter Interrupt Flag Register Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. • Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag. Bit 7 6 5 4 3 2 1 0 OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 TIMSK Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 98 8159E–AVR–02/2013 OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. • Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. • Bit 2 – TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGM13:0 bits setting. In normal and CTC modes, the TOV1 Flag is set when the timer overflows. Refer to Table 17-5 on page 94 for the TOV1 Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.ATmega8A [DATASHEET] 99 8159E–AVR–02/2013 18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 18.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV2 and OCF2) • Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock 18.2 Overview Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 18-1. For the actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 112. Figure 18-1. 8-bit Timer/Counter Block Diagram Timer/Counter DATA BUS = TCNTn Waveform Generation OCn = 0 Control Logic = 0xFF BOTTOM TOP count clear direction TOVn (Int. Req.) OCn (Int. Req.) Synchronization Unit OCRn TCCRn ASSRn Status Flags clkI/O clkASY Synchronized Status Flags asynchronous Mode Select (ASn) TOSC1 T/C Oscillator TOSC2 Prescaler clkTn clkI/OATmega8A [DATASHEET] 100 8159E–AVR–02/2013 18.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT2). The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC2). For details, see “Output Compare Unit” on page 101. The Compare Match event will also set the Compare Flag (OCF2) which can be used to generate an Output Compare interrupt request. 18.2.2 Definitions Many register and bit references in this document are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used (i.e., TCNT2 for accessing Timer/Counter2 counter value and so on). The definitions in Table 18-1 are also used extensively throughout the document. 18.3 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “Asynchronous Operation of the Timer/Counter” on page 109. For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 71. 18.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 18-2 shows a block diagram of the counter and its surrounding environment. Table 18-1. Definitions BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The assignment is dependent on the mode of operation.ATmega8A [DATASHEET] 101 8159E–AVR–02/2013 Figure 18-2. Counter Unit Block Diagram Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkT2 Timer/Counter clock. TOP Signalizes that TCNT2 has reached maximum value. BOTTOM Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter Control Register (TCCR2). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare Output OC2. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 104. The Timer/Counter Overflow (TOV2) Flag is set according to the mode of operation selected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt. 18.5 Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF2 Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 Flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the WGM21:0 bits and Compare Output mode (COM21:0) bits. The max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see “Modes of Operation” on page 104). Figure 18-3 shows a block diagram of the Output Compare unit. DATA BUS TCNTn Control Logic count TOVn (Int. Req.) BOTTOM TOP direction clear TOSC1 T/C Oscillator TOSC2 Prescaler clkI/O clk TnATmega8A [DATASHEET] 102 8159E–AVR–02/2013 Figure 18-3. Output Compare Unit, Block Diagram The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double buffering is disabled the CPU will access the OCR2 directly. 18.5.1 Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the OCF2 Flag or reload/clear the timer, but the OC2 pin will be updated as if a real Compare Match had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled). 18.5.2 Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 18.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2 value, the Compare Match will be OCFn (Int. Req.) = (8-bit Comparator ) OCRn OCxy DATA BUS TCNTn WGMn1:0 Waveform Generator TOP FOCn COMn1:0 BOTTOMATmega8A [DATASHEET] 103 8159E–AVR–02/2013 missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value even when changing between waveform generation modes. Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately. 18.6 Compare Match Output Unit The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses the COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match. Also, the COM21:0 bits control the OC2 pin output source. Figure 18-4 shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference is for the internal OC2 Register, not the OC2 pin. Figure 18-4. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC2) from the waveform generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as output before the OC2 value is visible on the pin. The port override function is independent of the Waveform Generation mode. PORT DDR D Q D Q OCn OCn Pin D Q Waveform Generator COMn1 COMn0 0 1 DATABUS FOCn clkI/OATmega8A [DATASHEET] 104 8159E–AVR–02/2013 The design of the Output Compare Pin logic allows initialization of the OC2 state before the output is enabled. Note that some COM21:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 112. 18.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM21:0 = 0 tells the waveform generator that no action on the OC2 Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 18-3 on page 112. For fast PWM mode, refer to Table 18-4 on page 113, and for phase correct PWM refer to Table 18-5 on page 113. A change of the COM21:0 bits state will have effect at the first Compare Match after the bits are written. For nonPWM modes, the action can be forced to have immediate effect by using the FOC2 strobe bits. 18.7 Modes of Operation The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM21:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM21:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (see “Compare Match Output Unit” on page 103). For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 108. 18.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8- bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 18.7.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 18-5. The counter value (TCNT2) increases until a Compare Match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared.ATmega8A [DATASHEET] 105 8159E–AVR–02/2013 Figure 18-5. CTC Mode, Timing Diagram An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2 is lower than the current value of TCNT2, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The waveform frequency is defined by the following equation: The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 18.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 18-6. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. TCNTn OCn (Toggle) OCn Interrupt Flag Set Period 1 2 3 4 (COMn1:0 = 1) f OCn f clk_I/O 2   N   1 + OCRn = ----------------------------------------------ATmega8A [DATASHEET] 106 8159E–AVR–02/2013 Figure 18-6. Fast PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM21:0 to 3 (see Table 18-4 on page 113). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2 Register at the Compare Match between OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2 to toggle its logical level on each Compare Match (COM21:0 = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2 is set to zero. This feature is similar to the OC2 toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 18.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2 while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation TCNTn OCRn Update and TOVn Interrupt Flag Set Period 1 2 3 OCn OCn (COMn1:0 = 2) (COMn1:0 = 3) OCRn Interrupt Flag Set 4 5 6 7 f OCnPWM f clk_I/O N  256 = ------------------ATmega8A [DATASHEET] 107 8159E–AVR–02/2013 has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 18-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. Figure 18-7. Phase Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM21:0 to 3 (see Table 18-5 on page 113). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2 Register at the Compare Match between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the OC2 Register at Compare Match between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. TOVn Interrupt Flag Set OCn Interrupt Flag Set 1 2 3 TCNTn Period OCn OCn (COMn1:0 = 2) (COMn1:0 = 3) OCRn Update f OCnPCPWM f clk_I/O N  510 = ------------------ATmega8A [DATASHEET] 108 8159E–AVR–02/2013 At the very start of period 2 in Figure 18-7 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match: • OCR2A changes its value from MAX, like in Figure 18-7. When the OCR2A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 18.8 Timer/Counter Timing Diagrams The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In Asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 18-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 18-8. Timer/Counter Timing Diagram, no Prescaling Figure 18-9 shows the same timing data, but with the prescaler enabled. Figure 18-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) Figure 18-10 shows the setting of OCF2 in all modes except CTC mode. clkTn (clkI/O/1) TOVn clkI/O TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8)ATmega8A [DATASHEET] 109 8159E–AVR–02/2013 Figure 18-10. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) Figure 18-11 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 18-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8) 18.9 Asynchronous Operation of the Timer/Counter 18.9.1 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2, and TCCR2. 4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB. 5. Clear the Timer/Counter2 Interrupt Flags. 6. Enable interrupts, if needed. OCFn OCRn TCNTn OCRn Value OCRn - 1 OCRn OCRn + 1 OCRn + 2 clkI/O clkTn (clkI/O/8) OCFn OCRn TCNTn (CTC) TOP TOP - 1 TOP BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8)ATmega8A [DATASHEET] 110 8159E–AVR–02/2013 • The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be more than four times the Oscillator frequency. • When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2 write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register – ASSR has been implemented. • When entering Power-save mode after having written to TCNT2, OCR2, or TCCR2, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR2 or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a Compare Match interrupt, and the MCU will not wake up. • If Timer/Counter2 is used to wake the device up from Power-save mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save or Extended Standby mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2, TCNT2, or OCR2. 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. 3. Enter Power-save or Extended Standby mode. • When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or Wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after Power-up or Wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake up from Power-save or Extended Standby mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. • Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 1. Write any value to either of the registers OCR2 or TCCR2. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT2. • During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the ATmega8A [DATASHEET] 111 8159E–AVR–02/2013 processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare Pin is changed on the timer clock and is not synchronized to the processor clock. 18.10 Timer/Counter Prescaler Figure 18-12. Prescaler for Timer/Counter2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkI/O. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port B. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. Applying an external clock source to TOSC1 is not recommended. For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSR2 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler. 10-BIT T/C PRESCALER TIMER/COUNTER2 CLOCK SOURCE clkI/O clkT2S TOSC1 AS2 CS20 CS21 CS22 clkT2S/8 clkT2S/64 clkT2S/128 clkT2S/1024 clkT2S/256 clkT2S/32 0 PSR2 Clear clkT2ATmega8A [DATASHEET] 112 8159E–AVR–02/2013 18.11 Register Description 18.11.1 TCCR2 – Timer/Counter Control Register • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate Compare Match is forced on the waveform generation unit. The OC2 output is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare. A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2 as TOP. The FOC2 bit is always read as zero. • Bit 6,3 – WGM21:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 18-2 and “Modes of Operation” on page 104. Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. • Bit 5:4 – COM21:0: Compare Match Output Mode These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 18-3 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). Bit 7 6 5 4 3 2 1 0 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 TCCR2 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 18-2. Waveform Generation Mode Bit Description Mode WGM21 (CTC2) WGM20 (PWM2) Timer/Counter Mode of Operation(1) TOP Update of OCR2 TOV2 Flag Set 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR2 Immediate MAX 3 1 1 Fast PWM 0xFF BOTTOM MAX Table 18-3. Compare Output Mode, Non-PWM Mode COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 0 1 Toggle OC2 on Compare Match 1 0 Clear OC2 on Compare Match 1 1 Set OC2 on Compare MatchATmega8A [DATASHEET] 113 8159E–AVR–02/2013 Table 18-4 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 105 for more details. Table 18-5 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode. Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 106 for more details. • Bit 2:0 – CS22:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see Table 18-6. 18.11.2 TCNT2 – Timer/Counter Register Table 18-4. Compare Output Mode, Fast PWM Mode(1) COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 0 1 Reserved 1 0 Clear OC2 on Compare Match, set OC2 at BOTTOM, (non-inverting mode) 1 1 Set OC2 on Compare Match, clear OC2 at BOTTOM, (inverting mode) Table 18-5. Compare Output Mode, Phase Correct PWM Mode(1) COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 0 1 Reserved 1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when downcounting. 1 1 Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match when downcounting. Table 18-6. Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkT2S/(No prescaling) 0 1 0 clkT2S/8 (From prescaler) 0 1 1 clkT2S/32 (From prescaler) 1 0 0 clkT2S/64 (From prescaler) 1 0 1 clkT2S/128 (From prescaler) 1 1 0 clkT2S/256 (From prescaler) 1 1 1 clkT2S/1024 (From prescaler) Bit 7 6 5 4 3 2 1 0 TCNT2[7:0] TCNT2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 114 8159E–AVR–02/2013 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register. 18.11.3 OCR2 – Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2 pin. 18.11.4 ASSR – Asynchronous Status Register • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter 2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2, and TCCR2 might be corrupted. • Bit 2 – TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. • Bit 1 – OCR2UB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set. When OCR2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2 is ready to be updated with a new value. • Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set. When TCCR2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is read. Bit 7 6 5 4 3 2 1 0 OCR2[7:0] OCR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 – – – – AS2 TCN2UB OCR2UB TCR2UB ASSR Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 115 8159E–AVR–02/2013 18.11.5 TIMSK – Timer/Counter Interrupt Mask Register • Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter2 occurs (i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR). • Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR). 18.11.6 TIFR – Timer/Counter Interrupt Flag Register • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare Match Interrupt is executed. • Bit 6 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 18.11.7 SFIOR – Special Function IO Register • Bit 1 – PSR2: Prescaler Reset Timer/Counter2 When this bit is written to one, the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in Asynchronous mode, the bit will remain one until the prescaler has been reset. Bit 7 6 5 4 3 2 1 0 OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 TIMSK Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 – – – – ACME PUD PSR2 PSR10 SFIOR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 116 8159E–AVR–02/2013 19. Serial Peripheral Interface – SPI 19.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode 19.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8A and peripheral devices or between several AVR devices. Figure 19-1. SPI Block Diagram(1) Note: 1. Refer to “Pin Configurations” on page 2, and Table 13-2 on page 56 for SPI pin placement. The interconnection between Master and Slave CPUs with SPI is shown in Figure 19-2. The system consists of two Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low SPI2X SPI2X DIVIDER /2/4/8/16/32/64/128ATmega8A [DATASHEET] 117 8159E–AVR–02/2013 the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI interrupt enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 19-2. SPI Master-Slave Interconnection The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: longer than 2 CPU clock cycles High period: longer than 2 CPU clock cycles. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 19-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 54. MSB MASTER LSB 8 BIT SHIFT REGISTER MSB SLAVE LSB 8 BIT SHIFT REGISTER MISO MOSI SPI CLOCK GENERATOR SCK SS MISO MOSI SCK SS VCC SHIFT ENABLEATmega8A [DATASHEET] 118 8159E–AVR–02/2013 Note: 1. See “Port B Pins Alternate Functions” on page 56 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. Table 19-1. SPI Pin Overrides(1) Pin Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined InputATmega8A [DATASHEET] 119 8159E–AVR–02/2013 Note: 1. See “About Code Examples” on page 6. Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<>8); UBRRL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSRB = (1<> 1) & 0x01; return ((resh << 8) | resl); }ATmega8A [DATASHEET] 137 8159E–AVR–02/2013 20.6.9 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero. When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete Interrupt will be executed as long as the RXC Flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR in order to clear the RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates. 20.6.10 Receiver Error Flags The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity Error (PE). All can be accessed by reading UCSRA. Common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRA must be read before the receive buffer (UDR), since reading the UDR I/O location changes the buffer read location. Another equality for the error flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRA is written for upward compatibility of future USART implementations. None of the error flags can generate interrupts. The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FE Flag is zero when the stop bit was correctly read (as one), and the FE Flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRA. The Data OverRun (DOR) Flag indicates data loss due to a Receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DOR Flag is set there was one or more serial frame lost between the frame last read from UDR, and the next frame read from UDR. For compatibility with future devices, always write this bit to zero when writing to UCSRA. The DOR Flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (PE) Flag indicates that the next frame in the receive buffer had a parity error when received. If parity check is not enabled the PE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 130 and “Parity Checker” on page 137. 20.6.11 Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (PE) Flag can then be read by software to check if the frame had a parity error. The PE bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. 20.6.12 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the Receiver will no longer override the normal functionATmega8A [DATASHEET] 138 8159E–AVR–02/2013 of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost. 20.6.13 Flushing the Receive Buffer The Receiver buffer FIFO will be flushed when the Receiver is disabled (i.e., the buffer will be emptied of its contents). Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC Flag is cleared. The following code example shows how to flush the receive buffer. Note: 1. See “About Code Examples” on page 6. 20.7 Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 20.7.1 Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 20-5 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). Figure 20-5. Start Bit Sampling When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The clock recovery logic Assembly Code Example(1) USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush C Code Example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1< 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck  12MHz High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck  12MHz 25.9.1 Serial Programming Algorithm When writing serial data to the ATmega8A, data is clocked on the rising edge of SCK. When reading data from the ATmega8A, data is clocked on the falling edge of SCK. See Figure 25-8 for timing details. Table 25-14. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB3 I Serial data in MISO PB4 O Serial data out SCK PB5 I Serial clock VCC GND XTAL1 SCK MISO MOSI RESET PB3 PB4 PB5 +2.7 - 5.5V AVCC +2.7 - 5.5V (2)ATmega8A [DATASHEET] 221 8159E–AVR–02/2013 To program and verify the ATmega8A in the Serial Programming mode, the following sequence is recommended (See four byte instruction formats in Table 25-16): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during Power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20 ms and enable Serial Programming by sending the Programming Enable serial instruction to pin MOSI. 3. The Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The page size is found in Table 25-5 on page 210. The memory page is loaded one byte at a time by supplying the 5LSB of the address and data together with the Load Program memory Page instruction. To ensure correct loading of the page, the data Low byte must be loaded before data High byte is applied for a given address. The Program memory Page is stored by loading the Write Program memory Page instruction with the 7 MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 25-15). 5. Note: If other commands than polling (read) are applied before any write operation (FLASH, EEPROM, Lock Bits, Fuses) is completed, it may result in incorrect programming. 6. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 25-15 on page 222). In a chip erased device, no 0xFFs in the data file(s) need to be programmed. 7. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 8. At the end of the programming session, RESET can be set high to commence normal operation. 9. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off 25.9.2 Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value 0xFF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming this value, the user will have to wait for at least tWD_FLASH before programming the next page. As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. See Table 97 for tWD_FLASH value. 25.9.3 Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value 0xFF, but the user should have the following in mind: As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is Re-ATmega8A [DATASHEET] 222 8159E–AVR–02/2013 programmed without chip-erasing the device. In this case, data polling cannot be used for the value 0xFF, and the user will have to wait at least tWD_EEPROM before programming the next byte. See Table 25-15 for tWD_EEPROM value. Figure 25-8. Serial Programming Waveforms Table 25-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FUSE 4.5 ms tWD_FLASH 4.5 ms tWD_EEPROM 9.0 ms tWD_ERASE 9.0 ms MSB MSB LSB LSB SERIAL CLOCK INPUT (SCK) SERIAL DATA INPUT (MOSI) (MISO) SAMPLE SERIAL DATA OUTPUTATmega8A [DATASHEET] 223 8159E–AVR–02/2013 Note: a = address high bits b = address low bits H = 0 – Low byte, 1 – High byte o = data out i = data in x = don’t care Table 25-16. Serial Programming Instruction Set Instruction Instruction Format Byte 1 Byte 2 Byte 3 Byte4 Operation Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. Read Program Memory 0010 H000 0000 aaaa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b. Load Program Memory Page 0100 H000 0000 xxxx xxxb bbbb iiii iiii Write H (high or low) data i to Program memory page at word address b. Data Low byte must be loaded before Data High byte is applied within the same address. Write Program Memory Page 0100 1100 0000 aaaa bbbx xxxx xxxx xxxx Write Program memory Page at address a:b. Read EEPROM Memory 1010 0000 00xx xxxa bbbb bbbb oooo oooo Read data o from EEPROM memory at address a:b. Write EEPROM Memory 1100 0000 00xx xxxa bbbb bbbb iiii iiii Write data i to EEPROM memory at address a:b. Read Lock Bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock Bits. “0” = programmed, “1” = unprogrammed. See Table 25-1 on page 207 for details. Write Lock Bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock Bits. Set bits = “0” to program Lock Bits. See Table 25- 1 on page 207 for details. Read Signature Byte 0011 0000 00xx xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b. Write Fuse Bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. See Table 25-4 on page 209 for details. Write Fuse High Bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. See Table 25-3 on page 208 for details. Read Fuse Bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse Bits. “0” = programmed, “1” = unprogrammed. See Table 25-4 on page 209 for details. Read Fuse High Bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse high bits. “0” = programmed, “1” = unprogrammed. See Table 25-3 on page 208 for details. Read Calibration Byte 0011 1000 00xx xxxx 0000 00bb oooo oooo Read Calibration ByteATmega8A [DATASHEET] 224 8159E–AVR–02/2013 25.9.4 SPI Serial Programming Characteristics For characteristics of the SPI module, see “SPI Timing Characteristics” on page 230.ATmega8A [DATASHEET] 225 8159E–AVR–02/2013 26. Electrical Characteristics – TA = -40°C to 85°C Note: Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 26.2 DC Characteristics 26.1 Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ................................................ 40.0mA DC Current VCC and GND Pins................................. 300.0mA TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min Typ Max Units VIL Input Low Voltage except XTAL1 and RESET pins VCC = 2.7V - 5.5V -0.5 0.2 VCC(1) V VIH Input High Voltage except XTAL1 and RESET pins VCC = 2.7V - 5.5V 0.6 VCC(2) VCC + 0.5 V VIL1 Input Low Voltage XTAL1 pin VCC = 2.7V - 5.5V -0.5 0.1 VCC(1) V VIH1 Input High Voltage XTAL 1 pin VCC = 2.7V - 5.5V 0.8 VCC(2) VCC + 0.5 V VIL2 Input Low Voltage RESET pin VCC = 2.7V - 5.5V -0.5 0.2 VCC V VIH2 Input High Voltage RESET pin VCC = 2.7V - 5.5V 0.9 VCC(2) VCC + 0.5 V VIL3 Input Low Voltage RESET pin as I/O VCC = 2.7V - 5.5V -0.5 0.2 VCC V VIH3 Input High Voltage RESET pin as I/O VCC = 2.7V - 5.5V 0.6 VCC(2) 0.7 VCC(2) VCC + 0.5 V VOL Output Low Voltage(3) (Ports B,C,D) I OL = 20mA, VCC = 5V IOL = 10mA, VCC = 3V 0.9 0.6 V V VOH Output High Voltage(4) (Ports B,C,D) I OH = -20mA, VCC = 5V IOH = -10mA, VCC = 3V 4.2 2.2 V V IIL Input Leakage Current I/O Pin Vcc = 5.5V, pin low (absolute value) 1 µA IIH Input Leakage Current I/O Pin Vcc = 5.5V, pin high (absolute value) 1 µAATmega8A [DATASHEET] 226 8159E–AVR–02/2013 Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low 2. “Min” means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: PDIP, TQFP, and QFN/MLF Package: 1] The sum of all IOL, for all ports, should not exceed 300mA. 2] The sum of all IOL, for ports C0 - C5 should not exceed 100mA. 3] The sum of all IOL, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: PDIP, TQFP, and QFN/MLF Package: 1] The sum of all IOH, for all ports, should not exceed 300mA. 2] The sum of all IOH, for port C0 - C5, should not exceed 100mA. 3] The sum of all IOH, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum VCC for Power-down is 2.5V. RRST Reset Pull-up Resistor 30 80 k Rpu I/O Pin Pull-up Resistor 20 50 k I CC Power Supply Current Active 4MHz, VCC = 3V 2 5 mA Active 8MHz, VCC = 5V 6 15 mA Idle 4MHz, VCC = 3V 0.5 2 mA Idle 8MHz, VCC = 5V 2.2 7 mA Power-down mode(5) WDT enabled, VCC = 3V <10 28 µA WDT disabled, VCC = 3V <1 3 µA VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 40 mV IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 -50 50 nA tACPD Analog Comparator Propagation Delay VCC = 2.7V VCC = 5.0V 750 500 ns TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min Typ Max UnitsATmega8A [DATASHEET] 227 8159E–AVR–02/2013 26.3 Speed Grades Figure 26-1. Maximum Frequency vs. Vcc 26.4 Clock Characteristics 26.4.1 External Clock Drive Waveforms Figure 26-2. External Clock Drive Waveforms 26.4.2 External Clock Drive 2.7V 4.5V 5.5V Safe Operating Area 16 MHz 8 MHz VIL1 VIH1 Table 26-1. External Clock Drive Symbol Parameter VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V Min Max Min Max Units 1/tCLCL Oscillator Frequency 0 8 0 16 MHz tCLCL Clock Period 125 62.5 ns tCHCX High Time 50 25 ns tCLCX Low Time 50 25 ns tCLCH Rise Time 1.6 0.5 s tCHCL Fall Time 1.6 0.5 s tCLCL Change in period from one clock cycle to the next 2 2%ATmega8A [DATASHEET] 228 8159E–AVR–02/2013 Notes: 1. R should be in the range 3 k - 100 k, and C should be at least 20 pF. The C values given in the table includes pin capacitance. This will vary with package type. 2. The frequency will vary with package type and board layout. 26.5 System and Reset Characteristics Notes: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling). 2. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 and BODLEVEL = 0 for ATmega8A. Table 26-2. External RC Oscillator, Typical Frequencies R [k] (1) C [pF] f(2) 33 22 650kHz 10 22 2.0MHz Table 26-3. Reset, Brown-out and Internal Voltage Reference Characteristics Symbol Parameter Condition Min Typ Max Units VPOT Power-on Reset Threshold Voltage (rising)(1) 1.4 2.3 V Power-on Reset Threshold Voltage (falling) 1.3 2.3 V VRST RESET Pin Threshold Voltage 0.2 0.9 VCC tRST Minimum pulse width on RESET Pin 1.5 µs VBOT Brown-out Reset Threshold Voltage(2) BODLEVEL = 1 2.40 2.60 2.90 V BODLEVEL = 0 3.70 4.00 4.50 tBOD Minimum low voltage period for Brownout Detection BODLEVEL = 1 2 µs BODLEVEL = 0 2 µs VHYST Brown-out Detector hysteresis 130 mV VBG Bandgap reference voltage 1.15 1.23 1.35 V tBG Bandgap reference start-up time 40 70 µs IBG Bandgap reference current consumption 10 µsATmega8A [DATASHEET] 229 8159E–AVR–02/2013 26.6 Two-wire Serial Interface Characteristics Table 26-4 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8A Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 26-3. Notes: 1. In ATmega8A, this parameter is characterized and not 100% tested. 2. Required only for fSCL > 100kHz. Table 26-4. Two-wire Serial Bus Requirements Symbol Parameter Condition Min Max Units VIL Input Low-voltage -0.5 0.3 VCC V VIH Input High-voltage 0.7 VCC VCC + 0.5 V Vhys(1) Hysteresis of Schmitt Trigger Inputs 0.05 VCC(2) – V VOL(1) Output Low-voltage 3mA sink current 0 0.4 V tr (1) Rise Time for both SDA and SCL 20 + 0.1Cb (3)(2) 300 ns tof (1) Output Fall Time from VIHmin to VILmax 10 pF < Cb < 400 pF(3) 20 + 0.1Cb (3)(2) 250 ns tSP(1) Spikes Suppressed by Input Filter 0 50(2) ns Ii Input Current each I/O Pin 0.1VCC < Vi < 0.9VCC -10 10 µA Ci (1) Capacitance for each I/O Pin – 10 pF fSCL SCL Clock Frequency fCK(4) > max(16fSCL, 250kHz)(5) 0 400 kHz Rp Value of Pull-up resistor fSCL  100kHz fSCL > 100kHz tHD;STA Hold Time (repeated) START Condition fSCL  100kHz 4.0 – µs fSCL > 100kHz 0.6 – µs tLOW Low Period of the SCL Clock fSCL  100kHz(6) 4.7 – µs fSCL > 100kHz(7) 1.3 – µs tHIGH High period of the SCL clock fSCL  100kHz 4.0 – µs fSCL > 100kHz 0.6 – µs tSU;STA Set-up time for a repeated START condition fSCL  100kHz 4.7 – µs fSCL > 100kHz 0.6 – µs tHD;DAT Data hold time fSCL  100kHz 0 3.45 µs fSCL > 100kHz 0 0.9 µs tSU;DAT Data setup time fSCL  100kHz 250 – ns fSCL > 100kHz 100 – ns tSU;STO Setup time for STOP condition fSCL  100kHz 4.0 – µs fSCL > 100kHz 0.6 – µs tBUF Bus free time between a STOP and START condition fSCL  100kHz 4.7 – µs fSCL > 100kHz 1.3 – µs VCC – 0,4V 3mA ---------------------------- 1000ns Cb -------------------  VCC – 0,4V 3mA ---------------------------- 300ns Cb ---------------- ATmega8A [DATASHEET] 230 8159E–AVR–02/2013 3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency 5. This requirement applies to all ATmega8A Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement. 6. The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6MHz for the low time requirement to be strictly met at fSCL = 100kHz. 7. The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308kHz when fCK = 8MHz. Still, ATmega8A devices connected to the bus may communicate at full speed (400kHz) with other ATmega8A devices, as well as any other device with a proper tLOW acceptance margin. Figure 26-3. Two-wire Serial Bus Timing 26.7 SPI Timing Characteristics See Figure 26-4 and Figure 26-5 for details. Note: 1. In SPI Programming mode the minimum SCK high/low period is: - 2tCLCL for fCK < 12MHz - 3tCLCL for fCK > 12MHz t SU;STA t LOW t HIGH t LOW t of t HD;STA t HD;DAT t SU;DAT t SU;STO t BUF SCL SDA t r Table 26-5. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 19-4 ns 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 • tSCK 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave 15 10 SCK period Slave 4 • tck 11 SCK high/low(1) Slave 2 • tck 12 Rise/Fall time Slave 1.6 13 Setup Slave 10 14 Hold Slave 10 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Salve 2 • tckATmega8A [DATASHEET] 231 8159E–AVR–02/2013 Figure 26-4. SPI interface timing requirements (Master Mode) Figure 26-5. SPI interface timing requirements (Slave Mode) MOSI (Data Output) SCK (CPOL = 1) MISO (Data Input) SCK (CPOL = 0) SS MSB LSB MSB LSB ... ... 6 1 2 2 4 5 3 7 8 MISO (Data Output) SCK (CPOL = 1) MOSI (Data Input) SCK (CPOL = 0) SS MSB LSB MSB LSB ... ... 10 11 11 13 14 12 15 17 9 X 16 18ATmega8A [DATASHEET] 232 8159E–AVR–02/2013 26.8 ADC Characteristics Notes: 1. Values are guidelines only. 2. Minimum for AVCC is 2.7V. 3. Maximum for AVCC is 5.5V. 4. Maximum conversion time is 1/50kHz*25 = 0.5 ms. Table 26-6. ADC Characteristics Symbol Parameter Condition Min(1) Typ(1) Max(1) Units Resolution Single Ended Conversion 10 Bits Absolute accuracy (Including INL, DNL, Quantization Error, Gain, and Offset Error) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 1.75 LSB Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1MHz 3 LSB Integral Non-linearity (INL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 0.75 LSB Differential Non-linearity (DNL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 0.5 LSB Gain Error Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 1 LSB Offset Error Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 1 LSB Conversion Time(4) Free Running Conversion 13 260 µs Clock Frequency 50 1000 kHz AVCC Analog Supply Voltage VCC - 0.3(2) VCC + 0.3(3) V VREF Reference Voltage 2.0 AVCC V VIN Input voltage GND VREF V Input bandwidth 38.5 kHz VINT Internal Voltage Reference 2.3 2.56 2.8 V RREF Reference Input Resistance 32 k RAIN Analog Input Resistance 55 100 MATmega8A [DATASHEET] 233 8159E–AVR–02/2013 27. Electrical Characteristics – TA = -40°C to 105°C Absolute Maximum Ratings* 27.1 DC Characteristics Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low Operating Temperature.................................. -55C to +125C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins................................ 200.0 mA TA = -40C to 105C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. Typ. Max. Units VIL Input Low Voltage, Except XTAL1 and RESET pin VCC = 2.7V - 5.5V -0.5 0.2VCC(1) V VIL1 Input Low Voltage, XTAL1 pin VCC = 2.7V - 5.5V -0.5 0.1VCC(1) V VIL2 Input Low Voltage, RESET pin VCC = 2.7V - 5.5V -0.5 0.1VCC(1) V VIH Input High Voltage, Except XTAL1 and RESET pins VCC = 2.7V - 5.5V 0.6VCC(2) VCC + 0.5 V VIH1 Input High Voltage, XTAL1 pin VCC = 2.7V - 5.5V 0.8VCC(2) VCC + 0.5 V VIH2 Input High Voltage, RESET pin VCC = 2.7V - 5.5V 0.9VCC(2) VCC + 0.5 V VOL Output Low Voltage(3), Port B (except RESET) I OL =20 mA, VCC = 5V IOL =10 mA, VCC = 3V 0.8 0.6 V VOH Output High Voltage(4), Port B (except RESET) I OH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V 4.0 2.2 V IIL Input Leakage Current I/O Pin 3 µA IIH Input Leakage Current I/O Pin 3 µA RRST Reset Pull-up Resistor 30 80 k RPU I/O Pin Pull-up Resistor 20 50 k VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 20 mV IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 -50 50 nAATmega8A [DATASHEET] 234 8159E–AVR–02/2013 2. “Min” means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: PDIP, TQFP, and QFN/MLF Package: 1] The sum of all IOL, for all ports, should not exceed 300 mA. 2] The sum of all IOL, for ports C0 - C5 should not exceed 100 mA. 3] The sum of all IOL, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: PDIP, TQFP, and QFN/MLF Package: 1] The sum of all IOH, for all ports, should not exceed 300 mA. 2] The sum of all IOH, for port C0 - C5, should not exceed 100 mA. 3] The sum of all IOH, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. Note: 1. The current consumption values include input leakage current. 27.1.1 ATmega8A DC Characteristics Table 27-1. TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. Typ. Max. Units ICC Power Supply Current Active 4 MHz, VCC = 3V 6 mA Active 8 MHz, VCC = 5V 15 mA Idle 4 MHz, VCC = 3V 3 mA Idle 8 MHz, VCC = 5V 8 mA Power-down mode(1) WDT enabled, VCC = 3V 35 µA WDT disabled, VCC = 3V 6 µAATmega8A [DATASHEET] 235 8159E–AVR–02/2013 28. Typical Characteristics – TA = -40°C to 85°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with Rail-to-Rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 28.1 Active Supply Current Figure 28-1. Active Supply Current vs. Frequency (0.1 - 1.0MHz) 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 2.7 V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA)ATmega8A [DATASHEET] 236 8159E–AVR–02/2013 Figure 28-2. Active Supply Current vs. Frequency (1 - 16MHz) Figure 28-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 0 2 4 6 8 10 12 14 0246 8 10 12 14 16 Frequency (MHz) ICC (mA) 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 2.7 V 85 °C 25 °C -40 °C 3 4 5 6 7 8 9 10 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA)ATmega8A [DATASHEET] 237 8159E–AVR–02/2013 Figure 28-4. Active Supply Current vs. VCC (Internal RC Oscillator, 4MHz) Figure 28-5. Active Supply Current vs. VCC (Internal RC Oscillator, 2MHz) 85 °C 25 °C -40 °C 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85 °C 25 °C -40 °C 1.2 1.6 2 2.4 2.8 3.2 3.6 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA)ATmega8A [DATASHEET] 238 8159E–AVR–02/2013 Figure 28-6. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) Figure 28-7. Active Supply Current vs. VCC (32kHz External Oscillator) 85 °C 25 °C -40 °C 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 25 °C 40 45 50 55 60 65 70 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA)ATmega8A [DATASHEET] 239 8159E–AVR–02/2013 28.2 Idle Supply Current Figure 28-8. Idle Supply Current vs. Frequency (0.1 - 1.0MHz) Figure 28-9. Idle Supply Current vs. Frequency (1 - 16MHz) 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 2.7 V 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA) 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 2.7 V 0 1 2 3 4 5 6 0246 8 10 12 14 16 Frequency (MHz) ICC (mA)ATmega8A [DATASHEET] 240 8159E–AVR–02/2013 Figure 28-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) Figure 28-11. Idle Supply Current vs. VCC (Internal RC Oscillator, 4MHz) 85 °C 25 °C -40 °C 1 1.5 2 2.5 3 3.5 4 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85 °C 25 °C -40 °C 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA)ATmega8A [DATASHEET] 241 8159E–AVR–02/2013 Figure 28-12. Idle Supply Current vs. VCC (Internal RC Oscillator, 2MHz) Figure 28-13. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85 °C 25 °C -40 °C 0 0.1 0.2 0.3 0.4 0.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA)ATmega8A [DATASHEET] 242 8159E–AVR–02/2013 Figure 28-14. Idle Supply Current vs. VCC (32kHz External Oscillator) 28.3 Power-down Supply Current Figure 28-15. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 25 °C 0 5 10 15 20 25 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA)ATmega8A [DATASHEET] 243 8159E–AVR–02/2013 Figure 28-16. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 28.4 Power-save Supply Current Figure 28-17. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 85 °C 25 °C -40 °C 0 5 10 15 20 25 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 25 °C 2 4 6 8 10 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA)ATmega8A [DATASHEET] 244 8159E–AVR–02/2013 28.5 Standby Supply Current Figure 28-18. Standby Supply Current vs. VCC (455kHz Resonator, Watchdog Timer Disabled) Figure 28-19. Standby Supply Current vs. VCC (1MHz Resonator, Watchdog Timer Disabled) 25 °C 0 10 20 30 40 50 60 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 25 °C 0 10 20 30 40 50 60 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA)ATmega8A [DATASHEET] 245 8159E–AVR–02/2013 Figure 28-20. Standby Supply Current vs. VCC (1MHz Xtal, Watchdog Timer Disabled) Figure 28-21. Standby Supply Current vs. VCC (4MHz Resonator, Watchdog Timer Disabled) 25 °C 0 10 20 30 40 50 60 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 25 °C 0 15 30 45 60 75 90 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA)ATmega8A [DATASHEET] 246 8159E–AVR–02/2013 Figure 28-22. Standby Supply Current vs. VCC (4MHz Xtal, Watchdog Timer Disabled) Figure 28-23. Standby Supply Current vs. VCC (6MHz Resonator, Watchdog Timer Disabled) 25 °C 0 10 20 30 40 50 60 70 80 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 25 °C 0 20 40 60 80 100 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA)ATmega8A [DATASHEET] 247 8159E–AVR–02/2013 Figure 28-24. Standby Supply Current vs. VCC (6MHz Xtal, Watchdog Timer Disabled) 28.6 Pin Pull-up Figure 28-25. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 25 °C 0 20 40 60 80 100 120 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 0 20 40 60 80 100 120 140 0123456 VOP (V) IOP (uA) 85 °C 25 °C -40 °CATmega8A [DATASHEET] 248 8159E–AVR–02/2013 Figure 28-26. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) Figure 28-27. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 85 °C 25 °C -40 °C 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 VOP (V) IOP (uA) 85 °C 25 °C -40 °C 0 20 40 60 80 100 120 012345 VRESET (V) IRESET (uA)ATmega8A [DATASHEET] 249 8159E–AVR–02/2013 Figure 28-28. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 28.7 Pin Driver Strength Figure 28-29. I/O Pin Output Voltage vs. Source Current (VCC = 5.0V) 85 °C 25 °C -40 °C 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 VRESET (V) IRESET (uA) 85 °C 25 °C -40 °C 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 0246 8 10 12 14 16 18 20 IOH (mA) VOH ( V)ATmega8A [DATASHEET] 250 8159E–AVR–02/2013 Figure 28-30. I/O Pin Output Voltage vs. Source Current (VCC = 3.0V) Figure 28-31. I/O Pin Output Voltage vs. Sink Current (VCC = 5.0V) 85 °C 25 °C -40 °C 1 1.5 2 2.5 3 3.5 0 4 8 12 16 20 IOH (mA) VOH ( V) 85 °C 25 °C -40 °C 0 0.1 0.2 0.3 0.4 0.5 0.6 0 4 8 12 16 20 IOL (mA) VOL ( V)ATmega8A [DATASHEET] 251 8159E–AVR–02/2013 Figure 28-32. I/O Pin Output Voltage vs. Sink Current (VCC = 3.0V) Figure 28-33. Reset Pin as I/O - Pin Source Current vs. Output Voltage (VCC = 5.0V) 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 0246 8 10 12 14 16 18 20 IOL (mA) VOL ( V) 0 1 2 3 4 5 2 2.5 3 3.5 4 4.5 VOH (V) Current (mA) 85 °C 25 °C -40 °CATmega8A [DATASHEET] 252 8159E–AVR–02/2013 Figure 28-34. Reset Pin as I/O - Pin Source Current vs. Output Voltage (VCC = 2.7V) Figure 28-35. Reset Pin as I/O - Pin Sink Current vs. Output Voltage (VCC = 5.0V) 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 VOH (V) Current (mA) 85 °C 25 °C -40 °C 85 °C 25 °C -40 °C 0 2 4 6 8 10 12 14 0 0.5 1 1.5 2 VOL (V) Current (mA)ATmega8A [DATASHEET] 253 8159E–AVR–02/2013 Figure 28-36. Reset Pin as I/O - Pin Sink Current vs. Output Voltage (VCC = 2.7V) 28.8 Pin Thresholds and Hysteresis Figure 28-37. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 0.5 1 1.5 2 VOL (V) Current (mA) 85 °C 25 °C -40 °C 1 1.5 2 2.5 3 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold ( V)ATmega8A [DATASHEET] 254 8159E–AVR–02/2013 Figure 28-38. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) Figure 28-39. I/O Pin Input Hysteresis vs. VCC 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold ( V) 85 °C 25 °C -40 °C 0.2 0.25 0.3 0.35 0.4 0.45 0.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Input Hysteresis (m V)ATmega8A [DATASHEET] 255 8159E–AVR–02/2013 Figure 28-40. Reset Pin as I/O - Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”) Figure 28-41. Reset Pin as I/O - Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”) 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold ( V) 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold ( V)ATmega8A [DATASHEET] 256 8159E–AVR–02/2013 Figure 28-42. Reset Pin as I/O - Pin Hysteresis vs. VCC Figure 28-43. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”) 85 °C 25 °C -40 °C 0 0.1 0.2 0.3 0.4 0.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Input Hysteresis (m V) 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold ( V)ATmega8A [DATASHEET] 257 8159E–AVR–02/2013 Figure 28-44. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”) Figure 28-45. Reset Input Pin Hysteresis vs. VCC 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold ( V) 85 °C 25 °C -40 °C 0 0.1 0.2 0.3 0.4 0.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Input Hysteresis (m V)ATmega8A [DATASHEET] 258 8159E–AVR–02/2013 28.9 Bod Thresholds and Analog Comparator Offset Figure 28-46. BOD Thresholds vs. Temperature (BOD Level is 4.0V) Figure 28-47. BOD Thresholds vs. Temperature (BOD Level is 2.7v) 3.7 3.75 3.8 3.85 3.9 3.95 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Threshold ( V) Rising Vcc Falling Vcc Temperature (°C) 2.5 2.55 2.6 2.65 2.7 2.75 2.8 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Threshold ( V) Rising Vcc Falling VccATmega8A [DATASHEET] 259 8159E–AVR–02/2013 Figure 28-48. Bandgap Voltage vs. VCC Figure 28-49. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) 85 °C 25 °C -40 °C 1.18 1.185 1.19 1.195 1.2 1.205 1.21 1.215 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Bandgap Voltage ( V) Comparator Offset Voltage (V) 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) 85 °C 25 °C -40 °C -0.004 -0.003 -0.002 -0.001 0 0.001 0.002 0.003ATmega8A [DATASHEET] 260 8159E–AVR–02/2013 Figure 28-50. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.8V) 28.10 Internal Oscillator Speed Figure 28-51. Watchdog Oscillator Frequency vs. VCC -0.004 -0.003 -0.002 -0.001 0 0.001 0.002 0.003 0.25 0.50 0.75 1.00 1.25 1.5 1.75 2.00 2.25 2.75 Common Mode Voltage (V) 2.50 Comparator Offset Voltage (V) 85 °C 25 °C -40 °C 85 °C 25 °C -40 °C 925 950 975 1000 1025 1050 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (kHz)ATmega8A [DATASHEET] 261 8159E–AVR–02/2013 Figure 28-52. Calibrated 8MHz RC Oscillator Frequency vs. Temperature Figure 28-53. Calibrated 8MHz RC Oscillator Frequency vs. VCC 5.5 V 4.0 V 2.7 V 6 6,5 7 7,5 8 8,5 -40 -20 0 20 40 60 80 100 Temperature (°C) FRC (MHz) 85 °C 25 °C -40 °C 6 6.5 7 7.5 8 8.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz)ATmega8A [DATASHEET] 262 8159E–AVR–02/2013 Figure 28-54. Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value Figure 28-55. Calibrated 4MHz RC Oscillator Frequency vs. Temperature 25 °C 2 4 6 8 10 12 14 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE FRC (MHz) 5.5 V 4.0 V 2.7 V 3.5 3.6 3.7 3.8 3.9 4 4.1 -40 -20 0 20 40 60 80 100 FRC (MHz) Temperature (°C)ATmega8A [DATASHEET] 263 8159E–AVR–02/2013 Figure 28-56. Calibrated 4MHz RC Oscillator Frequency vs. VCC Figure 28-57. Calibrated 4MHz RC Oscillator Frequency vs. Osccal Value 85 °C 25 °C -40 °C 3.5 3.6 3.7 3.8 3.9 4 4.1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz) 25 °C 1 2 3 4 5 6 7 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE FRC (MHz)ATmega8A [DATASHEET] 264 8159E–AVR–02/2013 Figure 28-58. Calibrated 2MHz RC Oscillator Frequency vs. Temperature Figure 28-59. Calibrated 2MHz RC Oscillator Frequency vs. VCC 5.5 V 4.0 V 2.7 V 1.75 1.8 1.85 1.9 1.95 2 2.05 2.1 -40 -20 0 20 40 60 80 100 FRC (MHz) Temperature (°C) 85 °C 25 °C -40 °C 1.8 1.85 1.9 1.95 2 2.05 2.1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz)ATmega8A [DATASHEET] 265 8159E–AVR–02/2013 Figure 28-60. Calibrated 2MHz RC Oscillator Frequency vs. Osccal Value Figure 28-61. Calibrated 1MHz RC Oscillator Frequency vs. Temperature 25 °C 0.5 1 1.5 2 2.5 3 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE FRC (MHz) 5.5 V 4.0 V 2.7 V 0.9 0.92 0.94 0.96 0.98 1 1.02 1.04 -40 -20 0 20 40 60 80 100 FRC (MHz) Temperature (°C)ATmega8A [DATASHEET] 266 8159E–AVR–02/2013 Figure 28-62. Calibrated 1MHz RC Oscillator Frequency vs. VCC Figure 28-63. Calibrated 1MHz RC Oscillator Frequency vs. Osccal Value 85 °C 25 °C -40 °C 0,9 0.92 0.94 0.96 0.98 1 1.02 1.04 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz) 25 °C 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE FRC (MHz)ATmega8A [DATASHEET] 267 8159E–AVR–02/2013 28.11 Current Consumption of Peripheral Units Figure 28-64. Brown-out Detector Current vs. VCC Figure 28-65. ADC Current vs. VCC (AREF = AVCC) 85 °C 25 °C -40 °C 0 4 8 12 16 20 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 85 °C 25 °C -40 °C 100 125 150 175 200 225 250 275 300 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA)ATmega8A [DATASHEET] 268 8159E–AVR–02/2013 Figure 28-66. AREF External Reference Current vs. VCC Figure 28-67. 32kHz TOSC Current vs. VCC (Watchdog Timer Disabled) 85 °C 25 °C -40 °C 40 60 80 100 120 140 160 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 85 °C 25 °C -40 °C 0 2 4 6 8 10 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA)ATmega8A [DATASHEET] 269 8159E–AVR–02/2013 Figure 28-68. Watchdog Timer Current vs. VCC Figure 28-69. Analog Comparator Current vs. VCC 85 °C 25 °C -40 °C 0 4 8 12 16 20 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 85 °C 25 °C -40 °C 0 10 20 30 40 50 60 70 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA)ATmega8A [DATASHEET] 270 8159E–AVR–02/2013 Figure 28-70. Programming Current vs. VCC 28.12 Current Consumption in Reset and Reset Pulsewidth Figure 28-71. Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) 85 °C 25 °C -40 °C 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 2.7 V 0 0.5 1 1.5 2 2.5 3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA)ATmega8A [DATASHEET] 271 8159E–AVR–02/2013 Figure 28-72. Reset Supply Current vs. VCC (1 - 16MHz, Excluding Current Through The Reset Pull-up) Figure 28-73. Reset Pulse Width vs. VCC 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 2.7 V 0 2 4 6 8 10 12 0246 8 10 12 14 16 Frequency (MHz) ICC (mA) 85 °C 25 °C -40 °C 0 150 300 450 600 750 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Pulsewidth (ns)ATmega8A [DATASHEET] 272 8159E–AVR–02/2013 29. Typical Characteristics – TA = -40°C to 105°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and thus, the corresponding I/O modules are turned off. Also the Analog Comparator is disabled during these measurements. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 29.1 ATmega8A Typical Characteristics 29.1.1 Active Supply Current Figure 29-1. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 105 °C 85 °C 25 °C -40 °C 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (mA)ATmega8A [DATASHEET] 273 8159E–AVR–02/2013 Figure 29-2. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) Figure 29-3. Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) 105 °C 85 °C 25 °C -40 °C 1.5 2 2.5 3 3.5 4 4.5 5 5.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (mA) 105 °C 85 °C 25 °C -40 °C 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (mA)ATmega8A [DATASHEET] 274 8159E–AVR–02/2013 Figure 29-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) Figure 29-5. Active Supply Current vs. VCC (32 kHz External Oscillator) 105 °C 85 °C 25 °C -40 °C 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (mA) 105 °C 85 °C 25 °C -40 °C 35 38 41 44 47 50 53 56 59 62 65 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (uA)ATmega8A [DATASHEET] 275 8159E–AVR–02/2013 29.1.2 Idle Supply Current Figure 29-6. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) Figure 29-7. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) 105 °C 85 °C 25 °C -40 °C 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 3.9 4.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (mA) 105 °C 85 °C 25 °C -40 °C 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (mA)ATmega8A [DATASHEET] 276 8159E–AVR–02/2013 Figure 29-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) Figure 29-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 105 °C 85 °C 25 °C -40 °C 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (mA) 105 °C 85 °C 25 °C -40 °C 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (mA)ATmega8A [DATASHEET] 277 8159E–AVR–02/2013 Figure 29-10. Idle Supply Current vs. VCC (32 kHz External RC Oscillator) 29.1.3 Power-down Supply Current Figure 29-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 105 °C 85 °C 25 °C -40 °C 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (uA) 105 °C 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (uA)ATmega8A [DATASHEET] 278 8159E–AVR–02/2013 Figure 29-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 29.1.4 Power-save Supply Current Figure 29-13. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 105 °C 85 °C 25 °C -40 °C 3 6 9 12 15 18 21 24 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (uA) 105 °C 85 °C 25 °C -40 °C 4 5 6 7 8 9 10 11 12 13 14 15 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (uA)ATmega8A [DATASHEET] 279 8159E–AVR–02/2013 29.1.5 Standby Supply Current Figure 29-14. Standby Supply Current vs. VCC (32 kHz External RC Oscillator) 29.1.6 Pin Pull-up Figure 29-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 105 °C 85 °C 25 °C -40 °C 7 9 11 13 15 17 19 21 23 25 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (uA) 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) IOP (uA) 105 °C 85 °C 25 °C -40 °CATmega8A [DATASHEET] 280 8159E–AVR–02/2013 Figure 29-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) Figure 29-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 105 °C 85 °C 25 °C -40 °C 0 10 20 30 40 50 60 70 80 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VOP (V) IOP (uA) 0 10 20 30 40 50 60 70 80 90 100 110 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) IRESET (uA) 105 °C 85 °C 25 °C -40 °CATmega8A [DATASHEET] 281 8159E–AVR–02/2013 Figure 29-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 29.1.7 Pin Driver Strength Figure 29-19. I/O Pin Output Voltage vs. Source Current (VCC = 5V) 105 °C 85 °C 25 °C -40 °C 0 10 20 30 40 50 60 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRESET (V) IRESET (uA) 105 °C 85 °C 25 °C -40 °C 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 5.1 0246 8 10 12 14 16 18 20 IOH (mA) VOH ( V)ATmega8A [DATASHEET] 282 8159E–AVR–02/2013 Figure 29-20. I/O Pin Output Voltage vs. Source Current (VCC = 3V) Figure 29-21. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 0246 8 10 12 14 16 18 20 IOH (mA) VOH ( V) 105 °C 85 °C 25 °C -40 °C 105 °C 85 °C 25 °C -40 °C 0 0.1 0.2 0.3 0.4 0.5 0.6 0246 8 10 12 14 16 18 20 IOL (mA) VOL ( V)ATmega8A [DATASHEET] 283 8159E–AVR–02/2013 Figure 29-22. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) 29.1.8 Pin Threshold and Hysteresis Figure 29-23. I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) 105 °C 85 °C 25 °C -40 °C 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0246 8 10 12 14 16 18 20 IOL(mA) VOL ( V) 105 °C 85 °C 25 °C -40 °C 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Threshold ( V)ATmega8A [DATASHEET] 284 8159E–AVR–02/2013 Figure 29-24. I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’) Figure 29-25. I/O Pin Input Hysteresis vs. VCC 105 °C 85 °C 25 °C -40 °C 1 1.3 1.6 1.9 2.2 2.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Threshold ( V) 105 °C 85 °C 25 °C -40 °C 0.25 0.3 0.35 0.4 0.45 0.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Input Hysteresis (m V)ATmega8A [DATASHEET] 285 8159E–AVR–02/2013 Figure 29-26. Reset Pin as I/O - Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) Figure 29-27. Reset Pin as I/O - Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’) 105 °C 85 °C 25 °C -40 °C 1.3 1.6 1.9 2.2 2.5 2.8 3.1 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Threshold ( V) 105 °C 85 °C 25 °C -40 °C 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Threshold ( V)ATmega8A [DATASHEET] 286 8159E–AVR–02/2013 Figure 29-28. Reset Pin as I/O - Pin Hysteresis vs. VCC Figure 29-29. Reset Input Threshold vs. VCC (VIH , Reset Pin Read as ‘1’) 105 °C 85 °C 25 °C -40 °C 0.4 0.45 0.5 0.55 0.6 0.65 0.7 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Input Hysteresis (m V) 105 °C 85 °C 25 °C -40 °C 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Threshold ( V)ATmega8A [DATASHEET] 287 8159E–AVR–02/2013 Figure 29-30. Reset Input Threshold vs. VCC (VIL, Reset Pin Read as ‘0’) Figure 29-31. Reset Pin Input Hysteresis vs. VCC 105 °C 85 °C 25 °C -40 °C 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Threshold ( V) 105 °C 85 °C 25 °C -40 °C 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Input Hysteresis (m V)ATmega8A [DATASHEET] 288 8159E–AVR–02/2013 29.1.9 BOD Threshold Figure 29-32. BOD Threshold vs. Temperature (VCC = 4.3V) Figure 29-33. BOD Threshold vs. Temperature (VCC = 2.7V) Rising Vcc Falling Vcc 3.8 3.82 3.84 3.86 3.88 3.9 3.92 3.94 3.96 3.98 4 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Threshold ( V) Rising Vcc Falling Vcc 2.47 2.49 2.51 2.53 2.55 2.57 2.59 2.61 2.63 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Threshold ( V)ATmega8A [DATASHEET] 289 8159E–AVR–02/2013 Figure 29-34. Bandgap Voltage vs. Temperature Figure 29-35. Bandgap Voltage vs. VCC 5.5V 5.0V 4.0V 3.3V 2.7V 1.8V 1.175 1.18 1.185 1.19 1.195 1.2 1.205 1.21 1.215 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Bandgap Voltage ( V) 105 °C 85 °C 25 °C -40 °C 1.175 1.18 1.185 1.19 1.195 1.2 1.205 1.21 1.215 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Bandgap Voltage ( V)ATmega8A [DATASHEET] 290 8159E–AVR–02/2013 29.1.10 Internal Oscillator Speed Figure 29-36. Watchdog Oscillator Frequency vs. VCC Figure 29-37. Watchdog Oscillator Frequency vs. Temperature 105 °C 85 °C 25 °C -40 °C 980 1000 1020 1040 1060 1080 1100 1120 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) FRC (kHz) 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 2.7 V 970 990 1010 1030 1050 1070 1090 1110 1130 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) FRC (kHz)ATmega8A [DATASHEET] 291 8159E–AVR–02/2013 Figure 29-38. Calibrated 8 MHz RC Oscillator vs. Temperature Figure 29-39. Calibrated 8 MHz RC Oscillator vs. VCC 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.0 V 2.7 V 6.6 6.8 7 7.2 7.4 7.6 7.8 8 8.2 8.4 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) FRC (MHz) 105 °C 85 °C 25 °C -40 °C 6.6 6.8 7 7.2 7.4 7.6 7.8 8 8.2 8.4 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) FRC (MHz)ATmega8A [DATASHEET] 292 8159E–AVR–02/2013 Figure 29-40. Calibrated 8 MHz RC Oscillator vs. OSCCAL Value Figure 29-41. Calibrated 4 MHz RC Oscillator vs. Temperature 105 °C 85 °C 25 °C -40 °C 2 4 6 8 10 12 14 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) FRC (MHz) 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.0 V 2.7 V 3.55 3.65 3.75 3.85 3.95 4.05 4.15 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) FRC (MHz)ATmega8A [DATASHEET] 293 8159E–AVR–02/2013 Figure 29-42. Calibrated 4 MHz RC Oscillator vs. VCC Figure 29-43. Calibrated 4 MHz RC Oscillator vs. OSCCAL Value 105 °C 85 °C 25 °C -40 °C 3.6 3.65 3.7 3.75 3.8 3.85 3.9 3.95 4 4.05 4.1 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) FRC (MHz) 105 °C 85 °C 25 °C -40 °C 1 2 3 4 5 6 7 8 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) FRC (MHz)ATmega8A [DATASHEET] 294 8159E–AVR–02/2013 Figure 29-44. Calibrated 2 MHz RC Oscillator vs. Temperature Figure 29-45. Calibrated 2 MHz RC Oscillator vs. VCC 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.0 V 2.7 V 1.78 1.81 1.84 1.87 1.9 1.93 1.96 1.99 2.02 2.05 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) FRC (MHz) 105 °C 85 °C 25 °C -40 °C 1.8 1.83 1.86 1.89 1.92 1.95 1.98 2.01 2.04 2.07 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) FRC (MHz)ATmega8A [DATASHEET] 295 8159E–AVR–02/2013 Figure 29-46. Calibrated 2 MHz RC Oscillator vs. OSCCAL Value Figure 29-47. Calibrated 1 MHz RC Oscillator vs. Temperature 105 °C 85 °C 25 °C -40 °C 0.8 1.1 1.4 1.7 2 2.3 2.6 2.9 3.2 3.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) FRC (MHz) 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.0 V 2.7 V 0.91 0.93 0.95 0.97 0.99 1.01 1.03 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) FRC (MHz)ATmega8A [DATASHEET] 296 8159E–AVR–02/2013 Figure 29-48. Calibrated 1 MHz RC Oscillator vs. VCC Figure 29-49. Calibrated 1 MHz RC Oscillator vs. OSCCAL Value 105 °C 85 °C 25 °C -40 °C 0.9 0.92 0.94 0.96 0.98 1 1.02 1.04 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) FRC (MHz) 105 °C 85 °C 25 °C -40 °C 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) FRC (MHz)ATmega8A [DATASHEET] 297 8159E–AVR–02/2013 29.1.11 Current Consumption of Peripheral Units Figure 29-50. Brown-out Detector Current vs. VCC Figure 29-51. ADC Current vs. VCC (AREF = AVCC) 105 °C 85 °C 25 °C -40 °C 8 9 10 11 12 13 14 15 16 17 18 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (uA) 105 °C 85 °C 25 °C -40 °C 140 160 180 200 220 240 260 280 300 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (uA)ATmega8A [DATASHEET] 298 8159E–AVR–02/2013 Figure 29-52. Watchdog Timer Current vs. VCC Figure 29-53. Analog Comparator Current vs. VCC 4 6 8 10 12 14 16 18 20 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (uA) 105 °C 85 °C 25 °C -40 °C 32 36 40 44 48 52 56 60 64 68 72 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (mA) 105 °C 85 °C 25 °C -40 °CATmega8A [DATASHEET] 299 8159E–AVR–02/2013 Figure 29-54. Programming Current vs. VCC 29.1.12 Current Consumption in Reset and Reset Pulsewidth Figure 29-55. Reset Supply Current vs. Vcc (0.1 - 1.0 MHz, Excluding Current Through the Reset Pull-up) 105 °C 85 °C 25 °C -40 °C 0 1 2 3 4 5 6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) ICC (mA) 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 2.7 V 0 0.5 1 1.5 2 2.5 3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA)ATmega8A [DATASHEET] 300 8159E–AVR–02/2013 Figure 29-56. Reset Supply Current vs. Vcc (1 - 16 MHz, Excluding Current Through the Reset Pull-up) Figure 29-57. Minimum Reset Pulsewidth vs. Vcc 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 2.7 V 0 2 4 6 8 10 12 0246 8 10 12 14 16 Frequency (MHz) ICC (mA) 105 °C 85 °C 25 °C -40 °C 100 200 300 400 500 600 700 800 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 VCC (V) Pulse width (ns)ATmega8A [DATASHEET] 301 8159E–AVR–02/2013 30. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F (0x5F) SREG I T H S V N Z C 8 0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 10 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 10 0x3C (0x5C) Reserved 0x3B (0x5B) GICR INT1 INT0 – – – – IVSEL IVCE 47, 65 0x3A (0x5A) GIFR INTF1 INTF0 – – – – – – 65 0x39 (0x59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 69, 97, 115 0x38 (0x58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 70, 97, 97 0x37 (0x57) SPMCR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 205 0x36 (0x56) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 176 0x35 (0x55) MCUCR SE SM2 SM1 SM0 ISC11 ISC10 ISC01 ISC00 35, 64 0x34 (0x54) MCUCSR – – – – WDRF BORF EXTRF PORF 42 0x33 (0x53) TCCR0 – – – – – CS02 CS01 CS00 69 0x32 (0x52) TCNT0 Timer/Counter0 (8 Bits) 69 0x31 (0x51) OSCCAL Oscillator Calibration Register 31 0x30 (0x50) SFIOR – – – – ACME PUD PSR2 PSR10 55, 72, 115, 180 0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 92 0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 95 0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High byte 96 0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low byte 96 0x2B (0x4B) OCR1AH Timer/Counter1 – Output Compare Register A High byte 96 0x2A (0x4A) OCR1AL Timer/Counter1 – Output Compare Register A Low byte 96 0x29 (0x49) OCR1BH Timer/Counter1 – Output Compare Register B High byte 96 0x28 (0x48) OCR1BL Timer/Counter1 – Output Compare Register B Low byte 96 0x27 (0x47) ICR1H Timer/Counter1 – Input Capture Register High byte 96 0x26 (0x46) ICR1L Timer/Counter1 – Input Capture Register Low byte 96 0x25 (0x45) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 112 0x24 (0x44) TCNT2 Timer/Counter2 (8 Bits) 113 0x23 (0x43) OCR2 Timer/Counter2 Output Compare Register 114 0x22 (0x42) ASSR – – – – AS2 TCN2UB OCR2UB TCR2UB 114 0x21 (0x41) WDTCR – – – WDCE WDE WDP2 WDP1 WDP0 42 0x20(1) (0x40)(1) UBRRH URSEL – – – UBRR[11:8] 147 UCSRC URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 145 0x1F (0x3F) EEARH – – – – – – – EEAR8 18 0x1E (0x3E) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 18 0x1D (0x3D) EEDR EEPROM Data Register 18 0x1C (0x3C) EECR – – – – EERIE EEMWE EEWE EERE 18 0x1B (0x3B) Reserved 0x1A (0x3A) Reserved 0x19 (0x39) Reserved 0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 62 0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 62 0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 63 0x15 (0x35) PORTC – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 63 0x14 (0x34) DDRC – DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 63 0x13 (0x33) PINC – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 63 0x12 (0x32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 63 0x11 (0x31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 63 0x10 (0x30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 63 0x0F (0x2F) SPDR SPI Data Register 124 0x0E (0x2E) SPSR SPIF WCOL – – – – – SPI2X 124 0x0D (0x2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 123 0x0C (0x2C) UDR USART I/O Data Register 143 0x0B (0x2B) UCSRA RXC TXC UDRE FE DOR PE U2X MPCM 144 0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 145 0x09 (0x29) UBRRL USART Baud Rate Register Low byte 147 0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 180 0x07 (0x27) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 190 0x06 (0x26) ADCSRA ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 191 0x05 (0x25) ADCH ADC Data Register High byte 193 0x04 (0x24) ADCL ADC Data Register Low byte 193 0x03 (0x23) TWDR Two-wire Serial Interface Data Register 178 0x02 (0x22) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 178 0x01 (0x21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 177 0x00 (0x20) TWBR Two-wire Serial Interface Bit Rate Register 176ATmega8A [DATASHEET] 302 8159E–AVR–02/2013 Note: 1. Refer to the USART description for details on how to access UBRRH and UCSRC. 2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.ATmega8A [DATASHEET] 303 8159E–AVR–02/2013 31. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd  Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd  Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl  Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd  Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd  Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd  Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd  Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl  Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd Rd  Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd  Rd K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd  Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd  Rd  Rr Z,N,V 1 COM Rd One’s Complement Rd  0xFF  Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd  0x00  Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd  Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd  Rd  (0xFF - K) Z,N,V 1 INC Rd Increment Rd  Rd + 1 Z,N,V 1 DEC Rd Decrement Rd  Rd  1 Z,N,V 1 TST Rd Test for Zero or Minus Rd  Rd  Rd Z,N,V 1 CLR Rd Clear Register Rd  Rd  Rd Z,N,V 1 SER Rd Set Register Rd  0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0  Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0  Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0  Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0  (Rd x Rr) << 1 Z,C 2 FMULS Rd, Rr Fractional Multiply Signed R1:R0  (Rd x Rr) << 1 Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0  (Rd x Rr) << 1 Z,C 2 BRANCH INSTRUCTIONS RJMP k Relative Jump PC PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC  Z None 2 RCALL k Relative Subroutine Call PC  PC + k + 1 None 3 ICALL Indirect Call to (Z) PC  Z None 3 RET Subroutine Return PC  STACK None 4 RETI Interrupt Return PC  STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1 / 2 / 3 CP Rd,Rr Compare Rd  Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd  Rr  C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd  K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC  PC + 2 or 3 None 1 / 2 / 3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC  PC + 2 or 3 None 1 / 2 / 3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC  PC + 2 or 3 None 1 / 2 / 3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC  PC + 2 or 3 None 1 / 2 / 3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1 / 2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1 / 2 BREQ k Branch if Equal if (Z = 1) then PC  PC + k + 1 None 1 / 2 BRNE k Branch if Not Equal if (Z = 0) then PC  PC + k + 1 None 1 / 2 BRCS k Branch if Carry Set if (C = 1) then PC  PC + k + 1 None 1 / 2 BRCC k Branch if Carry Cleared if (C = 0) then PC  PC + k + 1 None 1 / 2 BRSH k Branch if Same or Higher if (C = 0) then PC  PC + k + 1 None 1 / 2 BRLO k Branch if Lower if (C = 1) then PC  PC + k + 1 None 1 / 2 BRMI k Branch if Minus if (N = 1) then PC  PC + k + 1 None 1 / 2 BRPL k Branch if Plus if (N = 0) then PC  PC + k + 1 None 1 / 2 BRGE k Branch if Greater or Equal, Signed if (N  V= 0) then PC  PC + k + 1 None 1 / 2 BRLT k Branch if Less Than Zero, Signed if (N  V= 1) then PC  PC + k + 1 None 1 / 2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC  PC + k + 1 None 1 / 2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC  PC + k + 1 None 1 / 2 BRTS k Branch if T Flag Set if (T = 1) then PC  PC + k + 1 None 1 / 2 BRTC k Branch if T Flag Cleared if (T = 0) then PC  PC + k + 1 None 1 / 2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC  PC + k + 1 None 1 / 2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC  PC + k + 1 None 1 / 2 Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC  PC + k + 1 None 1 / 2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC  PC + k + 1 None 1 / 2ATmega8A [DATASHEET] 304 8159E–AVR–02/2013 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd  Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd  Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd  K None 1 LD Rd, X Load Indirect Rd  (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd  (X), X  X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X  X - 1, Rd  (X) None 2 LD Rd, Y Load Indirect Rd  (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd  (Y), Y  Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y  Y - 1, Rd  (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd  (Y + q) None 2 LD Rd, Z Load Indirect Rd  (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd  (Z), Z  Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z  Z - 1, Rd  (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd  (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd  (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X  X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X  X - 1, (X)  Rr None 2 ST Y, Rr Store Indirect (Y)  Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y)  Rr, Y  Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y  Y - 1, (Y)  Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q)  Rr None 2 ST Z, Rr Store Indirect (Z)  Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z)  Rr, Z  Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z  Z - 1, (Z)  Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q)  Rr None 2 STS k, Rr Store Direct to SRAM (k)  Rr None 2 LPM Load Program Memory R0  (Z) None 3 LPM Rd, Z Load Program Memory Rd  (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd  (Z), Z  Z+1 None 3 SPM Store Program Memory (Z)  R1:R0 None - IN Rd, P In Port Rd  P None 1 OUT P, Rr Out Port P  Rr None 1 PUSH Rr Push Register on Stack STACK  Rr None 2 POP Rd Pop Register from Stack Rd  STACK None 2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b)  1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b)  0 None 2 LSL Rd Logical Shift Left Rd(n+1)  Rd(n), Rd(0)  0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n)  Rd(n+1), Rd(7)  0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n)  Rd(n+1), n=0:6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3:0)Rd(7:4),Rd(7:4)Rd(3:0) None 1 BSET s Flag Set SREG(s)  1 SREG(s) 1 BCLR s Flag Clear SREG(s)  0 SREG(s) 1 BST Rr, b Bit Store from Register to T T  Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b)  T None 1 SEC Set Carry C  1 C1 CLC Clear Carry C  0 C 1 SEN Set Negative Flag N  1 N1 CLN Clear Negative Flag N  0 N 1 SEZ Set Zero Flag Z  1 Z1 CLZ Clear Zero Flag Z  0 Z 1 SEI Global Interrupt Enable I  1 I1 CLI Global Interrupt Disable I 0 I 1 SES Set Signed Test Flag S  1 S1 CLS Clear Signed Test Flag S  0 S 1 SEV Set Twos Complement Overflow. V  1 V1 CLV Clear Twos Complement Overflow V  0 V 1 SET Set T in SREG T  1 T1 Mnemonics Operands Description Operation Flags #Clocks CLT Clear T in SREG T  0 T 1 SEH Set Half Carry Flag in SREG H  1 H1 CLH Clear Half Carry Flag in SREG H  0 H 1 MCU CONTROL INSTRUCTIONS 31. Instruction Set Summary (Continued)ATmega8A [DATASHEET] 305 8159E–AVR–02/2013 NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 31. Instruction Set Summary (Continued)ATmega8A [DATASHEET] 306 8159E–AVR–02/2013 32. Ordering Information Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Tape & Reel 4. See characterization specifications at 105C Speed (MHz) Power Supply (V) Ordering Code(2) Package(1) Operation Range 16 2.7 - 5.5 ATmega8A-AU ATmega8A-AUR(3) ATmega8A-PU ATmega8A-MU ATmega8A-MUR(3) 32A 32A 28P3 32M1-A 32M1-A Industrial (-40C to 85C) ATmega8A-AN ATmega8A-ANR(3) ATmega8A-PN ATmega8A-MN ATmega8A-MNR(3) 32A 32A 28P3 32M1-A 32M1-A Extended (-40C to 105C)(4) Package Type 32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)ATmega8A [DATASHEET] 307 8159E–AVR–02/2013 33. Packaging Information 33.1 32A TITLE DRAWING NO. REV. 32A, 32-lead, 7 x 7mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP) 32A C 2010-10-20 PIN 1 IDENTIFIER 0°~7° PIN 1 L C A1 A2 A D1 D e E1 E B Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 8.75 9.00 9.25 D1 6.90 7.00 7.10 Note 2 E 8.75 9.00 9.25 E1 6.90 7.00 7.10 Note 2 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e 0.80 TYP COMMON DIMENSIONS (Unit of measure = mm) SYMBOL MIN NOM MAX NOTEATmega8A [DATASHEET] 308 8159E–AVR–02/2013 33.2 28P3 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 28P3, 28-lead (0.300"/7.62mm Wide) Plastic Dual Inline Package (PDIP) 28P3 B 09/28/01 PIN 1 E1 A1 B REF E B1 C L SEATING PLANE A 0º ~ 15º D e eB B2 (4 PLACES) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 4.5724 A1 0.508 – – D 34.544 – 34.798 Note 1 E 7.620 – 8.255 E1 7.112 – 7.493 Note 1 B 0.381 – 0.533 B1 1.143 – 1.397 B2 0.762 – 1.143 L 3.175 – 3.429 C 0.203 – 0.356 eB – – 10.160 e