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Farnell PDF
STK600 Expansion, Routing and Socket Boards - Atmel - Farnell Element 14
STK600 Expansion, Routing and Socket Boards - Atmel - Farnell Element 14
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
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APPLICATION NOTE
Atmel AVR600: STK600 Expansion, Routing and Socket
Boards
Atmel Microcontrollers
Introduction
This application note describes the process of developing new routing, socket and
expansion cards for the Atmel STK®
600. It also describes the physical parameters for
creating such cards.
The STK600 starter kit from Atmel has a sandwich design to match a specific part
package and pin out to the generic pin headers. It also features an expansion area
where most part pins are available.
While the variety of IC packages is relatively limited, the number of possible pinouts
increases rapidly with the number of pins. I.e. a 6-pin IC can have 720 (6!) different
pinouts!
The routing / socket card design provides a lowcost solution to support upcoming
devices as the socket is the cost driving factor.
STK600 users might also want to create their own routing cards to include
specialized hardware to prototype their own design.
Figure 1. STK600 router and socket card.
8170C−AVR−03/2013Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
2
Table of Contents
1. Routing Cards ...................................................................................... 3
1.1 Connector footprints .......................................................................................... 3
1.2 Physical dimensions and component placement .............................................. 4
1.3 Atmel STK600 socket connectors pinout .......................................................... 5
1.3.1 Signal descriptions .............................................................................. 8
2. Socket Cards ..................................................................................... 10
2.1 Power design issues ....................................................................................... 10
2.2 Connector MPN ............................................................................................... 10
2.3 Physical dimensions and component placement ............................................ 10
3. Expansion Cards ................................................................................ 11
3.1 Connector MPN ............................................................................................... 11
3.2 Physical dimensions and component placement ............................................ 12
3.3 Atmel STK600 expansion connectors pinout .................................................. 13
4. ID System .......................................................................................... 17
4.1 Signal usage ................................................................................................... 17
4.2 ID functions ..................................................................................................... 18
4.3 Examples ........................................................................................................ 19
5. Design Example ................................................................................. 20
6. Revision History ................................................................................. 22Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
3
1. Routing Cards
The routing cards sit between the generic socket card and the Atmel STK600. It has one pair of electric pads
underneath to mate with the STK600 spring loaded connector, and one pair of pads on top where the socket card
connector connects. A part specific card with the target IC soldered on can be viewed as a routing card without the top
pads.
1.1 Connector footprints
A routing card should have pads to mate with the following spring loaded connectors:
Table 1-1. Router card connectors.
Manufacturer and MPN Quantity Comment
SAMTEC, FSI-140-03-G-D-AD 2 80-pins to socket card (top)
SAMTEC, FSI-150-03-G-D-AD 2 100-pins to STK600 (bottom)
Figure 1-1. PCB land pattern for mating to FSI connectors. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
4
1.2 Physical dimensions and component placement
Figure 1-2. Routing card connector pad placement and dimensions.
Figure 1-3. Clip hole dimensions.
The board thickness should be 1.6mm to be compatible with the clips.
Note: Components on the main board might conflict with through hole mounted or secondary side mounted components.
Areas with such components are highlighted in Figure 1-4. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
5
Figure 1-4. Height restricted areas due to main board components.
1.3 Atmel STK600 socket connectors pinout
Figure 1-5 shows the pinout for the STK600 headers. This corresponds to the routing card connectors J1 and J2.
Figure 1-5. STK600 socket connectors’ pinout. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
6
Table 1-2. Atmel STK600 J201 left, routing card connector J1 pinout.
Signal name Pin number Signal name
VTG 2 1 GND
PA1 4 3 PA0
PA3 6 5 PA2
PA5 8 7 PA4
PA7 10 9 PA6
VTG 12 11 GND
PB1 14 13 PB0
PB3 16 15 PB2
PB5 18 17 PB4
PB7 20 19 PB6
VTG 22 21 GND
PC1 24 23 PC0
PC3 26 25 PC2
PC5 28 27 PC4
PC7 30 29 PC6
VTG 32 31 GND
PD1 34 33 PD0
PD3 36 35 PD2
PD5 38 37 PD4
PD7 40 39 PD6
VTG 42 41 GND
PE1 44 43 PE0
PE3 46 45 PE2
PE5 48 47 PE4
PE7 50 49 PE6
VTG 52 51 GND
PF1 54 53 PF0
PF3 56 55 PF2
PF5 58 57 PF4
PF7 60 59 PF6
VTG 62 61 GND
PG1 64 63 PG0
PG3 66 65 PG2
PG5 68 67 PG4
PG7 70 69 PG6
VTG 72 71 GND
PH1 74 73 PH0
PH3 76 75 PH2
PH5 78 77 PH4 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
7
PH7 80 79 PH6
VTG 82 81 GND
AREF0 84 83 XTAL1
AREF1 86 85 XTAL2
TGT_MOSI 88 87 GND
TGT_MISO 90 89 TOSC1
TGT_SCK 92 91 TOSC2
TDI 94 93 TGT_RESET
TDO 96 95 GND
TMS 98 97 Vext
TCK 100 99 Vcc
Table 1-3. Atmel STK600 J202 right, routing card connector J2 pinout.
Signal name Pin number Signal name
VTG 2 1 GND
PJ1 4 3 PJ0
PJ3 6 5 PJ2
PJ5 8 7 PJ4
PJ7 10 9 PJ6
VTG 12 11 GND
PK1 14 13 PK0
PK3 16 15 PK2
PK5 18 17 PK4
PK7 20 19 PK6
VTG 22 21 GND
PL1 24 23 PL0
PL3 26 25 PL2
PL5 28 27 PL4
PL7 30 29 PL6
VTG 32 31 GND
PM1 34 33 PM0
PM3 36 35 PM2
PM5 38 37 PM4
PM7 40 39 PM6
VTG 42 41 GND
PN1 44 43 PN0
PN3 46 45 PN2
PN5 48 47 PN4
PN7 50 49 PN6
VTG 52 51 GND
PP1 54 53 PP0 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
8
PP3 56 55 PP2
PP5 58 57 PP4
PP7 60 59 PP6
VTG 62 61 GND
PQ1 64 63 PQ0
PQ3 66 65 PQ2
PQ5 68 67 PQ4
PQ7 70 69 PQ6
VBUST 72 71 DP
UVCON 74 73 DN
Vcc 76 75 UID
Vext 78 77 GND
TGT_PDATA1 80 79 TGT_PDATA0
TGT_PDATA3 82 81 TGT_PDATA2
TGT_PDATA5 84 83 TGT_PDATA4
TGT_PDATA7 86 85 TGT_PDATA6
TGT_PCTRL1 88 87 TGT_PCTRL0
TGT_PCTRL3 90 89 TGT_PCTRL2
TGT_PCTRL5 92 91 TGT_PCTRL4
TGT_PCTRL7 94 93 TGT_PCTRL6
BOARD_ID1 96 95 BOARD_ID0
BOARD_ID3 98 97 BOARD_ID2
BOARD_ID5 100 99 BOARD_ID4
1.3.1 Signal descriptions
Table 1-4. Socket card connector pin description.
Atmel STK600 signal name MCU Comment
PAx, PBx etc PAx, PBx etc 1-to-1 MCU pin mapping
VTG Vcc Target supply rail controlled by Atmel AVR Studio®
/ STK600
GND GND
AREFx AREF Analog reference voltage, controlled by AVR Studio / STK600
XTALx XTALx Clock pins connected to oscillator on STK600
TGT_SCK, TGT_MISO, TGT_MOSI ISP pins ISP programming interface
TGT_TDI, TGT_TDO, TGT_TMS,
TGT_TCK JTAG pins JTAG programming interface
VBUST VBUS VBUS (sense) for USB
UID UID ID pin for USB OTG
UVCON UVCON
USB VBUS generation control for USB OTG. A low level on this
signal enables VBUS generation
DP, DN DP, DN USB differential pair
TGT_PDATA(0-7) (HV) data pins Data pins for high voltage (PP/HVSP) programming Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
9
TGT_CTRL0 (HV) BS2
Control signals for High voltage Parallel Programming / Serial
Programming. Refer to AVR datasheet for further information.
On AVRs with common XA1/BS2, XA1 is used.
On AVRs with common BS1/PAGEL, BS1 is used.
TGT_CTRL1 (HV) Ready/Busy
TGT_CTRL2 (HV) /OE
TGT_CTRL3 (HV) /WR
TGT_CTRL4 (HV) BS1
TGT_CTRL5 (HV) XA0
TGT_CTRL6 (HV) XA1
TGT_CTRL7 (HV) PAGEL
BOARD_IDn none
ID system for router / socket / expansion cards, see Chapter 4 -
ID System
Notes: 1. Not all AVR will have every pin (ex. two aref pins, tosc or usb).
2. A MCU pin will fan-out to both Pnx pin and to the programming interface(s) located at that pin. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
10
2. Socket Cards
Socket cards route each pin from the IC socket to separate pins on the spring loaded connectors on the bottom side,
facing the routing card.
2.1 Power design issues
As all routing is handled by the routing card, even power lines and power decoupling is ignored at the socket card. This
produces less than ideal power design, which may lead to unwanted noise, ground bounce, and other effects. It should
therefore be expected that heavily loaded designs cannot run at full speed on the Atmel STK600. Likewise, such power
design is not recommended for custom designs.
2.2 Connector MPN
Table 2-1. Socket card connector.
Manufacturer and MPN Quantity Comment
SAMTEC, FSI-140-03-G-D-AD 2 Spring loaded 80-pin connector
2.3 Physical dimensions and component placement
Figure 2-1. Socket card connector placement and dimensions.
ST1
J1 J2
45°
Note!
105mm
94mm
66mm
7mm
The board thickness should be 1.6mm to be compatible with the clips. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
11
3. Expansion Cards
The Atmel STK600 features an expansion area where cards for custom peripherals like memory expansion, LCD etc
can be placed. STK600 routes all part pins and power to the expansion card connectors.
3.1 Connector MPN
Table 3-1. Expansion card connector.
Manufacturer and MPN Quantity Comment
FCI, 61082-101402LF 2 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
12
3.2 Physical dimensions and component placement
Figure 3-1. Expansion card connector placement and dimensions.
There is no requirement to board thickness. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
13
3.3 Atmel STK600 expansion connectors pinout
Figure 3-2. Pinout for expansion connectors.
Table 3-2. STK600 J301 “expand0” connector pinout.
Signal name Pin number Signal name
VTG 2 1 GND
PA1 4 3 PA0
PA3 6 5 PA2
PA5 8 7 PA4
PA7 10 9 PA6
VTG 12 11 GND
PB1 14 13 PB0
PB3 16 15 PB2
PB5 18 17 PB4
PB7 20 19 PB6
VTG 22 21 GND
PC1 24 23 PC0
PC3 26 25 PC2
PC5 28 27 PC4
PC7 30 29 PC6
VTG 32 31 GND
PD1 34 33 PD0 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
14
PD3 36 35 PD2
PD5 38 37 PD4
PD7 40 39 PD6
VTG 42 41 GND
PE1 44 43 PE0
PE3 46 45 PE2
PE5 48 47 PE4
PE7 50 49 PE6
VTG 52 51 GND
PF1 54 53 PF0
PF3 56 55 PF2
PF5 58 57 PF4
PF7 60 59 PF6
VTG 62 61 GND
PG1 64 63 PG0
PG3 66 65 PG2
PG5 68 67 PG4
PG7 70 69 PG6
VTG 72 71 GND
PH1 74 73 PH0
PH3 76 75 PH2
PH5 78 77 PH4
PH7 80 79 PH6
VTG 82 81 GND
AREF0 84 83 XTAL1
AREF1 86 85 XTAL2
TGT_MOSI 88 87 GND
TGT_MISO 90 89 TOSC1
TGT_SCK 92 91 TOSC2
TDI 94 93 TGT_RESET
TDO 96 95 Vcc6
TMS 98 97 GND
TCK 100 99 Vcc6
Table 3-3. Atmel STK600 J302 “expand1” connector pinout.
Signal name Pin number Signal name
VTG 2 1 GND
PJ1 4 3 PJ0
PJ3 6 5 PJ2
PJ5 8 7 PJ4
PJ7 10 9 PJ6 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
15
VTG 12 11 GND
PK1 14 13 PK0
PK3 16 15 PK2
PK5 18 17 PK4
PK7 20 19 PK6
VTG 22 21 GND
PL1 24 23 PL0
PL3 26 25 PL2
PL5 28 27 PL4
PL7 30 29 PL6
VTG 32 31 GND
PM1 34 33 PM0
PM3 36 35 PM2
PM5 38 37 PM4
PM7 40 39 PM6
VTG 42 41 GND
PN1 44 43 PN0
PN3 46 45 PN2
PN5 48 47 PN4
PN7 50 49 PN6
VTG 52 51 GND
PP1 54 53 PP0
PP3 56 55 PP2
PP5 58 57 PP4
PP7 60 59 PP6
VTG 62 61 GND
PQ1 64 63 PQ0
PQ3 66 65 PQ2
PQ5 68 67 PQ4
PQ7 70 69 PQ6
Vext 72 71 GND
Vext 74 73 GND
GND 76 75 Vcc
GND 78 77 Vcc
TGT_PDATA1 80 79 TGT_PDATA0
TGT_PDATA3 82 81 TGT_PDATA2
TGT_PDATA5 84 83 TGT_PDATA4
TGT_PDATA7 86 85 TGT_PDATA6
TGT_PCTRL1 88 87 TGT_PCTRL0
TGT_PCTRL3 90 89 TGT_PCTRL2
TGT_PCTRL5 92 91 TGT_PCTRL4 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
16
TGT_PCTRL7 94 93 TGT_PCTRL6
Vcc3 96 95 GND
BOARD_ID1 98 97 BOARD_ID0
BOARD_ID7 100 99 BOARD_ID6 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
17
4. ID System
The Atmel STK600 features an ID system to identify which routing, socket and expansion card is attached. The STK600
can impose voltage limitations based on the IDs, and Atmel AVR Studio will notify the user if the combination is
incorrect.
The ID system consists of two common output and two board unique input signals. Each input is one of sixteen possible
values based in the input signals – giving a total ID space of 256.
Three IDs are reserved for custom use and can be implemented without use of ICs.
Table 4-1. IDs reserved for custom use.
Type ID
Board limited to 1.8V 0xCA
Board limited to 3.3V 0xCC
No limit on voltage 0xCF
The ID 0xff indicates no board present.
4.1 Signal usage
Table 4-2. ID system signal usage.
Name Direction Function
BOARD_ID0 Output (A) Common output to functions
BOARD_ID1 Output (B) Common output to functions
BOARD_ID2 Input Input from routing card
BOARD_ID3 Input Input from routing card
BOARD_ID4 Input Input from socket card
BOARD_ID5 Input Input from socket card
BOARD_ID6 Input Input from expansion card
BOARD_ID7 Input Input from expansion card Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
18
4.2 ID functions
The functions and their output according to input A and B:
B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Functions as logic expressions:
Function Expression ID
0 0 0x0
1 A + B 0x1
2 AB 0x2
3 B 0x3
4 AB 0x4
5 A 0x5
6 ⊕ BA 0x6
7 AB 0x7
8 AB 0x8
9 ⊕ BA 0x9
10 A 0xA
11 B + AB 0xB
12 B 0xC
13 B A⋅+ B 0xD
14 A + B 0xE
15 1 0xF Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
19
4.3 Examples
For a socket card to report the ID 0xCA:
Route BOARD_ID1 to BOARD_ID4 and BOARD_ID0 to BOARD_ID5
Figure 4-1. Socket card ID example.
For an expansion card to report the ID 0xCF:
Route BOARD_ID0 to BOARD_ID6 and VCC to BOARD_ID7
Figure 4-2. Expansion card ID example.
For a router card to report the ID 0xCC:
Route BOARD_ID1 to both BOARD_ID2 and BOARD_ID3.
Figure 4-3. Routing card ID example. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
20
5. Design Example
To support a new package type one would typically start with designing the socket card. The pinout between the socket
card and routing card is not defined and left to the designer. An example is given in Figure 5-1.
Next is the design of the routing card (Figure 5-3). The routing card’s role is to connect each pin from the socket card to
the corresponding pin on the Atmel STK600. In addition to decoupling etc, the routing card should also fan-out the
correct signals to programming headers.
Each card in the stack has its own board_id pins; the routing card is responsible for passing on the signal to the socket
card.
Figure 5-1. Schema capture of socket card.
Both the socket and routing card must also include the clip holes:
Figure 5-2. Clip holes included in schematic. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
21
Figure 5-3. Schema capture of routing card.
Copyright © 2008, Atmel Corporation Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
22
6. Revision History
Doc. Rev. Date Comments
8170C 03/2013 Example schematics for the ID system are updated
8170B 12/2010
8170A 10/2008 Initial document release
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© 2013 Atmel Corporation. All rights reserved. / Rev.: 8170C−AVR−03/2013
Atmel®, Atmel logo and combinations thereof, AVR®, AVR Studio®, Enabling Unlimited Possibilities®, STK®, and others are registered trademarks or trademarks of
Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
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automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
8159E–AVR–02/2013
Features
• High-performance, Low-power Atmel®AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 130 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments
– 8KBytes of In-System Self-programmable Flash program memory
– 512Bytes EEPROM
– 1KByte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85C/100 years at 25C(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
• Atmel QTouch® library support
– Capacitive touch buttons, sliders and wheels
– Atmel QTouch and QMatrix acquisition
– Up to 64 sense channels
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Three PWM Channels
– 8-channel ADC in TQFP and QFN/MLF package
• Eight Channels 10-bit Accuracy
– 6-channel ADC in PDIP package
• Six Channels 10-bit Accuracy
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
• I/O and Packages
– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF
• Operating Voltages
– 2.7 - 5.5V
– 0 - 16MHz
• Power Consumption at 4MHz, 3V, 25C
– Active: 3.6mA
– Idle Mode: 1.0mA
– Power-down Mode: 0.5µA
8-bit Atmel Microcontroller with 8KB In-System Programmable Flash
ATmega8AATmega8A [DATASHEET] 2
8159E–AVR–02/2013
1. Pin Configurations
Figure 1-1. Pinout ATmega8A
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
(INT1) PD3
(XCK/T0) PD4
GND
VCC
GND
VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0
(OC1A) PB1
(SS/OC1B) PB2
(MOSI/OC2) PB3
(MISO) PB4
PD2 (INT0)
PD1 (TXD)
PD0 (RXD)
PC6 (RESET)
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
TQFP Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
(RESET) PC6
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(XCK/T0) PD4
VCC
GND
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
PC1 (ADC1)
PC0 (ADC0)
GND
AREF
AVCC
PB5 (SCK)
PB4 (MISO)
PB3 (MOSI/OC2)
PB2 (SS/OC1B)
PB1 (OC1A)
PDIP
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
MLF Top View
(INT1) PD3
(XCK/T0) PD4
GND
VCC
GND
VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0
(OC1A) PB1
(SS/OC1B) PB2
(MOSI/OC2) PB3
(MISO) PB4
PD2 (INT0)
PD1 (TXD)
PD0 (RXD)
PC6 (RESET)
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
NOTE:
The large center pad underneath the MLF
packages is made of metal and internally
connected to GND. It should be soldered
or glued to the PCB to ensure good
mechanical stability. If the center pad is
left unconneted, the package might
loosen from the PCB.ATmega8A [DATASHEET] 3
8159E–AVR–02/2013
2. Overview
The Atmel®AVR® ATmega8A is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By
executing powerful instructions in a single clock cycle, the ATmega8A achieves throughputs approaching 1 MIPS
per MHz, allowing the system designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
INTERNAL
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
MCU CTRL.
& TIMING
OSCILLATOR
TIMERS/
COUNTERS
INTERRUPT
UNIT
STACK
POINTER
EEPROM
SRAM
STATUS
REGISTER
USART
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
PROGRAMMING
LOGIC SPI
ADC
INTERFACE
COMP.
INTERFACE
PORTC DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
+
-
PORTB DRIVERS/BUFFERS
PORTB DIGITAL INTERFACE
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
XTAL1
XTAL2
CONTROL
LINES
VCC
GND
MUX &
ADC
AGND
AREF
PC0 - PC6 PB0 - PB7
PD0 - PD7
AVR CPU
TWI
RESETATmega8A [DATASHEET] 4
8159E–AVR–02/2013
The Atmel®AVR® AVR core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient
while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega8A provides the following features: 8K bytes of In-System Programmable Flash with Read-WhileWrite
capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general purpose I/O lines, 32 general purpose
working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable
USART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eight channels in TQFP and
QFN/MLF packages) with 10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial
port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register
contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In
Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the
rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous
timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the
crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined
with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash Program memory
can be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory
programmer, or by an On-chip boot program running on the AVR core. The boot program can use any interface to
download the application program in the Application Flash memory. Software in the Boot Flash Section will continue
to run while the Application Flash Section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega8A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded
control applications.
The Atmel AVR ATmega8A is supported with a full suite of program and system development tools, including C
compilers, macro assemblers, program simulators and evaluation kits.
2.2 Pin Descriptions
2.2.1 VCC
Digital supply voltage.
2.2.2 GND
Ground.
2.2.3 Port B (PB7:PB0) – XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and
input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1 input for the Asynchronous
Timer/Counter2 if the AS2 bit in ASSR is set.ATmega8A [DATASHEET] 5
8159E–AVR–02/2013
The various special features of Port B are elaborated in “Alternate Functions of Port B” on page 56 and “System
Clock and Clock Options” on page 24.
2.2.4 Port C (PC5:PC0)
Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
2.2.5 PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ
from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the
minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in
Table 26-3 on page 228. Shorter pulses are not guaranteed to generate a Reset.
The various special features of Port C are elaborated on page 59.
2.2.6 Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega8A as listed on page 61.
2.2.7 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running. The minimum pulse length is given in Table 26-3 on page 228. Shorter pulses are not guaranteed to
generate a reset.
2.2.8 AVCC
AVCC is the supply voltage pin for the A/D Converter, Port C (3:0), and ADC (7:6). It should be externally connected
to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
Note that Port C (5:4) use digital supply voltage, VCC.
2.2.9 AREF
AREF is the analog reference pin for the A/D Converter.
2.2.10 ADC7:6 (TQFP and QFN/MLF Package Only)
In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered
from the analog supply and serve as 10-bit ADC channels.ATmega8A [DATASHEET] 6
8159E–AVR–02/2013
3. Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
Note: 1.
4. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20
years at 85°C or 100 years at 25°C.
5. About Code Examples
This datasheet contains simple code examples that briefly show how to use various parts of the device. These
code examples assume that the part specific header file is included before compilation. Be aware that not all C
compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
Please confirm with the C compiler documentation for more details.
6. Capacitive touch sensing
The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel
AVR® microcontrollers. The QTouch Library includes support for the QTouch and QMatrix® acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller.
This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the
touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library
User Guide - also available for download from the Atmel website.ATmega8A [DATASHEET] 7
8159E–AVR–02/2013
7. AVR CPU Core
7.1 Overview
This section discusses the Atmel®AVR® core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must therefore be able to access memories, perform calculations,
control peripherals, and handle interrupts.
Figure 7-1. Block Diagram of the AVR MCU Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories
and buses for program and data. Instructions in the Program memory are executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept
enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable
Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands
are output from the Register File, the operation is executed, and the result is stored back in the Register File
– in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –
enabling efficient address calculations. One of the these address pointers can also be used as an address pointer
for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
i/O Module 2
i/O Module1
i/O Module nATmega8A [DATASHEET] 8
8159E–AVR–02/2013
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single
register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation.
The Program flow is provided by conditional and unconditional jump and call instructions, able to directly address
the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory
address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot program section and the Application program
section. Both sections have dedicated Lock Bits for write and read/write protection. The SPM instruction that writes
into the Application Flash memory section must reside in the Boot program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total
SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data
SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in
the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have
priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the
priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register
File, 0x20 - 0x5F.
7.2 Arithmetic Logic Unit – ALU
The high-performance Atmel®AVR® ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register
and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical,
and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
7.3 Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the Status
Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
7.3.1 SREG – The AVR Status Register
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 9
8159E–AVR–02/2013
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control
is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts
are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an
interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set
and cleared by the application with the SEI and CLI instructions, as described in the Instruction Set Reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated
bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be
copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic.
See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See
the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description”
for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
7.4 General Purpose Register File
The Register File is optimized for the Atmel®AVR® Enhanced RISC instruction set. In order to achieve the required
performance and flexibility, the following input/output schemes are supported by the Register File:
• One 8-bit output operand and one 8-bit result input.
• Two 8-bit output operands and one 8-bit result input.
• Two 8-bit output operands and one 16-bit result input.
• One 16-bit output operand and one 16-bit result input.
Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.ATmega8A [DATASHEET] 10
8159E–AVR–02/2013
Figure 7-2. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single
cycle instructions.
As shown in Figure 7-2, each register is also assigned a Data memory address, mapping them directly into the first
32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory
organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to
index any register in the file.
7.4.1 The X-register, Y-register and Z-register
The registers R26:R31 have some added functions to their general purpose usage. These registers are 16-bit
address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are
defined as described in Figure 7-3.
Figure 7-3. The X-, Y- and Z-Registers
In the different addressing modes these address registers have functions as fixed displacement, automatic increment,
and automatic decrement (see the Instruction Set Reference for details).
7.5 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses
after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)ATmega8A [DATASHEET] 11
8159E–AVR–02/2013
locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data
SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease
the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts
are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be
set to point above start of the SRAM, see Figure 8-2 on page 16.
See Table 7-1 for Stack Pointer details.
The Atmel®AVR® Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR architecture is
so small that only SPL is needed. In this case, the SPH Register will not be present.
7.5.1 SPH and SPL – Stack Pointer High and Low Register
7.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The Atmel®AVR®CPU is
driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock
division is used.
Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture
and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with
the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Table 7-1. Stack Pointer instructions
Instruction Stack pointer Description
PUSH Decremented by 1 Data is pushed onto the stack
CALL
ICALL
RCALL
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
interrupt
POP Incremented by 1 Data is popped from the stack
RET
RETI
Incremented by 2 Return address is popped from the stack with return from
subroutine or return from interrupt
Bit 15 14 13 12 11 10 9 8
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
00000000ATmega8A [DATASHEET] 12
8159E–AVR–02/2013
Figure 7-4. The Parallel Instruction Fetches and Instruction Executions
Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
Figure 7-5. Single Cycle ALU Operation
7.7 Reset and Interrupt Handling
The Atmel®AVR® provides several different interrupt sources. These interrupts and the separate Reset Vector
each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable
bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to
enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when
Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory
Programming” on page 207 for details.
The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors.
The complete list of Vectors is shown in “Interrupts” on page 44. The list also determines the priority levels of the
different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next
is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the boot Flash section
by setting the Interrupt Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to
“Interrupts” on page 44 for more information. The Reset Vector can also be moved to the start of the boot Flash
section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming”
on page 194.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software
can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current
interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPUATmega8A [DATASHEET] 13
8159E–AVR–02/2013
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing
a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding
interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is
cleared, the corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable bit is set,
and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily
have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will
not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be
executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example
shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending
interrupts, as shown in the following example.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE ; start EEPROM write
sbi EECR, EEWE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1< xxx
:. :. :.
Table 12-2. Reset and Interrupt Vectors Placement
BOOTRST(1) IVSEL Reset Address Interrupt Vectors Start Address
1 0 0x000 0x001
1 1 0x000 Boot Reset Address + 0x001
0 0 Boot Reset Address 0x001
0 1 Boot Reset Address Boot Reset Address + 0x001ATmega8A [DATASHEET] 46
8159E–AVR–02/2013
When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes and the IVSEL bit in the GICR
Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and
Interrupt Vector Addresses is:
AddressLabels Code Comments
$000 rjmp RESET ; Reset handler
;
$001 RESET:ldi r16,high(RAMEND); Main program start
$002 out SPH,r16 ; Set Stack Pointer to top of RAM
$003 ldi r16,low(RAMEND)
$004 out SPL,r16
$005 sei ; Enable interrupts
$006 xxx
;
.org $c01
$c01 rjmp EXT_INT0 ; IRQ0 Handler
$c02 rjmp EXT_INT1 ; IRQ1 Handler
:. :. :. ;
$c12 rjmp SPM_RDY ; Store Program Memory Ready Handler
When the BOOTRST Fuse is programmed and the boot section size set to 2K bytes, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
AddressLabels Code Comments
.org $001
$001 rjmp EXT_INT0 ; IRQ0 Handler
$002 rjmp EXT_INT1 ; IRQ1 Handler
:. :. :. ;
$012 rjmp SPM_RDY ; Store Program Memory Ready Handler
;
.org $c00
$c00 rjmp RESET ; Reset handler
;
$c01 RESET:ldi r16,high(RAMEND); Main program start
$c02 out SPH,r16 ; Set Stack Pointer to top of RAM
$c03 ldi r16,low(RAMEND)
$c04 out SPL,r16
$c05 sei ; Enable interrupts
$c06 xxxATmega8A [DATASHEET] 47
8159E–AVR–02/2013
When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes, and the IVSEL bit in the GICR
Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and
Interrupt Vector Addresses is:
AddressLabels Code Comments
;
.org $c00
$c00 rjmp RESET ; Reset handler
$c01 rjmp EXT_INT0 ; IRQ0 Handler
$c02 rjmp EXT_INT1 ; IRQ1 Handler
:. :. :. ;
$c12 rjmp SPM_RDY ; Store Program Memory Ready Handler
$c13 RESET: ldi r16,high(RAMEND); Main program start
$c14 out SPH,r16 ; Set Stack Pointer to top of RAM
$c15 ldi r16,low(RAMEND)
$c16 out SPL,r16
$c17 sei ; Enable interrupts
$c18 xxx
12.1.1 Moving Interrupts Between Application and Boot Space
The General Interrupt Control Register controls the placement of the Interrupt Vector table.
12.2 Register Description
12.2.1 GICR – General Interrupt Control Register
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this
bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual
address of the start of the boot Flash section is determined by the BOOTSZ Fuses. Refer to the section “Boot
Loader Support – Read-While-Write Self-Programming” on page 194 for details. To avoid unintentional changes of
Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE
is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts
remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts
are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section
and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer
to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 194 for details on Boot Lock
Bits.
Bit 7 6 5 4 3 2 1 0
INT1 INT0 – – – – IVSEL IVCE GICR
Read/Write R/W R/W R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 48
8159E–AVR–02/2013
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four
cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the
IVSEL description above. See Code Example below.
Assembly Code Example
Move_interrupts:
; Enable change of Interrupt Vectors
ldi r16, (1< CSn2:0 > 1). The number
of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care
must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset
will affect the prescaler period for all Timer/Counters it is connected to.
16.4 External Clock Source
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin
is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is
then passed through the edge detector. Figure 16-1 shows a functional equivalent block diagram of the T1/T0 synchronization
and edge detector logic. The registers are clocked at the positive edge of the internal system clock
(clkI/O). The latch is transparent in the high period of the internal system clock.
The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it
detects.
Figure 16-1. T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has
been applied to the T1/T0 pin to the counter is updated.
Tn_sync
(To Clock
Select Logic)
Synchronization Edge Detector
D Q D Q
LE
Tn D Q
clkI/OATmega8A [DATASHEET] 72
8159E–AVR–02/2013
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock
cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling.
The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2)
given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it
can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system
clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended
that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 16-2. Prescaler for Timer/Counter0 and Timer/Counter1(1)
Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 16-1.
16.5 Register Description
16.5.1 SFIOR – Special Function IO Register
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The bit will be
cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that
Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.
This bit will always be read as zero.
PSR10
Clear
clkT1 clkT0
T1
T0
clkI/O
Synchronization
Synchronization
Bit 7 6 5 4 3 2 1 0
– – – – ACME PUD PSR2 PSR10 SFIOR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 73
8159E–AVR–02/2013
17. 16-bit Timer/Counter1
17.1 Features • True 16-bit Design (i.e., allows 16-bit PWM)
• Two Independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• External Event Counter
• Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
17.2 Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation,
and signal timing measurement. Most register and bit references in this section are written in general form. A lower
case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel.
However, when using the register or bit defines in a program, the precise form must be used i.e., TCNT1 for
accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 17-1. For the actual placement of I/O
pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are
shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 92.ATmega8A [DATASHEET] 74
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Figure 17-1. 16-bit Timer/Counter Block Diagram(1)
Note: 1. Refer to “Pin Configurations” on page 2, Table 13-2 on page 56, and Table 13-8 on page 61 for Timer/Counter1 pin
placement and description.
17.2.1 Registers
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all
16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are
described in the section “Accessing 16-bit Registers” on page 75. The Timer/Counter Control Registers
(TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in
the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked
with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers
are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement)
its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is
referred to as the timer clock (clkT1).
The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time.
The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output
on the Output Compare Pin (OC1A/B). See “Output Compare Units” on page 81. The Compare Match event will
also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.
Clock Select
Timer/Counter
DATA BUS
OCRnA
OCRnB
ICRn
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
= 0
TOP BOTTOM
Count
Clear
Direction
TOVn
(Int. Req.)
OCFnA
(Int. Req.)
OCFnB
(Int.Req.)
ICFn (Int.Req.)
TCCRnA TCCRnB
( From Analog
Comparator Ouput )
Tn Edge
Detector
( From Prescaler )
clkTnATmega8A [DATASHEET] 75
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The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on
either the Input Capture Pin (ICP1) or on the Analog Comparator pins (see “Analog Comparator” on page 179).
The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise
spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the
OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM
mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP value will in this
case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the
ICR1 Register can be used as an alternative, freeing the OCR1A to be used as PWM output.
17.2.2 Definitions
The following definitions are used extensively throughout the document:
17.2.3 Compatibility
The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Counter.
This 16-bit Timer/Counter is fully compatible with the earlier version regarding:
• All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers.
• Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers.
• Interrupt Vectors.
• The following control bits have changed name, but have same functionality and register location:
• PWM10 is changed to WGM10.
• PWM11 is changed to WGM11.
• CTC1 is changed to WGM12.
The following bits are added to the 16-bit Timer/Counter Control Registers:
• FOC1A and FOC1B are added to TCCR1A.
• WGM13 is added to TCCR1B.
The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases.
17.3 Accessing 16-bit Registers
The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus.
The 16-bit register must be byte accessed using two read or write operations. The 16-bit timer has a single 8-bit
register for temporary storing of the High byte of the 16-bit access. The same temporary register is shared between
all 16-bit registers within the 16-bit timer. Accessing the Low byte triggers the 16-bit read or write operation. When
the Low byte of a 16-bit register is written by the CPU, the High byte stored in the temporary register, and the Low
byte written are both copied into the 16-bit register in the same clock cycle. When the Low byte of a 16-bit register
is read by the CPU, the High byte of the 16-bit register is copied into the temporary register in the same clock cycle
as the Low byte is read.
Table 17-1. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.
MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
TOP The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be one of the fixed values:
0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 Register.
The assignment is dependent of the mode of operation.ATmega8A [DATASHEET] 76
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Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCR1A/B 16-bit registers does
not involve using the temporary register.
To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the Low byte must be
read before the High byte.
The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates
the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers.
Note that when using “C”, the compiler handles the 16-bit access.
Note: 1. See “About Code Examples” on page 6.
The assembly code example returns the TCNT1 value in the r17:r16 Register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two
instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the
same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted.
Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable
the interrupts during the 16-bit access.
Assembly Code Example(1)
:.
; Set TCNT1 to 0x01FF
ldi r17,0x01
ldi r16,0xFF
out TCNT1H,r17
out TCNT1L,r16
; Read TCNT1 into r17:r16
in r16,TCNT1L
in r17,TCNT1H
:.
C Code Example(1)
unsigned int i;
:.
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
:.ATmega8A [DATASHEET] 77
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The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the
OCR1A/B or ICR1 Registers can be done by using the same principle.
Note: 1. See “About Code Examples” on page 6.
The assembly code example returns the TCNT1 value in the r17:r16 Register pair.
Assembly Code Example(1)
TIM16_ReadTCNT1:
; Save Global Interrupt Flag
in r18,SREG
; Disable interrupts
cli
; Read TCNT1 into r17:r16
in r16,TCNT1L
in r17,TCNT1H
; Restore Global Interrupt Flag
out SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
/* Save Global Interrupt Flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore Global Interrupt Flag */
SREG = sreg;
return i;
}ATmega8A [DATASHEET] 78
8159E–AVR–02/2013
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the
OCR1A/B or ICR1 Registers can be done by using the same principle.
Note: 1. See “About Code Examples” on page 6.
The assembly code example requires that the r17:r16 Register pair contains the value to be written to TCNT1.
17.3.1 Reusing the Temporary High Byte Register
If writing to more than one 16-bit register where the High byte is the same for all registers written, then the High
byte only needs to be written once. However, note that the same rule of atomic operation described previously also
applies in this case.
17.4 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the
clock select logic which is controlled by the clock select (CS12:0) bits located in the Timer/Counter Control Register
B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers”
on page 71.
17.5 Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 17-2 shows
a block diagram of the counter and its surroundings.
Assembly Code Example(1)
TIM16_WriteTCNT1:
; Save Global Interrupt Flag
in r18,SREG
; Disable interrupts
cli
; Set TCNT1 to r17:r16
out TCNT1H,r17
out TCNT1L,r16
; Restore Global Interrupt Flag
out SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNT1( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save Global Interrupt Flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore Global Interrupt Flag */
SREG = sreg;
}ATmega8A [DATASHEET] 79
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Figure 17-2. Counter Unit Block Diagram
Signal description (internal signals):
count Increment or decrement TCNT1 by 1.
direction Select between increment and decrement.
clear Clear TCNT1 (set all bits to zero).
clkT1 Timer/Counter clock.
TOP Signalize that TCNT1 has reached maximum value.
BOTTOM Signalize that TCNT1 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (TCNT1H) containing the upper
eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can
only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU
accesses the High byte temporary register (TEMP). The temporary register is updated with the TCNT1H value
when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This
allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is
important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that
will give unpredictable results. The special cases are described in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer
clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the clock select bits
(CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be
accessed by the CPU, independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in
the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how
the counter behaves (counts) and how waveforms are generated on the Output Compare Outputs OC1x. For more
details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 84.
The Timer/Counter Overflow (TOV1) fLag is set according to the mode of operation selected by the WGM13:0 bits.
TOV1 can be used for generating a CPU interrupt.
17.6 Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a timestamp
indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via
the ICP1 pin or alternatively, via the Analog Comparator unit. The time-stamps can then be used to calculate freTEMP
(8-bit)
DATA BUS (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit) Control Logic
count
clear
direction
TOVn
(Int. Req.)
Clock Select
TOP BOTTOM
Tn Edge
Detector
( From Prescaler )
clkTnATmega8A [DATASHEET] 80
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quency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating
a log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 17-3. The elements of the block diagram
that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates
the Timer/Counter number.
Figure 17-3. Input Capture Unit Block Diagram
When a change of the logic level (an event) occurs on the Input Capture Pin (ICP1), alternatively on the Analog
Comparator Output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered.
When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Input Capture Register
(ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1
Register. If enabled (TICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is
automatically cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software by
writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the Low byte (ICR1L) and
then the High byte (ICR1H). When the Low byte is read the High byte is copied into the High byte temporary register
(TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for
defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set
before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the High byte must be
written to the ICR1H I/O location before the Low byte is written to ICR1L.
For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 75.
17.6.1 Input Capture Pin Source
The main trigger source for the Input Capture unit is the Input Capture Pin (ICP1). Timer/Counter 1 can alternatively
use the Analog Comparator Output as trigger source for the Input Capture unit. The Analog Comparator is
selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator
ICFn (Int. Req.)
Analog
Comparator
WRITE ICRn (16-bit Register)
ICRnH (8-bit)
Noise
Canceler
ICPn
Edge
Detector
TEMP (8-bit)
DATA BUS (8-bit)
ICRnL (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
ACO* ACIC* ICNC ICESATmega8A [DATASHEET] 81
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Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture
Flag must therefore be cleared after the change.
Both the Input Capture Pin (ICP1) and the Analog Comparator Output (ACO) inputs are sampled using the same
technique as for the T1 pin (Figure 16-1 on page 71). The edge detector is also identical. However, when the noise
canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system
clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter
is set in a Waveform Generation mode that uses ICR1 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
17.6.2 Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is
monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge
detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter Control
Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay
from a change applied to the input, to the update of the ICR1 Register. The noise canceler uses the system clock
and is therefore not affected by the prescaler.
17.6.3 Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the
incoming events. The time between two events is critical. If the processor has not read the captured value in the
ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of
the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine
as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response
time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during
operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture.
Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a
change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit
location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is
used).
17.7 Output Compare Units
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals
OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock
cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x Flag
is automatically cleared when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software
by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output
according to operating mode set by the Waveform Generation mode (WGM13:0) bits and Compare Output mode
(COM1x1:0) bits. The TOP and BOTTOM signals are used by the waveform generator for handling the special
cases of the extreme values in some modes of operation (See “Modes of Operation” on page 84.)
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e. counter resolution).
In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the
waveform generator.ATmega8A [DATASHEET] 82
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Figure 17-4 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates
the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The
elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded.
Figure 17-4. Output Compare Unit, Block Diagram
The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For
the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double
buffering synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x
directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the
Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is
not read via the High byte temporary register (TEMP). However, it is a good practice to read the Low byte first as
when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the
compare of all 16-bit is done continuously. The High byte (OCR1xH) has to be written first. When the High byte I/O
location is written by the CPU, the TEMP Register will be updated by the value written. Then when the Low byte
(OCR1xL) is written to the lower eight bits, the High byte will be copied into the upper 8-bits of either the OCR1x
buffer or OCR1x Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 75.
17.7.1 Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to
the Force Output Compare (FOC1x) bit. Forcing Compare Match will not set the OCF1x Flag or reload/clear the
timer, but the OC1x pin will be updated as if a real Compare Match had occurred (the COM1x1:0 bits settings
define whether the OC1x pin is set, cleared or toggled).
OCFnx (Int.Req.)
= (16-bit Comparator )
OCRnx Buffer (16-bit Register)
OCRnxH Buf. (8-bit)
OCnx
TEMP (8-bit)
DATA BUS (8-bit)
OCRnxL Buf. (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
WGMn3:0 COMnx1:0
OCRnx (16-bit Register)
OCRnxH (8-bit) OCRnxL (8-bit)
Waveform Generator
TOP
BOTTOMATmega8A [DATASHEET] 83
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17.7.2 Compare Match Blocking by TCNT1 Write
All CPU writes to the TCNT1 Register will block any Compare Match that occurs in the next timer clock cycle, even
when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering
an interrupt when the Timer/Counter clock is enabled.
17.7.3 Using the Output Compare Unit
Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are
risks involved when changing TCNT1 when using any of the Output Compare channels, independent of whether
the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the Compare Match will
be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with
variable TOP values. The Compare Match for the TOP will be ignored and the counter will continue to 0xFFFF.
Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting.
The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to output.
The easiest way of setting the OC1x value is to use the Force Output Compare (FOC1x) strobe bits in Normal
mode. The OC1x Register keeps its value even when changing between Waveform Generation modes.
Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the
COM1x1:0 bits will take effect immediately.
17.8 Compare Match Output Unit
The Compare Output mode (COM1x1:0) bits have two functions. The waveform generator uses the COM1x1:0 bits
for defining the Output Compare (OC1x) state at the next Compare Match. Secondly the COM1x1:0 bits control the
OC1x pin output source. Figure 17-5 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting.
The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port
Control Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x
state, the reference is for the internal OC1x Register, not the OC1x pin. If a System Reset occur, the OC1x Register
is reset to “0”.
Figure 17-5. Compare Match Output Unit, Schematic
PORT
DDR
D Q
D Q
OCnx
OCnx Pin
D Q Waveform
Generator
COMnx1
COMnx0
0
1
DATABUS
FOCnx
clkI/OATmega8A [DATASHEET] 84
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The general I/O port function is overridden by the Output Compare (OC1x) from the waveform generator if either of
the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction
Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set as output
before the OC1x value is visible on the pin. The port override function is generally independent of the
Waveform Generation mode, but there are some exceptions. Refer to Table 17-2, Table 17-3 and Table 17-4 for
details.
The design of the Output Compare Pin logic allows initialization of the OC1x state before the output is enabled.
Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See “Register Description” on
page 92.
The COM1x1:0 bits have no effect on the Input Capture unit.
17.8.1 Compare Output Mode and Waveform Generation
The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting
the COM1x1:0 = 0 tells the waveform generator that no action on the OC1x Register is to be performed on the
next Compare Match. For compare output actions in the non-PWM modes refer to Table 17-2 on page 93. For fast
PWM mode refer to Table 17-3 on page 93, and for phase correct and phase and frequency correct PWM refer to
Table 17-4 on page 93.
A change of the COM1x1:0 bits state will have effect at the first Compare Match after the bits are written. For nonPWM
modes, the action can be forced to have immediate effect by using the FOC1x strobe bits.
17.9 Modes of Operation
The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined by the
combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted
PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or toggle at a
Compare Match. See “Compare Match Output Unit” on page 83.
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 91.
17.9.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum
16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter
Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in
this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by software. There are no
special cases to consider in the Normal mode, a new counter value can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the
external events must not exceed the resolution of the counter. If the interval between events are too long, the timer
overflow interrupt or the prescaler must be used to extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
17.9.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to manipulate
the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches
either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for theATmega8A [DATASHEET] 85
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counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also
simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 17-6. The counter value (TCNT1) increases until a Compare
Match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.
Figure 17-6. CTC Mode, Timing Diagram
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or
ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler
routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when
the counter is running with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR1A or ICR1 is lower than the current value of
TCNT1, the counter will miss the Compare Match. The counter will then have to count to its maximum value
(0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. In many cases this feature is
not desirable. An alternative will then be to use the fast PWM mode using OCR1A for defining TOP (WGM13:0 =
15) since the OCR1A then will be double buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on each
Compare Match by setting the Compare Output mode bits to toggle mode (COM1A1:0 = 1). The OC1A value will
not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC1A = 1). The waveform
generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform
frequency is defined by the following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x0000.
17.9.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation.
The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode,
the Output Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x, and set at BOTTOM.
In inverting Compare Output mode output is set on Compare Match and cleared at BOTTOM. Due to the singleslope
operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and
phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM
TCNTn
OCnA
(Toggle)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
Period 1 2 3 4
(COMnA1:0 = 1)
f
OCnA
f
clk_I/O
2 N 1 + OCRnA = --------------------------------------------------ATmega8A [DATASHEET] 86
8159E–AVR–02/2013
mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum
resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or
OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation:
In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values
0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A
(WGM13:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 17-7. The figure shows fast PWM mode when OCR1A or ICR1 is used to define
TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation.
The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1
slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a
Compare Match occurs.
Figure 17-7. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OCF1A or
ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the
TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and
compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will
never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are
masked to zero when any of the OCR1x Registers are written.
The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1
Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with
none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of
TCNT1. The result will then be that the counter will miss the Compare Match at the TOP value. The counter will
then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can
occur. The OCR1A Register, however, is double buffered. This feature allows the OCR1A I/O location to be written
anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The
OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle
RFPWM
log TOP + 1
log 2 = -----------------------------------
TCNTn
OCRnx / TOP Update
and TOVn Interrupt Flag
Set and OCnA Interrupt
Flag Set or ICFn
Interrupt Flag Set
(Interrupt on TOP)
Period 1 2 3 4 5 6 7 8
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)ATmega8A [DATASHEET] 87
8159E–AVR–02/2013
the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the
TOV1 Flag is set.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A
Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively
changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer
feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the
COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the
COM1x1:0 to 3. See Table 17-3 on page 93. The actual OC1x value will only be visible on the port pin if the data
direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing)
the OC1x Register at the Compare Match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register
at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each
TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending
on the polarity of the output set by the COM1x1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A to toggle
its logical level on each Compare Match (COM1A1:0 = 1). This applies only if OCR1A is used to define the TOP
value (WGM13:0 = 15). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A
is set to zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buffer feature of
the Output Compare unit is enabled in the fast PWM mode.
17.9.4 Phase Correct PWM Mode
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a
high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase
and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output
Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x while upcounting, and set on the
Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope
operation has lower maximum operation frequency than single slope operation. However, due to the symmetric
feature of the dual-slope PWM modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or
OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is
16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values
0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in
OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1
value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 17-8. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The
TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent
f
OCnxPWM
f
clk_I/O
N 1 + TOP = -----------------------------------
RPCPWM
log TOP + 1
log 2 = -----------------------------------ATmega8A [DATASHEET] 88
8159E–AVR–02/2013
compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match
occurs.
Figure 17-8. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or
ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as
the OCR1x Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to generate
an interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will
never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are
masked to zero when any of the OCR1x Registers are written. As the third period shown in Figure 17-8 illustrates,
changing the TOP actively while the Timer/Counter is running in the Phase Correct mode can result in an unsymmetrical
output. The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x
update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is
determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value.
When these two values differ the two slopes of the period will differ in length. The difference in length gives the
unsymmetrical result on the output.
It is recommended to use the Phase and Frequency Correct mode instead of the Phase Correct mode when
changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no
differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting
the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COM1x1:0 to 3. See Table 17-4 on page 93. The actual OC1x value will only be visible on the port pin if the
data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing)
the OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter increments, and
clearing (or setting) the OC1x Register at Compare Match between OCR1x and TCNT1 when the counter decrements.
The PWM frequency for the output when using phase correct PWM can be calculated by the following
equation:
OCRnx / TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
f
OCnxPCPWM
f
clk_I/O
2 N TOP = ----------------------------ATmega8A [DATASHEET] 89
8159E–AVR–02/2013
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set
equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
If OCR1A is used to define the TOP value (WMG13:0 = 11) and COM1A1:0 = 1, the OC1A output will toggle with a
50% duty cycle.
17.9.5 Phase and Frequency Correct PWM Mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0
= 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase
and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The
counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare
Output mode, the Output Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x
while upcounting, and set on the Compare Match while downcounting. In inverting Compare Output mode, the
operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are
preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the
OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 17-8 and Figure 17-9).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A.
The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit
(ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation:
In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the
value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and
changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram
for the phase correct and frequency correct PWM mode is shown on Figure 17-9. The figure shows phase and
frequency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing
diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between
OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs.
RPFCPWM
log TOP + 1
log 2 = -----------------------------------ATmega8A [DATASHEET] 90
8159E–AVR–02/2013
Figure 17-9. Phase and Frequency Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated
with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the
OC1A or ICF1 Flag set when TCNT1 has reached TOP. The Interrupt Flags can then be used to generate an interrupt
each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will
never occur between the TCNT1 and the OCR1x.
As Figure 17-9 shows the output generated is, in contrast to the Phase Correct mode, symmetrical in all periods.
Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be
equal. This gives symmetrical output pulses and is therefore frequency correct.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A
Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively
changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer
feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x
pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated
by setting the COM1x1:0 to 3. See Table 17-4 on page 93. The actual OC1x value will only be visible on the
port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting
(or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter
increments, and clearing (or setting) the OC1x Register at Compare Match between OCR1x and TCNT1 when the
counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated
by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set
equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the
opposite logic values.
OCRnx / TOP Update and
TOVn Interrupt Flag Set
(Interrupt on Bottom)
OCnA Interrupt Flag Set or
ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
f
OCnxPFCPWM
f
clk_I/O
2 N TOP = ----------------------------ATmega8A [DATASHEET] 91
8159E–AVR–02/2013
If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a
50% duty cycle.
17.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal
in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x Register
is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 17-10 shows a
timing diagram for the setting of OCF1x.
Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 17-11 shows the same timing data, but with the prescaler enabled.
Figure 17-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8)
Figure 17-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct
PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should
be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the
TOV1 Flag at BOTTOM.
clkTn
(clkI/O/1)
OCFnx
clkI/O
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clkI/O
clkTn
(clkI/O/8)ATmega8A [DATASHEET] 92
8159E–AVR–02/2013
Figure 17-12. Timer/Counter Timing Diagram, no Prescaling
Figure 17-13 shows the same timing data, but with the prescaler enabled.
Figure 17-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
17.11 Register Description
17.11.1 TCCR1A – Timer/Counter 1 Control Register A
• Bit 7:6 – COM1A1:0: Compare Output Mode for channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for channel B
The COM1A1:0 and COM1B1:0 control the Output Compare Pins (OC1A and OC1B respectively) behavior. If one
or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx Value New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clkTn
(clkI/O/1)
clkI/O
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx Value New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)
Bit 7 6 5 4 3 2 1 0
COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 TCCR1A
Read/Write R/W R/W R/W R/W W W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 93
8159E–AVR–02/2013
pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal
port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding
to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0
bits setting. Table 17-2 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC
mode (non-PWM).
Table 17-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode.
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the Compare
Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 85. for more details.
Table 17-4 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase
and frequency correct, PWM mode.
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See “Phase Correct PWM
Mode” on page 87. for more details.
Table 17-2. Compare Output Mode, Non-PWM
COM1A1/
COM1B1
COM1A0/
COM1B0 Description
0 0 Normal port operation, OC1A/OC1B disconnected.
0 1 Toggle OC1A/OC1B on Compare Match
1 0 Clear OC1A/OC1B on Compare Match (Set output to low level)
1 1 Set OC1A/OC1B on Compare Match (Set output to high level)
Table 17-3. Compare Output Mode, Fast PWM(1)
COM1A1/
COM1B1
COM1A0/
COM1B0 Description
0 0 Normal port operation, OC1A/OC1B disconnected.
0 1 WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected
(normal port operation). For all other WGM1 settings, normal port
operation, OC1A/OC1B disconnected.
1 0 Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at BOTTOM,
(non-inverting mode)
1 1 Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at BOTTOM,
(inverting mode)
Table 17-4. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1)
COM1A1/
COM1B1
COM1A0/
COM1B0 Description
0 0 Normal port operation, OC1A/OC1B disconnected.
0 1 WGM13:0 = 9 or 14: Toggle OC1A on Compare Match, OC1B
disconnected (normal port operation). For all other WGM1 settings,
normal port operation, OC1A/OC1B disconnected.
1 0 Clear OC1A/OC1B on Compare Match when up-counting. Set
OC1A/OC1B on Compare Match when downcounting.
1 1 Set OC1A/OC1B on Compare Match when up-counting. Clear
OC1A/OC1B on Compare Match when downcounting.ATmega8A [DATASHEET] 94
8159E–AVR–02/2013
• Bit 3 – FOC1A: Force Output Compare for channel A
• Bit 2 – FOC1B: Force Output Compare for channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring
compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a
PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate Compare Match is forced on the
waveform generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that
the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that
determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match
(CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
• Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the
counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see
Table 17-5. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on
Compare Match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation”
on page 84.)
Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
Table 17-5. Waveform Generation Mode Bit Description
Mode WGM13
WGM12
(CTC1)
WGM11
(PWM11)
WGM10
(PWM10)
Timer/Counter Mode of
Operation(1) TOP
Update of
OCR1x
TOV1 Flag
Set on
0 0 0 0 0 Normal 0xFFFF Immediate MAX
1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM
2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM
3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM
4 0 1 0 0 CTC OCR1A Immediate MAX
5 0 1 0 1 Fast PWM, 8-bit 0x00FF BOTTOM TOP
6 0 1 1 0 Fast PWM, 9-bit 0x01FF BOTTOM TOP
7 0 1 1 1 Fast PWM, 10-bit 0x03FF BOTTOM TOP
8 1 0 0 0 PWM, Phase and Frequency Correct ICR1 BOTTOM BOTTOM
9 1 0 0 1 PWM, Phase and Frequency Correct OCR1A BOTTOM BOTTOM
10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM
11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM
12 1 1 0 0 CTC ICR1 Immediate MAX
13 1 1 0 1 (Reserved) – – –
14 1 1 1 0 Fast PWM ICR1 BOTTOM TOP
15 1 1 1 1 Fast PWM OCR1A BOTTOM TOPATmega8A [DATASHEET] 95
8159E–AVR–02/2013
17.11.2 TCCR1B – Timer/Counter 1 Control Register B
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input
from the Input Capture Pin (ICP1) is filtered. The filter function requires four successive equal valued samples of
the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the
noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a capture event. When the
ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a
rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register
(ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture
Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the
TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero
when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Figure 17-10 and Figure
17-11.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
Bit 7 6 5 4 3 2 1 0
ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 17-6. Clock Select Bit Description
CS12 CS11 CS10 Description
0 0 0 No clock source. (Timer/Counter stopped)
0 0 1 clkI/O/1 (No prescaling)
0 1 0 clkI/O/8 (From prescaler)
0 1 1 clkI/O/64 (From prescaler)
1 0 0 clkI/O/256 (From prescaler)
1 0 1 clkI/O/1024 (From prescaler)
1 1 0 External clock source on T1 pin. Clock on falling edge.
1 1 1 External clock source on T1 pin. Clock on rising edge.ATmega8A [DATASHEET] 96
8159E–AVR–02/2013
17.11.3 TCNT1H and TCNT1L – Timer/Counter 1
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read
and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and Low bytes are
read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See
“Accessing 16-bit Registers” on page 75.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a Compare Match between
TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the Compare Match on the following timer clock for all compare
units.
17.11.4 OCR1AH and OCR1AL– Output Compare Register 1 A
17.11.5 OCR1BH and OCR1BL – Output Compare Register 1 B
The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value
(TCNT1). A match can be used to generate an Output Compare Interrupt, or to generate a waveform output on the
OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and Low bytes are written simultaneously
when the CPU writes to these registers, the access is performed using an 8-bit temporary High byte
Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers”
on page 75.
17.11.6 ICR1H and ICR1L – Input Capture Register 1
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or
optionally on the Analog Comparator Output for Timer/Counter1). The Input Capture can be used for defining the
counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit temporary High byte Register
Bit 7 6 5 4 3 2 1 0
TCNT1[15:8] TCNT1H
TCNT1[7:0] TCNT1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR1A[15:8] OCR1AH
OCR1A[7:0] OCR1AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR1B[15:8] OCR1BH
OCR1B[7:0] OCR1BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ICR1[15:8] ICR1H
ICR1[7:0] ICR1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 97
8159E–AVR–02/2013
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on
page 75.
17.11.7 TIMSK(1) – Timer/Counter Interrupt Mask Register
Note: 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this
section. The remaining bits are described in their respective timer sections.
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Input Capture Interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page
44) is executed when the ICF1 Flag, located in TIFR, is set.
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Output Compare A match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts”
on page 44) is executed when the OCF1A Flag, located in TIFR, is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Output Compare B match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts”
on page 44) is executed when the OCF1B Flag, located in TIFR, is set.
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 44) is
executed when the TOV1 Flag, located in TIFR, is set.
17.11.8 TIFR(1) – Timer/Counter Interrupt Flag Register
Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The
remaining bits are described in their respective timer sections.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the
WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be
cleared by writing a logic one to its bit location.
• Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A
(OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
Bit 7 6 5 4 3 2 1 0
OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 TIMSK
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 TIFR
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 98
8159E–AVR–02/2013
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively,
OCF1A can be cleared by writing a logic one to its bit location.
• Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B
(OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively,
OCF1B can be cleared by writing a logic one to its bit location.
• Bit 2 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting. In normal and CTC modes, the TOV1 Flag is set
when the timer overflows. Refer to Table 17-5 on page 94 for the TOV1 Flag behavior when using another
WGM13:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1
can be cleared by writing a logic one to its bit location.ATmega8A [DATASHEET] 99
8159E–AVR–02/2013
18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
18.1 Features • Single Channel Counter
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, phase Correct Pulse Width Modulator (PWM)
• Frequency Generator
• 10-bit Clock Prescaler
• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)
• Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock
18.2 Overview
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified block diagram of
the 8-bit Timer/Counter is shown in Figure 18-1. For the actual placement of I/O pins, refer to “Pin Configurations”
on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O
Register and bit locations are listed in the “Register Description” on page 112.
Figure 18-1. 8-bit Timer/Counter Block Diagram
Timer/Counter
DATA BUS
=
TCNTn
Waveform
Generation OCn
= 0
Control Logic
= 0xFF
BOTTOM TOP
count
clear
direction
TOVn
(Int. Req.)
OCn
(Int. Req.)
Synchronization Unit
OCRn
TCCRn
ASSRn
Status Flags
clkI/O
clkASY
Synchronized Status Flags
asynchronous Mode
Select (ASn)
TOSC1
T/C
Oscillator
TOSC2
Prescaler
clkTn
clkI/OATmega8A [DATASHEET] 100
8159E–AVR–02/2013
18.2.1 Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten
as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked
with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers
are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins,
as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register
(ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement)
its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select
logic is referred to as the timer clock (clkT2).
The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times. The
result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on
the Output Compare Pin (OC2). For details, see “Output Compare Unit” on page 101. The Compare Match event
will also set the Compare Flag (OCF2) which can be used to generate an Output Compare interrupt request.
18.2.2 Definitions
Many register and bit references in this document are written in general form. A lower case “n” replaces the
Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise
form must be used (i.e., TCNT2 for accessing Timer/Counter2 counter value and so on).
The definitions in Table 18-1 are also used extensively throughout the document.
18.3 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The
clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to
logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For
details on asynchronous operation, see “Asynchronous Operation of the Timer/Counter” on page 109. For details
on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 71.
18.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 18-2 shows a
block diagram of the counter and its surrounding environment.
Table 18-1. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR2 Register. The assignment is dependent
on the mode of operation.ATmega8A [DATASHEET] 101
8159E–AVR–02/2013
Figure 18-2. Counter Unit Block Diagram
Signal description (internal signals):
count Increment or decrement TCNT2 by 1.
direction Selects between increment and decrement.
clear Clear TCNT2 (set all bits to zero).
clkT2 Timer/Counter clock.
TOP Signalizes that TCNT2 has reached maximum value.
BOTTOM Signalizes that TCNT2 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer
clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the clock select bits
(CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be
accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter
Control Register (TCCR2). There are close connections between how the counter behaves (counts) and how
waveforms are generated on the Output Compare Output OC2. For more details about advanced counting
sequences and waveform generation, see “Modes of Operation” on page 104.
The Timer/Counter Overflow (TOV2) Flag is set according to the mode of operation selected by the WGM21:0 bits.
TOV2 can be used for generating a CPU interrupt.
18.5 Output Compare Unit
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2). Whenever
TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare Flag (OCF2) at the
next timer clock cycle. If enabled (OCIE2 = 1), the Output Compare Flag generates an Output Compare interrupt.
The OCF2 Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 Flag can be
cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to
generate an output according to operating mode set by the WGM21:0 bits and Compare Output mode (COM21:0)
bits. The max and bottom signals are used by the waveform generator for handling the special cases of the
extreme values in some modes of operation (see “Modes of Operation” on page 104).
Figure 18-3 shows a block diagram of the Output Compare unit.
DATA BUS
TCNTn Control Logic
count
TOVn
(Int. Req.)
BOTTOM TOP
direction
clear
TOSC1
T/C
Oscillator
TOSC2
Prescaler
clkI/O
clk TnATmega8A [DATASHEET] 102
8159E–AVR–02/2013
Figure 18-3. Output Compare Unit, Block Diagram
The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal
and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering
synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence. The
synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCR2 Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR2 Buffer Register, and if double buffering is disabled the CPU will access the OCR2
directly.
18.5.1 Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to
the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the OCF2 Flag or reload/clear the
timer, but the OC2 pin will be updated as if a real Compare Match had occurred (the COM21:0 bits settings define
whether the OC2 pin is set, cleared or toggled).
18.5.2 Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 Register will block any Compare Match that occurs in the next timer clock
cycle, even when the timer is stopped. This feature allows OCR2 to be initialized to the same value as TCNT2 without
triggering an interrupt when the Timer/Counter clock is enabled.
18.5.3 Using the Output Compare Unit
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are
risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the
Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2 value, the Compare Match will be
OCFn (Int. Req.)
= (8-bit Comparator )
OCRn
OCxy
DATA BUS
TCNTn
WGMn1:0
Waveform Generator
TOP
FOCn
COMn1:0
BOTTOMATmega8A [DATASHEET] 103
8159E–AVR–02/2013
missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM
when the counter is downcounting.
The setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The
easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bit in Normal mode. The
OC2 Register keeps its value even when changing between waveform generation modes.
Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0
bits will take effect immediately.
18.6 Compare Match Output Unit
The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses the COM21:0 bits
for defining the Output Compare (OC2) state at the next Compare Match. Also, the COM21:0 bits control the OC2
pin output source. Figure 18-4 shows a simplified schematic of the logic affected by the COM21:0 bit setting. The
I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control
Registers (DDR and PORT) that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the
reference is for the internal OC2 Register, not the OC2 pin.
Figure 18-4. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC2) from the waveform generator if either of
the COM21:0 bits are set. However, the OC2 pin direction (input or output) is still controlled by the Data Direction
Register (DDR) for the port pin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as output
before the OC2 value is visible on the pin. The port override function is independent of the Waveform Generation
mode.
PORT
DDR
D Q
D Q
OCn
OCn Pin
D Q Waveform
Generator
COMn1
COMn0
0
1
DATABUS
FOCn
clkI/OATmega8A [DATASHEET] 104
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The design of the Output Compare Pin logic allows initialization of the OC2 state before the output is enabled. Note
that some COM21:0 bit settings are reserved for certain modes of operation. See “Register Description” on page
112.
18.6.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWM modes. For all modes, setting
the COM21:0 = 0 tells the waveform generator that no action on the OC2 Register is to be performed on the
next Compare Match. For compare output actions in the non-PWM modes refer to Table 18-3 on page 112. For
fast PWM mode, refer to Table 18-4 on page 113, and for phase correct PWM refer to Table 18-5 on page 113.
A change of the COM21:0 bits state will have effect at the first Compare Match after the bits are written. For nonPWM
modes, the action can be forced to have immediate effect by using the FOC2 strobe bits.
18.7 Modes of Operation
The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined by the
combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM21:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted
PWM). For non-PWM modes the COM21:0 bits control whether the output should be set, cleared, or toggled at a
Compare Match (see “Compare Match Output Unit” on page 103).
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 108.
18.7.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-
bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow
Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case
behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal mode, a new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
18.7.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter
resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2. The
OCR2 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare
Match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 18-5. The counter value (TCNT2) increases until a Compare
Match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared.ATmega8A [DATASHEET] 105
8159E–AVR–02/2013
Figure 18-5. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the
TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done
with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2 is
lower than the current value of TCNT2, the counter will miss the Compare Match. The counter will then have to
count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur.
For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical level on each Compare
Match by setting the Compare Output mode bits to toggle mode (COM21:0 = 1). The OC2 value will not be
visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a
maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The waveform frequency is defined by the
following equation:
The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x00.
18.7.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM waveform
generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter
counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output
Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2, and set at BOTTOM. In inverting
Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope
operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode
that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation,
rectification, and DAC applications. High frequency allows physically small sized external components (coils,
capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then
cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 18-6. The
TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent
compare matches between OCR2 and TCNT2.
TCNTn
OCn
(Toggle)
OCn Interrupt Flag Set
Period 1 2 3 4
(COMn1:0 = 1)
f
OCn
f
clk_I/O
2 N 1 + OCRn = ----------------------------------------------ATmega8A [DATASHEET] 106
8159E–AVR–02/2013
Figure 18-6. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the
interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0
bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM21:0
to 3 (see Table 18-4 on page 113). The actual OC2 value will only be visible on the port pin if the data direction for
the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2 Register at the
Compare Match between OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the
counter is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer
clock cycle. Setting the OCR2 equal to MAX will result in a constantly high or low output (depending on the polarity
of the output set by the COM21:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2 to toggle
its logical level on each Compare Match (COM21:0 = 1). The waveform generated will have a maximum frequency
of foc2 = fclk_I/O/2 when OCR2 is set to zero. This feature is similar to the OC2 toggle in CTC mode, except the double
buffer feature of the Output Compare unit is enabled in the fast PWM mode.
18.7.4 Phase Correct PWM Mode
The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM waveform generation
option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from
BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare
(OC2) is cleared on the Compare Match between TCNT2 and OCR2 while upcounting, and set on the Compare
Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation
TCNTn
OCRn Update
and
TOVn Interrupt Flag Set
Period 1 2 3
OCn
OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
OCRn Interrupt Flag Set
4 5 6 7
f
OCnPWM
f
clk_I/O
N 256 = ------------------ATmega8A [DATASHEET] 107
8159E–AVR–02/2013
has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the
dual-slope PWM modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter
is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count
direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct
PWM mode is shown on Figure 18-7. The TCNT2 value is in the timing diagram shown as a histogram for
illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal
line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2.
Figure 18-7. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can
be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the
COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be generated by setting the
COM21:0 to 3 (see Table 18-5 on page 113). The actual OC2 value will only be visible on the port pin if the data
direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2 Register
at the Compare Match between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the
OC2 Register at Compare Match between OCR2 and TCNT2 when the counter decrements. The PWM frequency
for the output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the output will be continuously low and if set
equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
TOVn Interrupt Flag Set
OCn Interrupt Flag Set
1 2 3
TCNTn
Period
OCn
OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
OCRn Update
f
OCnPCPWM
f
clk_I/O
N 510 = ------------------ATmega8A [DATASHEET] 108
8159E–AVR–02/2013
At the very start of period 2 in Figure 18-7 OCn has a transition from high to low even though there is no Compare
Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a
transition without Compare Match:
• OCR2A changes its value from MAX, like in Figure 18-7. When the OCR2A value is MAX the OCn pin value is
the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn
value at MAX must correspond to the result of an up-counting Compare Match.
• The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare
Match and hence the OCn change that would have happened on the way up.
18.8 Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clkT2) is therefore shown
as a clock enable signal. In Asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock.
The figures include information on when Interrupt Flags are set. Figure 18-8 contains timing data for basic
Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than
phase correct PWM mode.
Figure 18-8. Timer/Counter Timing Diagram, no Prescaling
Figure 18-9 shows the same timing data, but with the prescaler enabled.
Figure 18-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
Figure 18-10 shows the setting of OCF2 in all modes except CTC mode.
clkTn
(clkI/O/1)
TOVn
clkI/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)ATmega8A [DATASHEET] 109
8159E–AVR–02/2013
Figure 18-10. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8)
Figure 18-11 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.
Figure 18-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8)
18.9 Asynchronous Operation of the Timer/Counter
18.9.1 Asynchronous Operation of Timer/Counter2
When Timer/Counter2 operates asynchronously, some considerations must be taken.
• Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer
Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is:
1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2.
2. Select clock source by setting AS2 as appropriate.
3. Write new values to TCNT2, OCR2, and TCCR2.
4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB.
5. Clear the Timer/Counter2 Interrupt Flags.
6. Enable interrupts, if needed.
OCFn
OCRn
TCNTn
OCRn Value
OCRn - 1 OCRn OCRn + 1 OCRn + 2
clkI/O
clkTn
(clkI/O/8)
OCFn
OCRn
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)ATmega8A [DATASHEET] 110
8159E–AVR–02/2013
• The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin
may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be more than four times
the Oscillator frequency.
• When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register,
and latched after two positive edges on TOSC1. The user should not write a new value before the contents of
the temporary register have been transferred to its destination. Each of the three mentioned registers have their
individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2 write in
progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register
– ASSR has been implemented.
• When entering Power-save mode after having written to TCNT2, OCR2, or TCCR2, the user must wait until the
written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will
enter sleep mode before the changes are effective. This is particularly important if the Output Compare2
interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR2
or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to
zero, the device will never receive a Compare Match interrupt, and the MCU will not wake up.
• If Timer/Counter2 is used to wake the device up from Power-save mode, precautions must be taken if the user
wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time
between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the
device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save or Extended
Standby mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed:
1. Write a value to TCCR2, TCNT2, or OCR2.
2. Wait until the corresponding Update Busy Flag in ASSR returns to zero.
3. Enter Power-save or Extended Standby mode.
• When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always running,
except in Power-down and Standby modes. After a Power-up Reset or Wake-up from Power-down or Standby
mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The
user is advised to wait for at least one second before using Timer/Counter2 after Power-up or Wake-up from
Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a
wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the
Oscillator is in use or a clock signal is applied to the TOSC1 pin.
• Description of wake up from Power-save or Extended Standby mode when the timer is clocked asynchronously:
When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that
is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up,
the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction
following SLEEP.
• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since
TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register
synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When
waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the
previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after
waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The
recommended procedure for reading TCNT2 is thus as follows:
1. Write any value to either of the registers OCR2 or TCCR2.
2. Wait for the corresponding Update Busy Flag to be cleared.
3. Read TCNT2.
• During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes
three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the ATmega8A [DATASHEET] 111
8159E–AVR–02/2013
processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare Pin is
changed on the timer clock and is not synchronized to the processor clock.
18.10 Timer/Counter Prescaler
Figure 18-12. Prescaler for Timer/Counter2
The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock
clkI/O. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This
enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected
from Port B. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an
independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. Applying
an external clock source to TOSC1 is not recommended.
For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and
clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSR2 bit in SFIOR resets the prescaler.
This allows the user to operate with a predictable prescaler.
10-BIT T/C PRESCALER
TIMER/COUNTER2 CLOCK SOURCE
clkI/O clkT2S
TOSC1
AS2
CS20
CS21
CS22
clkT2S/8
clkT2S/64
clkT2S/128
clkT2S/1024
clkT2S/256
clkT2S/32
0 PSR2
Clear
clkT2ATmega8A [DATASHEET] 112
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18.11 Register Description
18.11.1 TCCR2 – Timer/Counter Control Register
• Bit 7 – FOC2: Force Output Compare
The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with
future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode. When writing a
logical one to the FOC2 bit, an immediate Compare Match is forced on the waveform generation unit. The OC2
output is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore
it is the value present in the COM21:0 bits that determines the effect of the forced compare.
A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2 as TOP.
The FOC2 bit is always read as zero.
• Bit 6,3 – WGM21:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and
what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal
mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See
Table 18-2 and “Modes of Operation” on page 104.
Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality
and location of these bits are compatible with previous versions of the timer.
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2
output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction
Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table
18-3 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM).
Bit 7 6 5 4 3 2 1 0
FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 TCCR2
Read/Write W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 18-2. Waveform Generation Mode Bit Description
Mode
WGM21
(CTC2)
WGM20
(PWM2)
Timer/Counter Mode of
Operation(1) TOP
Update of
OCR2
TOV2 Flag
Set
0 0 0 Normal 0xFF Immediate MAX
1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM
2 1 0 CTC OCR2 Immediate MAX
3 1 1 Fast PWM 0xFF BOTTOM MAX
Table 18-3. Compare Output Mode, Non-PWM Mode
COM21 COM20 Description
0 0 Normal port operation, OC2 disconnected.
0 1 Toggle OC2 on Compare Match
1 0 Clear OC2 on Compare Match
1 1 Set OC2 on Compare MatchATmega8A [DATASHEET] 113
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Table 18-4 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode.
Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but
the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 105 for more details.
Table 18-5 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode.
Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but
the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 106 for more details.
• Bit 2:0 – CS22:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Table 18-6.
18.11.2 TCNT2 – Timer/Counter Register
Table 18-4. Compare Output Mode, Fast PWM Mode(1)
COM21 COM20 Description
0 0 Normal port operation, OC2 disconnected.
0 1 Reserved
1 0 Clear OC2 on Compare Match, set OC2 at BOTTOM,
(non-inverting mode)
1 1 Set OC2 on Compare Match, clear OC2 at BOTTOM,
(inverting mode)
Table 18-5. Compare Output Mode, Phase Correct PWM Mode(1)
COM21 COM20 Description
0 0 Normal port operation, OC2 disconnected.
0 1 Reserved
1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match
when downcounting.
1 1 Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match
when downcounting.
Table 18-6. Clock Select Bit Description
CS22 CS21 CS20 Description
0 0 0 No clock source (Timer/Counter stopped).
0 0 1 clkT2S/(No prescaling)
0 1 0 clkT2S/8 (From prescaler)
0 1 1 clkT2S/32 (From prescaler)
1 0 0 clkT2S/64 (From prescaler)
1 0 1 clkT2S/128 (From prescaler)
1 1 0 clkT2S/256 (From prescaler)
1 1 1 clkT2S/1024 (From prescaler)
Bit 7 6 5 4 3 2 1 0
TCNT2[7:0] TCNT2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 114
8159E–AVR–02/2013
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit
counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying
the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between
TCNT2 and the OCR2 Register.
18.11.3 OCR2 – Output Compare Register
The Output Compare Register contains an 8-bit value that is continuously compared with the counter value
(TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC2 pin.
18.11.4 ASSR – Asynchronous Status Register
• Bit 3 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clkI/O. When AS2 is written to one,
Timer/Counter 2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the
value of AS2 is changed, the contents of TCNT2, OCR2, and TCCR2 might be corrupted.
• Bit 2 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that TCNT2 is ready to be updated with a new value.
• Bit 1 – OCR2UB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set. When OCR2 has been
updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that
OCR2 is ready to be updated with a new value.
• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set. When TCCR2 has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that TCCR2 is ready to be updated with a new value.
If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is set, the updated
value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer
value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is read.
Bit 7 6 5 4 3 2 1 0
OCR2[7:0] OCR2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
– – – – AS2 TCN2UB OCR2UB TCR2UB ASSR
Read/Write R R R R R/W R R R
Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 115
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18.11.5 TIMSK – Timer/Counter Interrupt Mask Register
• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare
Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter2 occurs
(i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR).
• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow
interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs (i.e., when
the TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR).
18.11.6 TIFR – Timer/Counter Interrupt Flag Register
• Bit 7 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 –
Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt Handling
Vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2
(Timer/Counter2 Compare Match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare Match
Interrupt is executed.
• Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing
the corresponding interrupt Handling Vector. Alternatively, TOV2 is cleared by writing a logic one to the flag.
When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the
Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting
direction at 0x00.
18.11.7 SFIOR – Special Function IO Register
• Bit 1 – PSR2: Prescaler Reset Timer/Counter2
When this bit is written to one, the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after
the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero if
Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in Asynchronous
mode, the bit will remain one until the prescaler has been reset.
Bit 7 6 5 4 3 2 1 0
OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 TIMSK
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 TIFR
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
– – – – ACME PUD PSR2 PSR10 SFIOR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 116
8159E–AVR–02/2013
19. Serial Peripheral Interface – SPI
19.1 Features • Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
19.2 Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8A and
peripheral devices or between several AVR devices.
Figure 19-1. SPI Block Diagram(1)
Note: 1. Refer to “Pin Configurations” on page 2, and Table 13-2 on page 56 for SPI pin placement.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 19-2. The system consists of two
Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low SPI2X SPI2X
DIVIDER
/2/4/8/16/32/64/128ATmega8A [DATASHEET] 117
8159E–AVR–02/2013
the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift
Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always
shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In –
Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave
Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by
user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the
SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator
stops, setting the end of Transmission Flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR
Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or
signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer
Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is
driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not
be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely
shifted, the end of Transmission Flag, SPIF is set. If the SPI interrupt enable bit, SPIE, in the SPCR
Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before
reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 19-2. SPI Master-Slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direction. This means that
bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When
receiving data, however, a received character must be read from the SPI Data Register before the next character
has been completely shifted in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of
the clock signal, the minimum low and high periods should be:
Low period: longer than 2 CPU clock cycles
High period: longer than 2 CPU clock cycles.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to
Table 19-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 54.
MSB MASTER LSB
8 BIT SHIFT REGISTER
MSB SLAVE LSB
8 BIT SHIFT REGISTER
MISO
MOSI
SPI
CLOCK GENERATOR
SCK
SS
MISO
MOSI
SCK
SS
VCC
SHIFT
ENABLEATmega8A [DATASHEET] 118
8159E–AVR–02/2013
Note: 1. See “Port B Pins Alternate Functions” on page 56 for a detailed description of how to define the direction of the
user defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins.
DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI
is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
Table 19-1. SPI Pin Overrides(1)
Pin Direction, Master SPI Direction, Slave SPI
MOSI User Defined Input
MISO Input User Defined
SCK User Defined Input
SS User Defined InputATmega8A [DATASHEET] 119
8159E–AVR–02/2013
Note: 1. See “About Code Examples” on page 6.
Assembly Code Example(1)
SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi r17,(1<>8);
UBRRL = (unsigned char)ubrr;
/* Enable receiver and transmitter */
UCSRB = (1<> 1) & 0x01;
return ((resh << 8) | resl);
}ATmega8A [DATASHEET] 137
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20.6.9 Receive Compete Flag and Interrupt
The USART Receiver has one flag that indicates the Receiver state.
The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one
when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any
unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC
bit will become zero.
When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete Interrupt
will be executed as long as the RXC Flag is set (provided that global interrupts are enabled). When interrupt-driven
data reception is used, the receive complete routine must read the received data from UDR in order to clear the
RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates.
20.6.10 Receiver Error Flags
The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity Error (PE). All can
be accessed by reading UCSRA. Common for the error flags is that they are located in the receive buffer together
with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRA must be
read before the receive buffer (UDR), since reading the UDR I/O location changes the buffer read location. Another
equality for the error flags is that they can not be altered by software doing a write to the flag location. However, all
flags must be set to zero when the UCSRA is written for upward compatibility of future USART implementations.
None of the error flags can generate interrupts.
The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable frame stored in the receive
buffer. The FE Flag is zero when the stop bit was correctly read (as one), and the FE Flag will be one when the
stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions
and protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRC since the Receiver
ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing
to UCSRA.
The Data OverRun (DOR) Flag indicates data loss due to a Receiver buffer full condition. A Data OverRun occurs
when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a
new start bit is detected. If the DOR Flag is set there was one or more serial frame lost between the frame last read
from UDR, and the next frame read from UDR. For compatibility with future devices, always write this bit to zero
when writing to UCSRA. The DOR Flag is cleared when the frame received was successfully moved from the Shift
Register to the receive buffer.
The Parity Error (PE) Flag indicates that the next frame in the receive buffer had a parity error when received. If
parity check is not enabled the PE bit will always be read zero. For compatibility with future devices, always set this
bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 130 and “Parity Checker”
on page 137.
20.6.11 Parity Checker
The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed
(odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the
data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the
check is stored in the receive buffer together with the received data and stop bits. The Parity Error (PE) Flag can
then be read by software to check if the frame had a parity error.
The PE bit is set if the next character that can be read from the receive buffer had a parity error when received and
the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read.
20.6.12 Disabling the Receiver
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore
be lost. When disabled (i.e., the RXEN is set to zero) the Receiver will no longer override the normal functionATmega8A [DATASHEET] 138
8159E–AVR–02/2013
of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the
buffer will be lost.
20.6.13 Flushing the Receive Buffer
The Receiver buffer FIFO will be flushed when the Receiver is disabled (i.e., the buffer will be emptied of its contents).
Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error
condition, read the UDR I/O location until the RXC Flag is cleared. The following code example shows how to flush
the receive buffer.
Note: 1. See “About Code Examples” on page 6.
20.7 Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The
clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous
serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby
improving the noise immunity of the Receiver. The asynchronous reception operational range depends on the
accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
20.7.1 Asynchronous Clock Recovery
The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 20-5 illustrates the sampling
process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and
eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation
due to the sampling process. Note the larger time variation when using the Double Speed mode (U2X = 1) of operation.
Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity).
Figure 20-5. Start Bit Sampling
When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection
sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The clock recovery logic
Assembly Code Example(1)
USART_Flush:
sbis UCSRA, RXC
ret
in r16, UDR
rjmp USART_Flush
C Code Example(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRA & (1< 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck 12MHz
High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck 12MHz
25.9.1 Serial Programming Algorithm
When writing serial data to the ATmega8A, data is clocked on the rising edge of SCK.
When reading data from the ATmega8A, data is clocked on the falling edge of SCK. See Figure 25-8 for timing
details.
Table 25-14. Pin Mapping Serial Programming
Symbol Pins I/O Description
MOSI PB3 I Serial data in
MISO PB4 O Serial data out
SCK PB5 I Serial clock
VCC
GND
XTAL1
SCK
MISO
MOSI
RESET
PB3
PB4
PB5
+2.7 - 5.5V
AVCC
+2.7 - 5.5V (2)ATmega8A [DATASHEET] 221
8159E–AVR–02/2013
To program and verify the ATmega8A in the Serial Programming mode, the following sequence is recommended
(See four byte instruction formats in Table 25-16):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer
can not guarantee that SCK is held low during Power-up. In this case, RESET must be given a
positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.
2. Wait for at least 20 ms and enable Serial Programming by sending the Programming Enable serial instruction
to pin MOSI.
3. The Serial Programming instructions will not work if the communication is out of synchronization. When in
sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable
instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the
0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The page size is found in Table 25-5 on page 210. The
memory page is loaded one byte at a time by supplying the 5LSB of the address and data together with
the Load Program memory Page instruction. To ensure correct loading of the page, the data Low byte
must be loaded before data High byte is applied for a given address. The Program memory Page is stored
by loading the Write Program memory Page instruction with the 7 MSB of the address. If polling is not
used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 25-15).
5. Note: If other commands than polling (read) are applied before any write operation (FLASH, EEPROM,
Lock Bits, Fuses) is completed, it may result in incorrect programming.
6. The EEPROM array is programmed one byte at a time by supplying the address and data together with
the appropriate Write instruction. An EEPROM memory location is first automatically erased before new
data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte.
(See Table 25-15 on page 222). In a chip erased device, no 0xFFs in the data file(s) need to be
programmed.
7. Any memory location can be verified by using the Read instruction which returns the content at the
selected address at serial output MISO.
8. At the end of the programming session, RESET can be set high to commence normal operation.
9. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off
25.9.2 Data Polling Flash
When a page is being programmed into the Flash, reading an address location within the page being programmed
will give the value 0xFF. At the time the device is ready for a new page, the programmed value will read correctly.
This is used to determine when the next page can be written. Note that the entire page is written simultaneously
and any address within the page can be used for polling. Data polling of the Flash will not work for the value 0xFF,
so when programming this value, the user will have to wait for at least tWD_FLASH before programming the next
page. As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain
0xFF, can be skipped. See Table 97 for tWD_FLASH value.
25.9.3 Data Polling EEPROM
When a new byte has been written and is being programmed into EEPROM, reading the address location being
programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will
read correctly. This is used to determine when the next byte can be written. This will not work for the value 0xFF,
but the user should have the following in mind: As a chip-erased device contains 0xFF in all locations, programming
of addresses that are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is Re-ATmega8A [DATASHEET] 222
8159E–AVR–02/2013
programmed without chip-erasing the device. In this case, data polling cannot be used for the value 0xFF, and the
user will have to wait at least tWD_EEPROM before programming the next byte. See Table 25-15 for tWD_EEPROM value.
Figure 25-8. Serial Programming Waveforms
Table 25-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
tWD_FUSE 4.5 ms
tWD_FLASH 4.5 ms
tWD_EEPROM 9.0 ms
tWD_ERASE 9.0 ms
MSB
MSB
LSB
LSB
SERIAL CLOCK INPUT
(SCK)
SERIAL DATA INPUT
(MOSI)
(MISO)
SAMPLE
SERIAL DATA OUTPUTATmega8A [DATASHEET] 223
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Note: a = address high bits
b = address low bits
H = 0 – Low byte, 1 – High byte
o = data out
i = data in
x = don’t care
Table 25-16. Serial Programming Instruction Set
Instruction
Instruction Format
Byte 1 Byte 2 Byte 3 Byte4 Operation
Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after
RESET goes low.
Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.
Read Program Memory 0010 H000 0000 aaaa bbbb bbbb oooo oooo Read H (high or low) data o from
Program memory at word address
a:b.
Load Program Memory
Page
0100 H000 0000 xxxx xxxb bbbb iiii iiii Write H (high or low) data i to
Program memory page at word
address b. Data Low byte must be
loaded before Data High byte is
applied within the same address.
Write Program Memory
Page
0100 1100 0000 aaaa bbbx xxxx xxxx xxxx Write Program memory Page at
address a:b.
Read EEPROM Memory 1010 0000 00xx xxxa bbbb bbbb oooo oooo Read data o from EEPROM
memory at address a:b.
Write EEPROM Memory 1100 0000 00xx xxxa bbbb bbbb iiii iiii Write data i to EEPROM memory
at address a:b.
Read Lock Bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock Bits. “0” = programmed,
“1” = unprogrammed. See Table
25-1 on page 207 for details.
Write Lock Bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock Bits. Set bits = “0” to
program Lock Bits. See Table 25-
1 on page 207 for details.
Read Signature Byte 0011 0000 00xx xxxx xxxx xxbb oooo oooo Read Signature Byte o at address
b.
Write Fuse Bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to
unprogram. See Table 25-4 on
page 209 for details.
Write Fuse High Bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to
unprogram. See Table 25-3 on
page 208 for details.
Read Fuse Bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse Bits. “0” = programmed,
“1” = unprogrammed. See Table
25-4 on page 209 for details.
Read Fuse High Bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse high bits. “0” = programmed,
“1” = unprogrammed.
See Table 25-3 on page 208 for
details.
Read Calibration Byte 0011 1000 00xx xxxx 0000 00bb oooo oooo Read Calibration ByteATmega8A [DATASHEET] 224
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25.9.4 SPI Serial Programming Characteristics
For characteristics of the SPI module, see “SPI Timing Characteristics” on page 230.ATmega8A [DATASHEET] 225
8159E–AVR–02/2013
26. Electrical Characteristics – TA = -40°C to 85°C
Note: Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured
on the same process technology. Min and Max values will be available after the device is characterized.
26.2 DC Characteristics
26.1 Absolute Maximum Ratings*
Operating Temperature.................................. -55C to +125C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground ................................-0.5V to VCC+0.5V
Voltage on RESET with respect to Ground......-0.5V to +13.0V
Maximum Operating Voltage ............................................ 6.0V
DC Current per I/O Pin ................................................ 40.0mA
DC Current VCC and GND Pins................................. 300.0mA
TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted)
Symbol Parameter Condition Min Typ Max Units
VIL
Input Low Voltage except
XTAL1 and RESET pins VCC = 2.7V - 5.5V -0.5 0.2 VCC(1) V
VIH
Input High Voltage except
XTAL1 and RESET pins VCC = 2.7V - 5.5V 0.6 VCC(2) VCC + 0.5 V
VIL1
Input Low Voltage
XTAL1 pin
VCC = 2.7V - 5.5V -0.5 0.1 VCC(1) V
VIH1
Input High Voltage
XTAL 1 pin
VCC = 2.7V - 5.5V 0.8 VCC(2) VCC + 0.5 V
VIL2
Input Low Voltage
RESET pin
VCC = 2.7V - 5.5V -0.5 0.2 VCC V
VIH2
Input High Voltage
RESET pin
VCC = 2.7V - 5.5V 0.9 VCC(2) VCC + 0.5 V
VIL3
Input Low Voltage
RESET pin as I/O VCC = 2.7V - 5.5V -0.5 0.2 VCC V
VIH3
Input High Voltage
RESET pin as I/O VCC = 2.7V - 5.5V 0.6 VCC(2)
0.7 VCC(2) VCC + 0.5 V
VOL
Output Low Voltage(3)
(Ports B,C,D)
I
OL = 20mA, VCC = 5V
IOL = 10mA, VCC = 3V
0.9
0.6
V
V
VOH
Output High Voltage(4)
(Ports B,C,D)
I
OH = -20mA, VCC = 5V
IOH = -10mA, VCC = 3V
4.2
2.2
V
V
IIL
Input Leakage
Current I/O Pin
Vcc = 5.5V, pin low
(absolute value) 1 µA
IIH
Input Leakage
Current I/O Pin
Vcc = 5.5V, pin high
(absolute value) 1 µAATmega8A [DATASHEET] 226
8159E–AVR–02/2013
Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low
2. “Min” means the lowest value where the pin is guaranteed to be read as high
3. Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state
conditions (non-transient), the following must be observed:
PDIP, TQFP, and QFN/MLF Package:
1] The sum of all IOL, for all ports, should not exceed 300mA.
2] The sum of all IOL, for ports C0 - C5 should not exceed 100mA.
3] The sum of all IOL, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
4. Although each I/O port can source more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state
conditions (non-transient), the following must be observed:
PDIP, TQFP, and QFN/MLF Package:
1] The sum of all IOH, for all ports, should not exceed 300mA.
2] The sum of all IOH, for port C0 - C5, should not exceed 100mA.
3] The sum of all IOH, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
5. Minimum VCC for Power-down is 2.5V.
RRST Reset Pull-up Resistor 30 80 k
Rpu I/O Pin Pull-up Resistor 20 50 k
I
CC
Power Supply Current
Active 4MHz, VCC = 3V 2 5 mA
Active 8MHz, VCC = 5V 6 15 mA
Idle 4MHz, VCC = 3V 0.5 2 mA
Idle 8MHz, VCC = 5V 2.2 7 mA
Power-down mode(5) WDT enabled, VCC = 3V <10 28 µA
WDT disabled, VCC = 3V <1 3 µA
VACIO
Analog Comparator
Input Offset Voltage
VCC = 5V
Vin = VCC/2 40 mV
IACLK
Analog Comparator
Input Leakage Current
VCC = 5V
Vin = VCC/2 -50 50 nA
tACPD
Analog Comparator
Propagation Delay
VCC = 2.7V
VCC = 5.0V
750
500 ns
TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued)
Symbol Parameter Condition Min Typ Max UnitsATmega8A [DATASHEET] 227
8159E–AVR–02/2013
26.3 Speed Grades
Figure 26-1. Maximum Frequency vs. Vcc
26.4 Clock Characteristics
26.4.1 External Clock Drive Waveforms
Figure 26-2. External Clock Drive Waveforms
26.4.2 External Clock Drive
2.7V 4.5V 5.5V
Safe Operating Area
16 MHz
8 MHz
VIL1
VIH1
Table 26-1. External Clock Drive
Symbol Parameter
VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V
Min Max Min Max Units
1/tCLCL Oscillator Frequency 0 8 0 16 MHz
tCLCL Clock Period 125 62.5 ns
tCHCX High Time 50 25 ns
tCLCX Low Time 50 25 ns
tCLCH Rise Time 1.6 0.5 s
tCHCL Fall Time 1.6 0.5 s
tCLCL
Change in period from one
clock cycle to the next 2 2%ATmega8A [DATASHEET] 228
8159E–AVR–02/2013
Notes: 1. R should be in the range 3 k - 100 k, and C should be at least 20 pF. The C values given in the table includes pin
capacitance. This will vary with package type.
2. The frequency will vary with package type and board layout.
26.5 System and Reset Characteristics
Notes: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling).
2. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the
device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur
before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is
performed using BODLEVEL = 1 and BODLEVEL = 0 for ATmega8A.
Table 26-2. External RC Oscillator, Typical Frequencies
R [k]
(1) C [pF] f(2)
33 22 650kHz
10 22 2.0MHz
Table 26-3. Reset, Brown-out and Internal Voltage Reference Characteristics
Symbol Parameter Condition Min Typ Max Units
VPOT
Power-on Reset Threshold Voltage
(rising)(1) 1.4 2.3 V
Power-on Reset Threshold Voltage
(falling) 1.3 2.3 V
VRST RESET Pin Threshold Voltage 0.2 0.9 VCC
tRST Minimum pulse width on RESET Pin 1.5 µs
VBOT
Brown-out Reset Threshold Voltage(2) BODLEVEL = 1 2.40 2.60 2.90
V
BODLEVEL = 0 3.70 4.00 4.50
tBOD
Minimum low voltage period for Brownout
Detection
BODLEVEL = 1 2 µs
BODLEVEL = 0 2 µs
VHYST Brown-out Detector hysteresis 130 mV
VBG Bandgap reference voltage 1.15 1.23 1.35 V
tBG Bandgap reference start-up time 40 70 µs
IBG Bandgap reference current consumption 10 µsATmega8A [DATASHEET] 229
8159E–AVR–02/2013
26.6 Two-wire Serial Interface Characteristics
Table 26-4 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8A Two-wire Serial
Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 26-3.
Notes: 1. In ATmega8A, this parameter is characterized and not 100% tested.
2. Required only for fSCL > 100kHz.
Table 26-4. Two-wire Serial Bus Requirements
Symbol Parameter Condition Min Max Units
VIL Input Low-voltage -0.5 0.3 VCC V
VIH Input High-voltage 0.7 VCC VCC + 0.5 V
Vhys(1) Hysteresis of Schmitt Trigger Inputs 0.05 VCC(2) – V
VOL(1) Output Low-voltage 3mA sink current 0 0.4 V
tr
(1) Rise Time for both SDA and SCL 20 + 0.1Cb
(3)(2) 300 ns
tof
(1) Output Fall Time from VIHmin to VILmax 10 pF < Cb < 400 pF(3) 20 + 0.1Cb
(3)(2) 250 ns
tSP(1) Spikes Suppressed by Input Filter 0 50(2) ns
Ii Input Current each I/O Pin 0.1VCC < Vi
< 0.9VCC -10 10 µA
Ci
(1) Capacitance for each I/O Pin – 10 pF
fSCL SCL Clock Frequency fCK(4) > max(16fSCL, 250kHz)(5) 0 400 kHz
Rp Value of Pull-up resistor
fSCL 100kHz
fSCL > 100kHz
tHD;STA Hold Time (repeated) START Condition
fSCL 100kHz 4.0 – µs
fSCL > 100kHz 0.6 – µs
tLOW Low Period of the SCL Clock
fSCL 100kHz(6) 4.7 – µs
fSCL > 100kHz(7) 1.3 – µs
tHIGH High period of the SCL clock
fSCL 100kHz 4.0 – µs
fSCL > 100kHz 0.6 – µs
tSU;STA Set-up time for a repeated START condition
fSCL 100kHz 4.7 – µs
fSCL > 100kHz 0.6 – µs
tHD;DAT Data hold time
fSCL 100kHz 0 3.45 µs
fSCL > 100kHz 0 0.9 µs
tSU;DAT Data setup time
fSCL 100kHz 250 – ns
fSCL > 100kHz 100 – ns
tSU;STO Setup time for STOP condition
fSCL 100kHz 4.0 – µs
fSCL > 100kHz 0.6 – µs
tBUF
Bus free time between a STOP and START
condition
fSCL 100kHz 4.7 – µs
fSCL > 100kHz 1.3 – µs
VCC – 0,4V
3mA ---------------------------- 1000ns
Cb
-------------------
VCC – 0,4V
3mA ---------------------------- 300ns
Cb
---------------- ATmega8A [DATASHEET] 230
8159E–AVR–02/2013
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATmega8A Two-wire Serial Interface operation. Other devices connected to the Two-wire
Serial Bus need only obey the general fSCL requirement.
6. The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than
6MHz for the low time requirement to be strictly met at fSCL = 100kHz.
7. The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement
will not be strictly met for fSCL > 308kHz when fCK = 8MHz. Still, ATmega8A devices connected to the bus may communicate
at full speed (400kHz) with other ATmega8A devices, as well as any other device with a proper tLOW acceptance margin.
Figure 26-3. Two-wire Serial Bus Timing
26.7 SPI Timing Characteristics
See Figure 26-4 and Figure 26-5 for details.
Note: 1. In SPI Programming mode the minimum SCK high/low period is:
- 2tCLCL for fCK < 12MHz
- 3tCLCL for fCK > 12MHz
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA t
HD;DAT t
SU;DAT t
SU;STO
t
BUF
SCL
SDA
t
r
Table 26-5. SPI Timing Parameters
Description Mode Min Typ Max
1 SCK period Master See Table 19-4
ns
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 • tSCK
7 SCK to out Master 10
8 SCK to out high Master 10
9 SS low to out Slave 15
10 SCK period Slave 4 • tck
11 SCK high/low(1) Slave 2 • tck
12 Rise/Fall time Slave 1.6
13 Setup Slave 10
14 Hold Slave 10
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS high to tri-state Slave 10
18 SS low to SCK Salve 2 • tckATmega8A [DATASHEET] 231
8159E–AVR–02/2013
Figure 26-4. SPI interface timing requirements (Master Mode)
Figure 26-5. SPI interface timing requirements (Slave Mode)
MOSI
(Data Output)
SCK
(CPOL = 1)
MISO
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
MSB LSB
...
...
6 1
2 2
4 5 3
7 8
MISO
(Data Output)
SCK
(CPOL = 1)
MOSI
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
MSB LSB
...
...
10
11 11
13 14 12
15 17
9
X
16
18ATmega8A [DATASHEET] 232
8159E–AVR–02/2013
26.8 ADC Characteristics
Notes: 1. Values are guidelines only.
2. Minimum for AVCC is 2.7V.
3. Maximum for AVCC is 5.5V.
4. Maximum conversion time is 1/50kHz*25 = 0.5 ms.
Table 26-6. ADC Characteristics
Symbol Parameter Condition Min(1) Typ(1) Max(1) Units
Resolution Single Ended Conversion 10 Bits
Absolute accuracy
(Including INL, DNL,
Quantization Error, Gain,
and Offset Error)
Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200kHz
1.75 LSB
Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 1MHz
3 LSB
Integral Non-linearity (INL)
Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200kHz 0.75 LSB
Differential Non-linearity
(DNL)
Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200kHz 0.5 LSB
Gain Error Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200kHz
1 LSB
Offset Error Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200kHz
1 LSB
Conversion Time(4) Free Running Conversion 13 260 µs
Clock Frequency 50 1000 kHz
AVCC Analog Supply Voltage VCC - 0.3(2) VCC + 0.3(3) V
VREF Reference Voltage 2.0 AVCC V
VIN Input voltage GND VREF V
Input bandwidth 38.5 kHz
VINT Internal Voltage Reference 2.3 2.56 2.8 V
RREF Reference Input Resistance 32 k
RAIN Analog Input Resistance 55 100 MATmega8A [DATASHEET] 233
8159E–AVR–02/2013
27. Electrical Characteristics – TA = -40°C to 105°C
Absolute Maximum Ratings*
27.1 DC Characteristics
Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low
Operating Temperature.................................. -55C to +125C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground ................................-0.5V to VCC+0.5V
Voltage on RESET with respect to Ground......-0.5V to +13.0V
Maximum Operating Voltage ............................................ 6.0V
DC Current per I/O Pin ............................................... 40.0 mA
DC Current VCC and GND Pins................................ 200.0 mA
TA = -40C to 105C, VCC = 2.7V to 5.5V (unless otherwise noted)
Symbol Parameter Condition Min. Typ. Max. Units
VIL
Input Low Voltage, Except
XTAL1 and RESET pin VCC = 2.7V - 5.5V -0.5 0.2VCC(1) V
VIL1
Input Low Voltage,
XTAL1 pin VCC = 2.7V - 5.5V -0.5 0.1VCC(1) V
VIL2
Input Low Voltage,
RESET pin VCC = 2.7V - 5.5V -0.5 0.1VCC(1) V
VIH
Input High Voltage,
Except XTAL1 and
RESET pins
VCC = 2.7V - 5.5V 0.6VCC(2) VCC + 0.5 V
VIH1
Input High Voltage,
XTAL1 pin VCC = 2.7V - 5.5V 0.8VCC(2) VCC + 0.5 V
VIH2
Input High Voltage,
RESET pin VCC = 2.7V - 5.5V 0.9VCC(2) VCC + 0.5 V
VOL
Output Low Voltage(3),
Port B (except RESET)
I
OL =20 mA, VCC = 5V
IOL =10 mA, VCC = 3V
0.8
0.6 V
VOH
Output High Voltage(4),
Port B (except RESET)
I
OH = -20 mA, VCC = 5V
IOH = -10 mA, VCC = 3V
4.0
2.2 V
IIL
Input Leakage
Current I/O Pin 3 µA
IIH
Input Leakage
Current I/O Pin 3 µA
RRST Reset Pull-up Resistor 30 80 k
RPU I/O Pin Pull-up Resistor 20 50 k
VACIO
Analog Comparator
Input Offset Voltage
VCC = 5V
Vin = VCC/2 20 mV
IACLK
Analog Comparator
Input Leakage Current
VCC = 5V
Vin = VCC/2 -50 50 nAATmega8A [DATASHEET] 234
8159E–AVR–02/2013
2. “Min” means the lowest value where the pin is guaranteed to be read as high
3. Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state
conditions (non-transient), the following must be observed:
PDIP, TQFP, and QFN/MLF Package:
1] The sum of all IOL, for all ports, should not exceed 300 mA.
2] The sum of all IOL, for ports C0 - C5 should not exceed 100 mA.
3] The sum of all IOL, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
4. Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state
conditions (non-transient), the following must be observed:
PDIP, TQFP, and QFN/MLF Package:
1] The sum of all IOH, for all ports, should not exceed 300 mA.
2] The sum of all IOH, for port C0 - C5, should not exceed 100 mA.
3] The sum of all IOH, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
Note: 1. The current consumption values include input leakage current.
27.1.1 ATmega8A DC Characteristics
Table 27-1. TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted)
Symbol Parameter Condition Min. Typ. Max. Units
ICC
Power Supply Current
Active 4 MHz, VCC = 3V 6 mA
Active 8 MHz, VCC = 5V 15 mA
Idle 4 MHz, VCC = 3V 3 mA
Idle 8 MHz, VCC = 5V 8 mA
Power-down mode(1) WDT enabled, VCC = 3V 35 µA
WDT disabled, VCC = 3V 6 µAATmega8A [DATASHEET] 235
8159E–AVR–02/2013
28. Typical Characteristics – TA = -40°C to 85°C
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption
measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A
sine wave generator with Rail-to-Rail output is used as clock source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of
I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating
voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance,
VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at
frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down
mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.
28.1 Active Supply Current
Figure 28-1. Active Supply Current vs. Frequency (0.1 - 1.0MHz)
5.5 V
5.0 V
4.5 V
4.0 V
3.6 V
3.3 V
2.7 V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
ICC (mA)ATmega8A [DATASHEET] 236
8159E–AVR–02/2013
Figure 28-2. Active Supply Current vs. Frequency (1 - 16MHz)
Figure 28-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
0
2
4
6
8
10
12
14
0246 8 10 12 14 16
Frequency (MHz)
ICC (mA)
5.5 V
5.0 V
4.5 V
4.0 V
3.6 V
3.3 V
2.7 V
85 °C
25 °C
-40 °C
3
4
5
6
7
8
9
10
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (mA)ATmega8A [DATASHEET] 237
8159E–AVR–02/2013
Figure 28-4. Active Supply Current vs. VCC (Internal RC Oscillator, 4MHz)
Figure 28-5. Active Supply Current vs. VCC (Internal RC Oscillator, 2MHz)
85 °C
25 °C
-40 °C
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (mA)
85 °C
25 °C
-40 °C
1.2
1.6
2
2.4
2.8
3.2
3.6
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (mA)ATmega8A [DATASHEET] 238
8159E–AVR–02/2013
Figure 28-6. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
Figure 28-7. Active Supply Current vs. VCC (32kHz External Oscillator)
85 °C
25 °C
-40 °C
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (mA)
25 °C
40
45
50
55
60
65
70
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (µA)ATmega8A [DATASHEET] 239
8159E–AVR–02/2013
28.2 Idle Supply Current
Figure 28-8. Idle Supply Current vs. Frequency (0.1 - 1.0MHz)
Figure 28-9. Idle Supply Current vs. Frequency (1 - 16MHz)
5.5 V
5.0 V
4.5 V
4.0 V
3.6 V
3.3 V
2.7 V
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
ICC (mA)
5.5 V
5.0 V
4.5 V
4.0 V
3.6 V
3.3 V
2.7 V
0
1
2
3
4
5
6
0246 8 10 12 14 16
Frequency (MHz)
ICC (mA)ATmega8A [DATASHEET] 240
8159E–AVR–02/2013
Figure 28-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
Figure 28-11. Idle Supply Current vs. VCC (Internal RC Oscillator, 4MHz)
85 °C
25 °C
-40 °C
1
1.5
2
2.5
3
3.5
4
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (mA)
85 °C
25 °C
-40 °C
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (mA)ATmega8A [DATASHEET] 241
8159E–AVR–02/2013
Figure 28-12. Idle Supply Current vs. VCC (Internal RC Oscillator, 2MHz)
Figure 28-13. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (mA)
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (mA)ATmega8A [DATASHEET] 242
8159E–AVR–02/2013
Figure 28-14. Idle Supply Current vs. VCC (32kHz External Oscillator)
28.3 Power-down Supply Current
Figure 28-15. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)
25 °C
0
5
10
15
20
25
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)ATmega8A [DATASHEET] 243
8159E–AVR–02/2013
Figure 28-16. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)
28.4 Power-save Supply Current
Figure 28-17. Power-save Supply Current vs. VCC (Watchdog Timer Disabled)
85 °C
25 °C
-40 °C
0
5
10
15
20
25
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)
25 °C
2
4
6
8
10
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)ATmega8A [DATASHEET] 244
8159E–AVR–02/2013
28.5 Standby Supply Current
Figure 28-18. Standby Supply Current vs. VCC (455kHz Resonator, Watchdog Timer Disabled)
Figure 28-19. Standby Supply Current vs. VCC (1MHz Resonator, Watchdog Timer Disabled)
25 °C
0
10
20
30
40
50
60
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)
25 °C
0
10
20
30
40
50
60
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)ATmega8A [DATASHEET] 245
8159E–AVR–02/2013
Figure 28-20. Standby Supply Current vs. VCC (1MHz Xtal, Watchdog Timer Disabled)
Figure 28-21. Standby Supply Current vs. VCC (4MHz Resonator, Watchdog Timer Disabled)
25 °C
0
10
20
30
40
50
60
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)
25 °C
0
15
30
45
60
75
90
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)ATmega8A [DATASHEET] 246
8159E–AVR–02/2013
Figure 28-22. Standby Supply Current vs. VCC (4MHz Xtal, Watchdog Timer Disabled)
Figure 28-23. Standby Supply Current vs. VCC (6MHz Resonator, Watchdog Timer Disabled)
25 °C
0
10
20
30
40
50
60
70
80
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)
25 °C
0
20
40
60
80
100
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)ATmega8A [DATASHEET] 247
8159E–AVR–02/2013
Figure 28-24. Standby Supply Current vs. VCC (6MHz Xtal, Watchdog Timer Disabled)
28.6 Pin Pull-up
Figure 28-25. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
25 °C
0
20
40
60
80
100
120
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)
0
20
40
60
80
100
120
140
0123456
VOP (V)
IOP (uA)
85 °C
25 °C
-40 °CATmega8A [DATASHEET] 248
8159E–AVR–02/2013
Figure 28-26. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
Figure 28-27. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
70
80
0 0.5 1 1.5 2 2.5 3
VOP (V)
IOP (uA)
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
012345
VRESET (V)
IRESET (uA)ATmega8A [DATASHEET] 249
8159E–AVR–02/2013
Figure 28-28. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
28.7 Pin Driver Strength
Figure 28-29. I/O Pin Output Voltage vs. Source Current (VCC = 5.0V)
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
0 0.5 1 1.5 2 2.5 3
VRESET (V)
IRESET (uA)
85 °C
25 °C
-40 °C
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5
0246 8 10 12 14 16 18 20
IOH (mA)
VOH (
V)ATmega8A [DATASHEET] 250
8159E–AVR–02/2013
Figure 28-30. I/O Pin Output Voltage vs. Source Current (VCC = 3.0V)
Figure 28-31. I/O Pin Output Voltage vs. Sink Current (VCC = 5.0V)
85 °C
25 °C
-40 °C
1
1.5
2
2.5
3
3.5
0 4 8 12 16 20
IOH (mA)
VOH (
V)
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
0.6
0 4 8 12 16 20
IOL (mA)
VOL (
V)ATmega8A [DATASHEET] 251
8159E–AVR–02/2013
Figure 28-32. I/O Pin Output Voltage vs. Sink Current (VCC = 3.0V)
Figure 28-33. Reset Pin as I/O - Pin Source Current vs. Output Voltage (VCC = 5.0V)
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
0246 8 10 12 14 16 18 20
IOL (mA)
VOL (
V)
0
1
2
3
4
5
2 2.5 3 3.5 4 4.5
VOH (V)
Current (mA)
85 °C
25 °C
-40 °CATmega8A [DATASHEET] 252
8159E–AVR–02/2013
Figure 28-34. Reset Pin as I/O - Pin Source Current vs. Output Voltage (VCC = 2.7V)
Figure 28-35. Reset Pin as I/O - Pin Sink Current vs. Output Voltage (VCC = 5.0V)
0
0.5
1
1.5
2
2.5
3
3.5
4
0 0.5 1 1.5 2 2.5
VOH (V)
Current (mA)
85 °C
25 °C
-40 °C
85 °C
25 °C
-40 °C
0
2
4
6
8
10
12
14
0 0.5 1 1.5 2
VOL (V)
Current (mA)ATmega8A [DATASHEET] 253
8159E–AVR–02/2013
Figure 28-36. Reset Pin as I/O - Pin Sink Current vs. Output Voltage (VCC = 2.7V)
28.8 Pin Thresholds and Hysteresis
Figure 28-37. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”)
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0 0.5 1 1.5 2
VOL (V)
Current (mA)
85 °C
25 °C
-40 °C
1
1.5
2
2.5
3
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Threshold (
V)ATmega8A [DATASHEET] 254
8159E–AVR–02/2013
Figure 28-38. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”)
Figure 28-39. I/O Pin Input Hysteresis vs. VCC
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Threshold (
V)
85 °C
25 °C
-40 °C
0.2
0.25
0.3
0.35
0.4
0.45
0.5
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Input Hysteresis (m
V)ATmega8A [DATASHEET] 255
8159E–AVR–02/2013
Figure 28-40. Reset Pin as I/O - Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”)
Figure 28-41. Reset Pin as I/O - Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”)
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Threshold (
V)
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Threshold (
V)ATmega8A [DATASHEET] 256
8159E–AVR–02/2013
Figure 28-42. Reset Pin as I/O - Pin Hysteresis vs. VCC
Figure 28-43. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”)
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Input Hysteresis (m
V)
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Threshold (
V)ATmega8A [DATASHEET] 257
8159E–AVR–02/2013
Figure 28-44. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”)
Figure 28-45. Reset Input Pin Hysteresis vs. VCC
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Threshold (
V)
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Input Hysteresis (m
V)ATmega8A [DATASHEET] 258
8159E–AVR–02/2013
28.9 Bod Thresholds and Analog Comparator Offset
Figure 28-46. BOD Thresholds vs. Temperature (BOD Level is 4.0V)
Figure 28-47. BOD Thresholds vs. Temperature (BOD Level is 2.7v)
3.7
3.75
3.8
3.85
3.9
3.95
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Threshold (
V)
Rising Vcc
Falling Vcc
Temperature (°C)
2.5
2.55
2.6
2.65
2.7
2.75
2.8
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)
Threshold (
V)
Rising Vcc
Falling VccATmega8A [DATASHEET] 259
8159E–AVR–02/2013
Figure 28-48. Bandgap Voltage vs. VCC
Figure 28-49. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V)
85 °C
25 °C
-40 °C
1.18
1.185
1.19
1.195
1.2
1.205
1.21
1.215
2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Bandgap
Voltage (
V) Comparator Offset Voltage (V)
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Common Mode Voltage (V)
85 °C
25 °C
-40 °C
-0.004
-0.003
-0.002
-0.001
0
0.001
0.002
0.003ATmega8A [DATASHEET] 260
8159E–AVR–02/2013
Figure 28-50. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.8V)
28.10 Internal Oscillator Speed
Figure 28-51. Watchdog Oscillator Frequency vs. VCC
-0.004
-0.003
-0.002
-0.001
0
0.001
0.002
0.003
0.25 0.50 0.75 1.00 1.25 1.5 1.75 2.00 2.25 2.75
Common Mode Voltage (V)
2.50
Comparator Offset Voltage (V)
85 °C
25 °C
-40 °C
85 °C
25 °C
-40 °C
925
950
975
1000
1025
1050
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
FRC (kHz)ATmega8A [DATASHEET] 261
8159E–AVR–02/2013
Figure 28-52. Calibrated 8MHz RC Oscillator Frequency vs. Temperature
Figure 28-53. Calibrated 8MHz RC Oscillator Frequency vs. VCC
5.5 V
4.0 V
2.7 V
6
6,5
7
7,5
8
8,5
-40 -20 0 20 40 60 80 100
Temperature (°C)
FRC (MHz)
85 °C
25 °C
-40 °C
6
6.5
7
7.5
8
8.5
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
FRC (MHz)ATmega8A [DATASHEET] 262
8159E–AVR–02/2013
Figure 28-54. Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value
Figure 28-55. Calibrated 4MHz RC Oscillator Frequency vs. Temperature
25 °C
2
4
6
8
10
12
14
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL VALUE
FRC (MHz)
5.5 V
4.0 V
2.7 V
3.5
3.6
3.7
3.8
3.9
4
4.1
-40 -20 0 20 40 60 80 100
FRC (MHz)
Temperature (°C)ATmega8A [DATASHEET] 263
8159E–AVR–02/2013
Figure 28-56. Calibrated 4MHz RC Oscillator Frequency vs. VCC
Figure 28-57. Calibrated 4MHz RC Oscillator Frequency vs. Osccal Value
85 °C
25 °C
-40 °C
3.5
3.6
3.7
3.8
3.9
4
4.1
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
FRC (MHz)
25 °C
1
2
3
4
5
6
7
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL VALUE
FRC (MHz)ATmega8A [DATASHEET] 264
8159E–AVR–02/2013
Figure 28-58. Calibrated 2MHz RC Oscillator Frequency vs. Temperature
Figure 28-59. Calibrated 2MHz RC Oscillator Frequency vs. VCC
5.5 V
4.0 V
2.7 V
1.75
1.8
1.85
1.9
1.95
2
2.05
2.1
-40 -20 0 20 40 60 80 100
FRC (MHz)
Temperature (°C)
85 °C
25 °C
-40 °C
1.8
1.85
1.9
1.95
2
2.05
2.1
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
FRC (MHz)ATmega8A [DATASHEET] 265
8159E–AVR–02/2013
Figure 28-60. Calibrated 2MHz RC Oscillator Frequency vs. Osccal Value
Figure 28-61. Calibrated 1MHz RC Oscillator Frequency vs. Temperature
25 °C
0.5
1
1.5
2
2.5
3
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL VALUE
FRC (MHz)
5.5 V
4.0 V
2.7 V
0.9
0.92
0.94
0.96
0.98
1
1.02
1.04
-40 -20 0 20 40 60 80 100
FRC (MHz)
Temperature (°C)ATmega8A [DATASHEET] 266
8159E–AVR–02/2013
Figure 28-62. Calibrated 1MHz RC Oscillator Frequency vs. VCC
Figure 28-63. Calibrated 1MHz RC Oscillator Frequency vs. Osccal Value
85 °C
25 °C
-40 °C
0,9
0.92
0.94
0.96
0.98
1
1.02
1.04
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
FRC (MHz)
25 °C
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL VALUE
FRC (MHz)ATmega8A [DATASHEET] 267
8159E–AVR–02/2013
28.11 Current Consumption of Peripheral Units
Figure 28-64. Brown-out Detector Current vs. VCC
Figure 28-65. ADC Current vs. VCC (AREF = AVCC)
85 °C
25 °C
-40 °C
0
4
8
12
16
20
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)
85 °C
25 °C
-40 °C
100
125
150
175
200
225
250
275
300
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)ATmega8A [DATASHEET] 268
8159E–AVR–02/2013
Figure 28-66. AREF External Reference Current vs. VCC
Figure 28-67. 32kHz TOSC Current vs. VCC (Watchdog Timer Disabled)
85 °C
25 °C
-40 °C
40
60
80
100
120
140
160
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)
85 °C
25 °C
-40 °C
0
2
4
6
8
10
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)ATmega8A [DATASHEET] 269
8159E–AVR–02/2013
Figure 28-68. Watchdog Timer Current vs. VCC
Figure 28-69. Analog Comparator Current vs. VCC
85 °C
25 °C
-40 °C
0
4
8
12
16
20
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
70
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)ATmega8A [DATASHEET] 270
8159E–AVR–02/2013
Figure 28-70. Programming Current vs. VCC
28.12 Current Consumption in Reset and Reset Pulsewidth
Figure 28-71. Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up)
85 °C
25 °C
-40 °C
0
1
2
3
4
5
6
2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (mA)
5.5 V
5.0 V
4.5 V
4.0 V
3.6 V
3.3 V
2.7 V
0
0.5
1
1.5
2
2.5
3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
ICC (mA)ATmega8A [DATASHEET] 271
8159E–AVR–02/2013
Figure 28-72. Reset Supply Current vs. VCC (1 - 16MHz, Excluding Current Through The Reset Pull-up)
Figure 28-73. Reset Pulse Width vs. VCC
5.5 V
5.0 V
4.5 V
4.0 V
3.6 V
3.3 V
2.7 V
0
2
4
6
8
10
12
0246 8 10 12 14 16
Frequency (MHz)
ICC (mA)
85 °C
25 °C
-40 °C
0
150
300
450
600
750
2,5 3 3,5 4 4,5 5 5,5
V CC (V)
Pulsewidth (ns)ATmega8A [DATASHEET] 272
8159E–AVR–02/2013
29. Typical Characteristics – TA = -40°C to 105°C
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption
measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A
sine wave generator with rail-to-rail output is used as clock source.
All Active- and Idle current consumption measurements are done with all bits in the PRR registers set and thus, the
corresponding I/O modules are turned off. Also the Analog Comparator is disabled during these measurements.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of
I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating
voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance,
VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at
frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down
mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.
29.1 ATmega8A Typical Characteristics
29.1.1 Active Supply Current
Figure 29-1. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
105 °C
85 °C
25 °C
-40 °C
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (mA)ATmega8A [DATASHEET] 273
8159E–AVR–02/2013
Figure 29-2. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz)
Figure 29-3. Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz)
105 °C
85 °C
25 °C
-40 °C
1.5
2
2.5
3
3.5
4
4.5
5
5.5
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (mA)
105 °C
85 °C
25 °C
-40 °C
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (mA)ATmega8A [DATASHEET] 274
8159E–AVR–02/2013
Figure 29-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
Figure 29-5. Active Supply Current vs. VCC (32 kHz External Oscillator)
105 °C
85 °C
25 °C
-40 °C
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (mA)
105 °C
85 °C
25 °C
-40 °C
35
38
41
44
47
50
53
56
59
62
65
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (uA)ATmega8A [DATASHEET] 275
8159E–AVR–02/2013
29.1.2 Idle Supply Current
Figure 29-6. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
Figure 29-7. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz)
105 °C
85 °C
25 °C
-40 °C
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
3.6
3.9
4.2
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (mA)
105 °C
85 °C
25 °C
-40 °C
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (mA)ATmega8A [DATASHEET] 276
8159E–AVR–02/2013
Figure 29-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz)
Figure 29-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
105 °C
85 °C
25 °C
-40 °C
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (mA)
105 °C
85 °C
25 °C
-40 °C
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (mA)ATmega8A [DATASHEET] 277
8159E–AVR–02/2013
Figure 29-10. Idle Supply Current vs. VCC (32 kHz External RC Oscillator)
29.1.3 Power-down Supply Current
Figure 29-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)
105 °C
85 °C
25 °C
-40 °C
6.5
8.5
10.5
12.5
14.5
16.5
18.5
20.5
22.5
24.5
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (uA)
105 °C
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (uA)ATmega8A [DATASHEET] 278
8159E–AVR–02/2013
Figure 29-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)
29.1.4 Power-save Supply Current
Figure 29-13. Power-save Supply Current vs. VCC (Watchdog Timer Disabled)
105 °C
85 °C
25 °C
-40 °C
3
6
9
12
15
18
21
24
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (uA)
105 °C
85 °C
25 °C
-40 °C
4
5
6
7
8
9
10
11
12
13
14
15
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (uA)ATmega8A [DATASHEET] 279
8159E–AVR–02/2013
29.1.5 Standby Supply Current
Figure 29-14. Standby Supply Current vs. VCC (32 kHz External RC Oscillator)
29.1.6 Pin Pull-up
Figure 29-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
105 °C
85 °C
25 °C
-40 °C
7
9
11
13
15
17
19
21
23
25
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (uA)
0
20
40
60
80
100
120
140
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOP (V)
IOP (uA)
105 °C
85 °C
25 °C
-40 °CATmega8A [DATASHEET] 280
8159E–AVR–02/2013
Figure 29-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
Figure 29-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
105 °C
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
70
80
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
VOP (V)
IOP (uA)
0
10
20
30
40
50
60
70
80
90
100
110
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VRESET (V)
IRESET (uA)
105 °C
85 °C
25 °C
-40 °CATmega8A [DATASHEET] 281
8159E–AVR–02/2013
Figure 29-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
29.1.7 Pin Driver Strength
Figure 29-19. I/O Pin Output Voltage vs. Source Current (VCC = 5V)
105 °C
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
VRESET (V)
IRESET (uA)
105 °C
85 °C
25 °C
-40 °C
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5
5.1
0246 8 10 12 14 16 18 20
IOH (mA)
VOH (
V)ATmega8A [DATASHEET] 282
8159E–AVR–02/2013
Figure 29-20. I/O Pin Output Voltage vs. Source Current (VCC = 3V)
Figure 29-21. I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
0246 8 10 12 14 16 18 20
IOH (mA)
VOH (
V)
105 °C
85 °C
25 °C
-40 °C
105 °C
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
0.6
0246 8 10 12 14 16 18 20
IOL (mA)
VOL (
V)ATmega8A [DATASHEET] 283
8159E–AVR–02/2013
Figure 29-22. I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
29.1.8 Pin Threshold and Hysteresis
Figure 29-23. I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’)
105 °C
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0246 8 10 12 14 16 18 20
IOL(mA)
VOL (
V)
105 °C
85 °C
25 °C
-40 °C
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
Threshold (
V)ATmega8A [DATASHEET] 284
8159E–AVR–02/2013
Figure 29-24. I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’)
Figure 29-25. I/O Pin Input Hysteresis vs. VCC
105 °C
85 °C
25 °C
-40 °C
1
1.3
1.6
1.9
2.2
2.5
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
Threshold (
V)
105 °C
85 °C
25 °C
-40 °C
0.25
0.3
0.35
0.4
0.45
0.5
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
Input Hysteresis (m
V)ATmega8A [DATASHEET] 285
8159E–AVR–02/2013
Figure 29-26. Reset Pin as I/O - Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’)
Figure 29-27. Reset Pin as I/O - Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’)
105 °C
85 °C
25 °C
-40 °C
1.3
1.6
1.9
2.2
2.5
2.8
3.1
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
Threshold (
V)
105 °C
85 °C
25 °C
-40 °C
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
Threshold (
V)ATmega8A [DATASHEET] 286
8159E–AVR–02/2013
Figure 29-28. Reset Pin as I/O - Pin Hysteresis vs. VCC
Figure 29-29. Reset Input Threshold vs. VCC (VIH , Reset Pin Read as ‘1’)
105 °C
85 °C
25 °C
-40 °C
0.4
0.45
0.5
0.55
0.6
0.65
0.7
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
Input Hysteresis (m
V)
105 °C
85 °C
25 °C
-40 °C
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
Threshold (
V)ATmega8A [DATASHEET] 287
8159E–AVR–02/2013
Figure 29-30. Reset Input Threshold vs. VCC (VIL, Reset Pin Read as ‘0’)
Figure 29-31. Reset Pin Input Hysteresis vs. VCC
105 °C
85 °C
25 °C
-40 °C
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
Threshold (
V)
105 °C
85 °C
25 °C
-40 °C
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
Input Hysteresis (m
V)ATmega8A [DATASHEET] 288
8159E–AVR–02/2013
29.1.9 BOD Threshold
Figure 29-32. BOD Threshold vs. Temperature (VCC = 4.3V)
Figure 29-33. BOD Threshold vs. Temperature (VCC = 2.7V)
Rising Vcc
Falling Vcc
3.8
3.82
3.84
3.86
3.88
3.9
3.92
3.94
3.96
3.98
4
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
Temperature (°C)
Threshold (
V)
Rising Vcc
Falling Vcc
2.47
2.49
2.51
2.53
2.55
2.57
2.59
2.61
2.63
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
Temperature (°C)
Threshold (
V)ATmega8A [DATASHEET] 289
8159E–AVR–02/2013
Figure 29-34. Bandgap Voltage vs. Temperature
Figure 29-35. Bandgap Voltage vs. VCC
5.5V
5.0V
4.0V
3.3V
2.7V
1.8V
1.175
1.18
1.185
1.19
1.195
1.2
1.205
1.21
1.215
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
Temperature (°C)
Bandgap
Voltage (
V)
105 °C
85 °C
25 °C
-40 °C
1.175
1.18
1.185
1.19
1.195
1.2
1.205
1.21
1.215
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Bandgap
Voltage (
V)ATmega8A [DATASHEET] 290
8159E–AVR–02/2013
29.1.10 Internal Oscillator Speed
Figure 29-36. Watchdog Oscillator Frequency vs. VCC
Figure 29-37. Watchdog Oscillator Frequency vs. Temperature
105 °C
85 °C
25 °C
-40 °C
980
1000
1020
1040
1060
1080
1100
1120
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
FRC (kHz)
5.5 V
5.0 V
4.5 V
4.0 V
3.6 V
2.7 V
970
990
1010
1030
1050
1070
1090
1110
1130
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
Temperature (°C)
FRC (kHz)ATmega8A [DATASHEET] 291
8159E–AVR–02/2013
Figure 29-38. Calibrated 8 MHz RC Oscillator vs. Temperature
Figure 29-39. Calibrated 8 MHz RC Oscillator vs. VCC
5.5 V
5.0 V
4.5 V
4.0 V
3.6 V
3.0 V
2.7 V
6.6
6.8
7
7.2
7.4
7.6
7.8
8
8.2
8.4
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
Temperature (°C)
FRC (MHz)
105 °C
85 °C
25 °C
-40 °C
6.6
6.8
7
7.2
7.4
7.6
7.8
8
8.2
8.4
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
FRC (MHz)ATmega8A [DATASHEET] 292
8159E–AVR–02/2013
Figure 29-40. Calibrated 8 MHz RC Oscillator vs. OSCCAL Value
Figure 29-41. Calibrated 4 MHz RC Oscillator vs. Temperature
105 °C
85 °C
25 °C
-40 °C
2
4
6
8
10
12
14
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)
FRC (MHz)
5.5 V
5.0 V
4.5 V
4.0 V
3.6 V
3.0 V
2.7 V
3.55
3.65
3.75
3.85
3.95
4.05
4.15
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
Temperature (°C)
FRC (MHz)ATmega8A [DATASHEET] 293
8159E–AVR–02/2013
Figure 29-42. Calibrated 4 MHz RC Oscillator vs. VCC
Figure 29-43. Calibrated 4 MHz RC Oscillator vs. OSCCAL Value
105 °C
85 °C
25 °C
-40 °C
3.6
3.65
3.7
3.75
3.8
3.85
3.9
3.95
4
4.05
4.1
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
FRC (MHz)
105 °C
85 °C
25 °C
-40 °C
1
2
3
4
5
6
7
8
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)
FRC (MHz)ATmega8A [DATASHEET] 294
8159E–AVR–02/2013
Figure 29-44. Calibrated 2 MHz RC Oscillator vs. Temperature
Figure 29-45. Calibrated 2 MHz RC Oscillator vs. VCC
5.5 V
5.0 V
4.5 V
4.0 V
3.6 V
3.0 V
2.7 V
1.78
1.81
1.84
1.87
1.9
1.93
1.96
1.99
2.02
2.05
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
Temperature (°C)
FRC (MHz)
105 °C
85 °C
25 °C
-40 °C
1.8
1.83
1.86
1.89
1.92
1.95
1.98
2.01
2.04
2.07
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
FRC (MHz)ATmega8A [DATASHEET] 295
8159E–AVR–02/2013
Figure 29-46. Calibrated 2 MHz RC Oscillator vs. OSCCAL Value
Figure 29-47. Calibrated 1 MHz RC Oscillator vs. Temperature
105 °C
85 °C
25 °C
-40 °C
0.8
1.1
1.4
1.7
2
2.3
2.6
2.9
3.2
3.5
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)
FRC (MHz)
5.5 V
5.0 V
4.5 V
4.0 V
3.6 V
3.0 V
2.7 V
0.91
0.93
0.95
0.97
0.99
1.01
1.03
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
Temperature (°C)
FRC (MHz)ATmega8A [DATASHEET] 296
8159E–AVR–02/2013
Figure 29-48. Calibrated 1 MHz RC Oscillator vs. VCC
Figure 29-49. Calibrated 1 MHz RC Oscillator vs. OSCCAL Value
105 °C
85 °C
25 °C
-40 °C
0.9
0.92
0.94
0.96
0.98
1
1.02
1.04
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
FRC (MHz)
105 °C
85 °C
25 °C
-40 °C
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)
FRC (MHz)ATmega8A [DATASHEET] 297
8159E–AVR–02/2013
29.1.11 Current Consumption of Peripheral Units
Figure 29-50. Brown-out Detector Current vs. VCC
Figure 29-51. ADC Current vs. VCC (AREF = AVCC)
105 °C
85 °C
25 °C
-40 °C
8
9
10
11
12
13
14
15
16
17
18
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (uA)
105 °C
85 °C
25 °C
-40 °C
140
160
180
200
220
240
260
280
300
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (uA)ATmega8A [DATASHEET] 298
8159E–AVR–02/2013
Figure 29-52. Watchdog Timer Current vs. VCC
Figure 29-53. Analog Comparator Current vs. VCC
4
6
8
10
12
14
16
18
20
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (uA)
105 °C
85 °C
25 °C
-40 °C
32
36
40
44
48
52
56
60
64
68
72
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (mA)
105 °C
85 °C
25 °C
-40 °CATmega8A [DATASHEET] 299
8159E–AVR–02/2013
Figure 29-54. Programming Current vs. VCC
29.1.12 Current Consumption in Reset and Reset Pulsewidth
Figure 29-55. Reset Supply Current vs. Vcc (0.1 - 1.0 MHz, Excluding Current Through the Reset Pull-up)
105 °C
85 °C
25 °C
-40 °C
0
1
2
3
4
5
6
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
ICC (mA)
5.5 V
5.0 V
4.5 V
4.0 V
3.6 V
2.7 V
0
0.5
1
1.5
2
2.5
3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
ICC (mA)ATmega8A [DATASHEET] 300
8159E–AVR–02/2013
Figure 29-56. Reset Supply Current vs. Vcc (1 - 16 MHz, Excluding Current Through the Reset Pull-up)
Figure 29-57. Minimum Reset Pulsewidth vs. Vcc
5.5 V
5.0 V
4.5 V
4.0 V
3.6 V
2.7 V
0
2
4
6
8
10
12
0246 8 10 12 14 16
Frequency (MHz)
ICC (mA)
105 °C
85 °C
25 °C
-40 °C
100
200
300
400
500
600
700
800
2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC (V)
Pulse
width (ns)ATmega8A [DATASHEET] 301
8159E–AVR–02/2013
30. Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x3F (0x5F) SREG I T H S V N Z C 8
0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 10
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 10
0x3C (0x5C) Reserved
0x3B (0x5B) GICR INT1 INT0 – – – – IVSEL IVCE 47, 65
0x3A (0x5A) GIFR INTF1 INTF0 – – – – – – 65
0x39 (0x59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 69, 97, 115
0x38 (0x58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 70, 97, 97
0x37 (0x57) SPMCR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 205
0x36 (0x56) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 176
0x35 (0x55) MCUCR SE SM2 SM1 SM0 ISC11 ISC10 ISC01 ISC00 35, 64
0x34 (0x54) MCUCSR – – – – WDRF BORF EXTRF PORF 42
0x33 (0x53) TCCR0 – – – – – CS02 CS01 CS00 69
0x32 (0x52) TCNT0 Timer/Counter0 (8 Bits) 69
0x31 (0x51) OSCCAL Oscillator Calibration Register 31
0x30 (0x50) SFIOR – – – – ACME PUD PSR2 PSR10 55, 72, 115, 180
0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 92
0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 95
0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High byte 96
0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low byte 96
0x2B (0x4B) OCR1AH Timer/Counter1 – Output Compare Register A High byte 96
0x2A (0x4A) OCR1AL Timer/Counter1 – Output Compare Register A Low byte 96
0x29 (0x49) OCR1BH Timer/Counter1 – Output Compare Register B High byte 96
0x28 (0x48) OCR1BL Timer/Counter1 – Output Compare Register B Low byte 96
0x27 (0x47) ICR1H Timer/Counter1 – Input Capture Register High byte 96
0x26 (0x46) ICR1L Timer/Counter1 – Input Capture Register Low byte 96
0x25 (0x45) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 112
0x24 (0x44) TCNT2 Timer/Counter2 (8 Bits) 113
0x23 (0x43) OCR2 Timer/Counter2 Output Compare Register 114
0x22 (0x42) ASSR – – – – AS2 TCN2UB OCR2UB TCR2UB 114
0x21 (0x41) WDTCR – – – WDCE WDE WDP2 WDP1 WDP0 42
0x20(1) (0x40)(1) UBRRH URSEL – – – UBRR[11:8] 147
UCSRC URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 145
0x1F (0x3F) EEARH – – – – – – – EEAR8 18
0x1E (0x3E) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 18
0x1D (0x3D) EEDR EEPROM Data Register 18
0x1C (0x3C) EECR – – – – EERIE EEMWE EEWE EERE 18
0x1B (0x3B) Reserved
0x1A (0x3A) Reserved
0x19 (0x39) Reserved
0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 62
0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 62
0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 63
0x15 (0x35) PORTC – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 63
0x14 (0x34) DDRC – DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 63
0x13 (0x33) PINC – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 63
0x12 (0x32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 63
0x11 (0x31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 63
0x10 (0x30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 63
0x0F (0x2F) SPDR SPI Data Register 124
0x0E (0x2E) SPSR SPIF WCOL – – – – – SPI2X 124
0x0D (0x2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 123
0x0C (0x2C) UDR USART I/O Data Register 143
0x0B (0x2B) UCSRA RXC TXC UDRE FE DOR PE U2X MPCM 144
0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 145
0x09 (0x29) UBRRL USART Baud Rate Register Low byte 147
0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 180
0x07 (0x27) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 190
0x06 (0x26) ADCSRA ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 191
0x05 (0x25) ADCH ADC Data Register High byte 193
0x04 (0x24) ADCL ADC Data Register Low byte 193
0x03 (0x23) TWDR Two-wire Serial Interface Data Register 178
0x02 (0x22) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 178
0x01 (0x21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 177
0x00 (0x20) TWBR Two-wire Serial Interface Bit Rate Register 176ATmega8A [DATASHEET] 302
8159E–AVR–02/2013
Note: 1. Refer to the USART description for details on how to access UBRRH and UCSRC.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.ATmega8A [DATASHEET] 303
8159E–AVR–02/2013
31. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd Rd Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd Rd K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1
COM Rd One’s Complement Rd 0xFF Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd 0x00 Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd Rd (0xFF - K) Z,N,V 1
INC Rd Increment Rd Rd + 1 Z,N,V 1
DEC Rd Decrement Rd Rd 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd Rd Rd Z,N,V 1
CLR Rd Clear Register Rd Rd Rd Z,N,V 1
SER Rd Set Register Rd 0xFF None 1
MUL Rd, Rr Multiply Unsigned R1:R0 Rd x Rr Z,C 2
MULS Rd, Rr Multiply Signed R1:R0 Rd x Rr Z,C 2
MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 Rd x Rr Z,C 2
FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 (Rd x Rr) << 1 Z,C 2
FMULS Rd, Rr Fractional Multiply Signed R1:R0 (Rd x Rr) << 1 Z,C 2
FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 (Rd x Rr) << 1 Z,C 2
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC Z None 2
RCALL k Relative Subroutine Call PC PC + k + 1 None 3
ICALL Indirect Call to (Z) PC Z None 3
RET Subroutine Return PC STACK None 4
RETI Interrupt Return PC STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1 / 2 / 3
CP Rd,Rr Compare Rd Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd Rr C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1 / 2 / 3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1 / 2 / 3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1 / 2 / 3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1 / 2 / 3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1 / 2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1 / 2
BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1 / 2
BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1 / 2
BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1 / 2
BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1 / 2
BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1 / 2
BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1 / 2
BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1 / 2
BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1 / 2
BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1 / 2
BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1 / 2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1 / 2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1 / 2
BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1 / 2
BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1 / 2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1 / 2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1 / 2
Mnemonics Operands Description Operation Flags #Clocks
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1 / 2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1 / 2ATmega8A [DATASHEET] 304
8159E–AVR–02/2013
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd Rr None 1
MOVW Rd, Rr Copy Register Word Rd+1:Rd Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd K None 1
LD Rd, X Load Indirect Rd (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2
LD Rd, Y Load Indirect Rd (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2
LD Rd, Z Load Indirect Rd (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd (k) None 2
ST X, Rr Store Indirect (X) Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2
ST Y, Rr Store Indirect (Y) Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2
ST Z, Rr Store Indirect (Z) Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2
STS k, Rr Store Direct to SRAM (k) Rr None 2
LPM Load Program Memory R0 (Z) None 3
LPM Rd, Z Load Program Memory Rd (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3
SPM Store Program Memory (Z) R1:R0 None -
IN Rd, P In Port Rd P None 1
OUT P, Rr Out Port P Rr None 1
PUSH Rr Push Register on Stack STACK Rr None 2
POP Rd Pop Register from Stack Rd STACK None 2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2
CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2
LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1
ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0:6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3:0)Rd(7:4),Rd(7:4)Rd(3:0) None 1
BSET s Flag Set SREG(s) 1 SREG(s) 1
BCLR s Flag Clear SREG(s) 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) T None 1
SEC Set Carry C 1 C1
CLC Clear Carry C 0 C 1
SEN Set Negative Flag N 1 N1
CLN Clear Negative Flag N 0 N 1
SEZ Set Zero Flag Z 1 Z1
CLZ Clear Zero Flag Z 0 Z 1
SEI Global Interrupt Enable I 1 I1
CLI Global Interrupt Disable I 0 I 1
SES Set Signed Test Flag S 1 S1
CLS Clear Signed Test Flag S 0 S 1
SEV Set Twos Complement Overflow. V 1 V1
CLV Clear Twos Complement Overflow V 0 V 1
SET Set T in SREG T 1 T1
Mnemonics Operands Description Operation Flags #Clocks
CLT Clear T in SREG T 0 T 1
SEH Set Half Carry Flag in SREG H 1 H1
CLH Clear Half Carry Flag in SREG H 0 H 1
MCU CONTROL INSTRUCTIONS
31. Instruction Set Summary (Continued)ATmega8A [DATASHEET] 305
8159E–AVR–02/2013
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1
31. Instruction Set Summary (Continued)ATmega8A [DATASHEET] 306
8159E–AVR–02/2013
32. Ordering Information
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).
Also Halide free and fully Green.
3. Tape & Reel
4. See characterization specifications at 105C
Speed (MHz) Power Supply (V) Ordering Code(2) Package(1) Operation Range
16 2.7 - 5.5
ATmega8A-AU
ATmega8A-AUR(3)
ATmega8A-PU
ATmega8A-MU
ATmega8A-MUR(3)
32A
32A
28P3
32M1-A
32M1-A
Industrial
(-40C to 85C)
ATmega8A-AN
ATmega8A-ANR(3)
ATmega8A-PN
ATmega8A-MN
ATmega8A-MNR(3)
32A
32A
28P3
32M1-A
32M1-A
Extended
(-40C to 105C)(4)
Package Type
32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)ATmega8A [DATASHEET] 307
8159E–AVR–02/2013
33. Packaging Information
33.1 32A
TITLE DRAWING NO. REV.
32A, 32-lead, 7 x 7mm body size, 1.0mm body thickness,
0.8mm lead pitch, thin profile plastic quad flat package (TQFP) 32A C
2010-10-20
PIN 1 IDENTIFIER
0°~7°
PIN 1
L
C
A1 A2 A
D1
D
e E1 E
B
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 8.75 9.00 9.25
D1 6.90 7.00 7.10 Note 2
E 8.75 9.00 9.25
E1 6.90 7.00 7.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
COMMON DIMENSIONS
(Unit of measure = mm)
SYMBOL MIN NOM MAX NOTEATmega8A [DATASHEET] 308
8159E–AVR–02/2013
33.2 28P3
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
28P3, 28-lead (0.300"/7.62mm Wide) Plastic Dual
Inline Package (PDIP) 28P3 B
09/28/01
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
0º ~ 15º
D
e
eB
B2
(4 PLACES)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 4.5724
A1 0.508 – –
D 34.544 – 34.798 Note 1
E 7.620 – 8.255
E1 7.112 – 7.493 Note 1
B 0.381 – 0.533
B1 1.143 – 1.397
B2 0.762 – 1.143
L 3.175 – 3.429
C 0.203 – 0.356
eB – – 10.160
e 2.540 TYP
Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). ATmega8A [DATASHEET] 309
8159E–AVR–02/2013
32M1-A
34. Errata
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
32M1-A, 32-pad, 5 x 5 x 1.0mm Body, Lead Pitch 0.50mm, 32M1-A E
5/25/06
3.10mm Exposed Pad, Micro Lead Frame Package (MLF)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D1
D
E1 E
b e
A3
A2
A1
A
D2
E2
0.08 C
L
1
2
3
P
P
0
1
2
3
A 0.80 0.90 1.00
A1 – 0.02 0.05
A2 – 0.65 1.00
A3 0.20 REF
b 0.18 0.23 0.30
D
D1
D2 2.95 3.10 3.25
4.90 5.00 5.10
4.70 4.75 4.80
4.70 4.75 4.80
4.90 5.00 5.10
E
E1
E2 2.95 3.10 3.25
e 0.50 BSC
L 0.30 0.40 0.50
P – – 0.60
– – 12o
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0
Pin 1 ID
Pin #1 Notch
(0.20 R)
K 0.20 – –
K
KATmega8A [DATASHEET] 310
8159E–AVR–02/2013
The revision letter in this section refers to the revision of the ATmega8A device.
34.1 ATmega8A, rev. L
• First Analog Comparator conversion may be delayed
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• Signature may be Erased in Serial Programming Mode
• CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32kHz Oscillator is Used to Clock the
Asynchronous Timer/Counter2
• Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request
1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than
expected on some devices.
Problem Fix / Workaround
When the device has been powered or reset, disable then enable theAnalog Comparator before the first
conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous
Timer/Counter register (TCNTx) is 0x00.
Problem Fix / Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing
to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or
asynchronous Output Compare Register (OCRx).
3. Signature may be Erased in Serial Programming Mode
If the signature bytes are read before a chiperase command is completed, the signature may be erased causing
the device ID and calibration bytes to disappear. This is critical, especially, if the part is running on internal
RC oscillator.
Problem Fix / Workaround:
Ensure that the chiperase command has exceeded before applying the next command.
4. CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32kHz Oscillator is Used to
Clock the Asynchronous Timer/Counter2
When the internal RC Oscillator is used as the main clock source, it is possible to run the Timer/Counter2
asynchronously by connecting a 32kHz Oscillator between XTAL1/TOSC1 and XTAL2/TOSC2. But when the
internal RC Oscillator is selected as the main clock source, the CKOPT Fuse does not control the internal
capacitors on XTAL1/TOSC1 and XTAL2/TOSC2. As long as there are no capacitors connected to
XTAL1/TOSC1 and XTAL2/TOSC2, safe operation of the Oscillator is not guaranteed.
Problem Fix / Workaround
Use external capacitors in the range of 20 - 36 pF on XTAL1/TOSC1 and XTAL2/TOSC2. This will be fixed in
ATmega8A Rev. G where the CKOPT Fuse will control internal capacitors also when internal RC Oscillator is
selected as main clock source. For ATmega8A Rev. G, CKOPT = 0 (programmed) will enable the internal
capacitors on XTAL1 and XTAL2. Customers who want compatibility between Rev. G and older revisions,
must ensure that CKOPT is unprogrammed (CKOPT = 1).ATmega8A [DATASHEET] 311
8159E–AVR–02/2013
5. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an
unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.ATmega8A [DATASHEET] 312
8159E–AVR–02/2013
35. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision in
this section refers to the document revision.
35.1 Rev.8159E – 02/2013
35.2 Rev.8159D – 02/11
35.3 Rev.8159C – 07/09
35.4 Rev.8159B – 05/09
1. Applied the Atmel new page layout for datasheets including new logo and last page.
2. Removed the reference to the debuggers and In-Circuit Emulators.
3. Added “Capacitive touch sensing” on page 6.
4. Added “Electrical Characteristics – TA = -40°C to 105°C” on page 233.
5. Added “Typical Characteristics – TA = -40°C to 105°C” on page 272.
1. Updated the datasheet according to the Atmel new Brand Style Guide.
2. Updated “Performing Page Erase by SPM” on page 200 by adding an extra note.
3. Updated “Ordering Information” on page 306 to include Tape & Reel.
1. Updated “Errata” on page 309.
1. Updated “System and Reset Characteristics” on page 228 with new BODLEVEL values
2. Updated “ADC Characteristics” on page 232 with new VINT values.
3. Updated “Typical Characteristics – TA = -40°C to 85°C” view.
4. Updated “Errata” on page 309. ATmega8A, rev L.
5. Created a new Table Of Contents.ATmega8A [DATASHEET] 313
8159E–AVR–02/2013
35.5 Rev.8159A – 08/08
1. Initial revision (Based on the ATmega8/L datasheet 2486T-AVR-05/08)
2. Changes done compared to ATmega8/L datasheet 2486T-AVR-05/08:
– All Electrical Characteristics are moved to “Electrical Characteristics – TA =
-40°C to 85°C” on page 225.
– Updated “DC Characteristics” on page 225 with new VOL Max (0.9V and
0.6V) and typical value for ICC.
– Added “Speed Grades” on page 227.
– Added a new sub section “System and Reset Characteristics” on page 228.
– Updated “System and Reset Characteristics” on page 228 with new VBOT
BODLEVEL = 0 (3.6V, 4.0V and 4.2V).
– Register descriptions are moved to sub section at the end of each chapter.
– New graphics in “Typical Characteristics – TA = -40°C to 85°C” on page
235.
– New “Ordering Information” on page 306.Enter Title of Manual [DATASHEET] i
8159E–AVR–02/2013
Table of Contents
Features .....................................................................................................1
1 Pin Configurations ...................................................................................2
2 Overview ...................................................................................................3
2.1 Block Diagram ...................................................................................................3
2.2 Pin Descriptions .................................................................................................4
3 Resources .................................................................................................6
4 Data Retention ..........................................................................................6
5 About Code Examples .............................................................................6
6 Capacitive touch sensing ........................................................................6
7 AVR CPU Core ..........................................................................................7
7.1 Overview ............................................................................................................7
7.2 Arithmetic Logic Unit – ALU ...............................................................................8
7.3 Status Register ..................................................................................................8
7.4 General Purpose Register File ..........................................................................9
7.5 Stack Pointer ...................................................................................................10
7.6 Instruction Execution Timing ...........................................................................11
7.7 Reset and Interrupt Handling ...........................................................................12
8 AVR Memories ........................................................................................15
8.1 Overview ..........................................................................................................15
8.2 In-System Reprogrammable Flash Program Memory .....................................15
8.3 SRAM Data Memory ........................................................................................16
8.4 EEPROM Data Memory ..................................................................................17
8.5 I/O Memory ......................................................................................................17
8.6 Register Description ........................................................................................18
9 System Clock and Clock Options .........................................................24
9.1 Clock Systems and their Distribution ...............................................................24
9.2 Clock Sources .................................................................................................25
9.3 Crystal Oscillator .............................................................................................25
9.4 Low-frequency Crystal Oscillator .....................................................................27
9.5 External RC Oscillator .....................................................................................27
9.6 Calibrated Internal RC Oscillator .....................................................................29
9.7 External Clock .................................................................................................30Enter Title of Manual [DATASHEET] ii
8159E–AVR–02/2013
9.8 Timer/Counter Oscillator ..................................................................................30
9.9 Register Description ........................................................................................31
10 Power Management and Sleep Modes .................................................32
10.1 Sleep Modes ....................................................................................................32
10.2 Idle Mode .........................................................................................................32
10.3 ADC Noise Reduction Mode ............................................................................33
10.4 Power-down Mode ...........................................................................................33
10.5 Power-save Mode ............................................................................................33
10.6 Standby Mode .................................................................................................34
10.7 Minimizing Power Consumption ......................................................................34
10.8 Register Description ........................................................................................35
11 System Control and Reset .....................................................................36
11.1 Resetting the AVR ...........................................................................................36
11.2 Reset Sources .................................................................................................36
11.3 Internal Voltage Reference ..............................................................................39
11.4 Watchdog Timer ..............................................................................................40
11.5 Timed Sequences for Changing the Configuration of the Watchdog Timer ....40
11.6 Register Description ........................................................................................42
12 Interrupts .................................................................................................44
12.1 Interrupt Vectors in ATmega8A .......................................................................44
12.2 Register Description ........................................................................................47
13 I/O Ports ..................................................................................................49
13.1 Overview ..........................................................................................................49
13.2 Ports as General Digital I/O .............................................................................50
13.3 Alternate Port Functions ..................................................................................54
13.4 Register Description ........................................................................................62
14 External Interrupts .................................................................................64
14.1 Register Description ........................................................................................64
15 8-bit Timer/Counter0 ..............................................................................66
15.1 Features ..........................................................................................................66
15.2 Overview ..........................................................................................................66
15.3 Timer/Counter Clock Sources .........................................................................67
15.4 Counter Unit ....................................................................................................67
15.5 Operation .........................................................................................................67
15.6 Timer/Counter Timing Diagrams ......................................................................68Enter Title of Manual [DATASHEET] iii
8159E–AVR–02/2013
15.7 Register Description ........................................................................................69
16 Timer/Counter0 and Timer/Counter1 Prescalers .................................71
16.1 Overview ..........................................................................................................71
16.2 Internal Clock Source ......................................................................................71
16.3 Prescaler Reset ...............................................................................................71
16.4 External Clock Source .....................................................................................71
16.5 Register Description ........................................................................................72
17 16-bit Timer/Counter1 ............................................................................73
17.1 Features ..........................................................................................................73
17.2 Overview ..........................................................................................................73
17.3 Accessing 16-bit Registers ..............................................................................75
17.4 Timer/Counter Clock Sources .........................................................................78
17.5 Counter Unit ....................................................................................................78
17.6 Input Capture Unit ...........................................................................................79
17.7 Output Compare Units .....................................................................................81
17.8 Compare Match Output Unit ............................................................................83
17.9 Modes of Operation .........................................................................................84
17.10 Timer/Counter Timing Diagrams ......................................................................91
17.11 Register Description ........................................................................................92
18 8-bit Timer/Counter2 with PWM and Asynchronous Operation .........99
18.1 Features ..........................................................................................................99
18.2 Overview ..........................................................................................................99
18.3 Timer/Counter Clock Sources .......................................................................100
18.4 Counter Unit ..................................................................................................100
18.5 Output Compare Unit .....................................................................................101
18.6 Compare Match Output Unit ..........................................................................103
18.7 Modes of Operation .......................................................................................104
18.8 Timer/Counter Timing Diagrams ....................................................................108
18.9 Asynchronous Operation of the Timer/Counter .............................................109
18.10 Timer/Counter Prescaler ...............................................................................111
18.11 Register Description ......................................................................................112
19 Serial Peripheral Interface – SPI .........................................................116
19.1 Features ........................................................................................................116
19.2 Overview ........................................................................................................116
19.3 SS Pin Functionality ......................................................................................121Enter Title of Manual [DATASHEET] iv
8159E–AVR–02/2013
19.4 Data Modes ...................................................................................................121
19.5 Register Description ......................................................................................123
20 USART ...................................................................................................125
20.1 Features ........................................................................................................125
20.2 Overview ........................................................................................................125
20.3 Clock Generation ...........................................................................................127
20.4 Frame Formats ..............................................................................................129
20.5 USART Initialization .......................................................................................130
20.6 Data Transmission – The USART Transmitter ..............................................131
20.7 Asynchronous Data Reception ......................................................................138
20.8 Multi-processor Communication Mode ..........................................................141
20.9 Accessing UBRRH/UCSRC Registers ...........................................................142
20.10 Register Description ......................................................................................143
20.11 Examples of Baud Rate Setting .....................................................................147
21 Two-wire Serial Interface .....................................................................152
21.1 Features ........................................................................................................152
21.2 Overview ........................................................................................................152
21.3 Two-wire Serial Interface Bus Definition ........................................................154
21.4 Data Transfer and Frame Format ..................................................................155
21.5 Multi-master Bus Systems, Arbitration and Synchronization .........................157
21.6 Using the TWI ................................................................................................159
21.7 Multi-master Systems and Arbitration ............................................................174
21.8 Register Description ......................................................................................176
22 Analog Comparator ..............................................................................179
22.1 Overview ........................................................................................................179
22.2 Analog Comparator Multiplexed Input ...........................................................179
22.3 Register Description ......................................................................................180
23 Analog-to-Digital Converter ................................................................182
23.1 Features ........................................................................................................182
23.2 Overview ........................................................................................................182
23.3 Starting a Conversion ....................................................................................184
23.4 Prescaling and Conversion Timing ................................................................184
23.5 Changing Channel or Reference Selection ...................................................186
23.6 ADC Noise Canceler .....................................................................................187
23.7 ADC Conversion Result .................................................................................190Enter Title of Manual [DATASHEET] v
8159E–AVR–02/2013
23.8 Register Description ......................................................................................190
24 Boot Loader Support – Read-While-Write Self-Programming .........194
24.1 Features ........................................................................................................194
24.2 Overview ........................................................................................................194
24.3 Application and Boot Loader Flash Sections .................................................194
24.4 Read-While-Write and No Read-While-Write Flash Sections ........................194
24.5 Boot Loader Lock Bits ...................................................................................197
24.6 Entering the Boot Loader Program ................................................................198
24.7 Addressing the Flash During Self-Programming ...........................................198
24.8 Self-Programming the Flash ..........................................................................199
24.9 Register Description ......................................................................................205
25 Memory Programming .........................................................................207
25.1 Program And Data Memory Lock Bits ...........................................................207
25.2 Fuse Bits ........................................................................................................208
25.3 Signature Bytes .............................................................................................209
25.4 Calibration Byte .............................................................................................209
25.5 Page Size ......................................................................................................210
25.6 Parallel Programming Parameters, Pin Mapping, and Commands ...............210
25.7 Parallel Programming ....................................................................................212
25.8 Serial Downloading ........................................................................................220
25.9 Serial Programming Pin Mapping ..................................................................220
26 Electrical Characteristics – TA = -40°C to 85°C .................................225
26.1 Absolute Maximum Ratings* .........................................................................225
26.2 DC Characteristics .........................................................................................225
26.3 Speed Grades ...............................................................................................227
26.4 Clock Characteristics .....................................................................................227
26.5 System and Reset Characteristics ................................................................228
26.6 Two-wire Serial Interface Characteristics ......................................................229
26.7 SPI Timing Characteristics ............................................................................230
26.8 ADC Characteristics ......................................................................................232
27 Electrical Characteristics – TA = -40°C to 105°C ...............................233
27.1 DC Characteristics .........................................................................................233
28 Typical Characteristics – TA = -40°C to 85°C ....................................235
28.1 Active Supply Current ....................................................................................235
28.2 Idle Supply Current ........................................................................................239Enter Title of Manual [DATASHEET] vi
8159E–AVR–02/2013
28.3 Power-down Supply Current ..........................................................................242
28.4 Power-save Supply Current ...........................................................................243
28.5 Standby Supply Current ................................................................................244
28.6 Pin Pull-up .....................................................................................................247
28.7 Pin Driver Strength ........................................................................................249
28.8 Pin Thresholds and Hysteresis ......................................................................253
28.9 Bod Thresholds and Analog Comparator Offset ............................................258
28.10 Internal Oscillator Speed ...............................................................................260
28.11 Current Consumption of Peripheral Units ......................................................267
28.12 Current Consumption in Reset and Reset Pulsewidth ...................................270
29 Typical Characteristics – TA = -40°C to 105°C ..................................272
29.1 ATmega8A Typical Characteristics ................................................................272
30 Register Summary ................................................................................301
31 Instruction Set Summary .....................................................................303
32 Ordering Information ...........................................................................306
33 Packaging Information .........................................................................307
33.1 32A ................................................................................................................307
33.2 28P3 ..............................................................................................................308
34 Errata .....................................................................................................309
34.1 ATmega8A, rev. L ..........................................................................................310
35 Datasheet Revision History .................................................................312
35.1 Rev.8159E – 02/2013 ....................................................................................312
35.2 Rev.8159D – 02/11 ........................................................................................312
35.3 Rev.8159C – 07/09 ........................................................................................312
35.4 Rev.8159B – 05/09 ........................................................................................312
35.5 Rev.8159A – 08/08 ........................................................................................313
Table of Contents.......................................................................................iAtmel Corporation
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© 2013 Atmel Corporation. All rights reserved. / Rev.: 8159E–AVR–02/2013
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Atmel AVR1924: XMEGA-A1 Xplained Hardware
User's Guide
Features
• Atmel® ATxmega128A1 microcontroller
• External memory
- 8MB SDRAM
• Atmel AT32UC3B1256
- Communication gateway
- Programmer for Atmel AVR® XMEGA®
• Analog input (to ADC)
- Temperature sensor
- Light sensor
• Analog output (from DAC)
- Mono speaker via audio amplifier
• Digital I/O
- UART communication through USB gateway
- Eight mechanical button switches
- Eight LEDs
- Eight spare analog pins
- 24 spare digital pins
1 Introduction
The Atmel XMEGA-A1 Xplained evaluation kit is a hardware platform to evaluate
the Atmel ATxmega128A1 microcontroller.
The kit offers a larger range of features that enables the Atmel AVR XMEGA user
to get started using XMEGA peripherals right away and understand how to
integrate the XMEGA device in their own design.
Figure 1-1. XMEGA-A1 Xplained evaluation kit.
8-bit Atmel
Microcontrollers
Application Note
Preliminary
Rev. 8370C-AVR-12/11 2 Atmel AVR1924
8370C-AVR-12/11
2 Related items
Atmel FLIP (Flexible In-system Programmer)
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3886
Atmel AVR Studio® 4 (free Atmel IDE)
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=2725
Atmel AVR JTAGICE mkII (on-chip programming and debugging tool)
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3353
Atmel AVR ONE! (on-chip programming and debugging tool)
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4279
3 General information
This document targets the Atmel XMEGA-A1 Xplained evaluation kit, revision 9. The
schematic, layout, and bill of materials can be found online in the zip files associated
with this application note at:
http://www.atmel.com/products/AVR/xplain.asp?family_id=607&source=redirect.
The XMEGA-A1 Xplained kit is intended to demonstrate the Atmel ATxmega128A1
microcontroller, and the hardware that relates to the Atmel AT32UC3B1256 is,
therefore, not covered in this document.
Figure 3-1. Overview of the XMEGA-A1 Xplained kit.
SDRAM
ATxmega128A1 JTAG and PDI
DataFlash footprint
XMEGA PORT A
USB (COM and PSU)
ATxmega128A1
Speaker
XMEGA PORT C
Audio amp.
XMEGA PORT F Power jumper XMEGA PORT D/R
Light sensor
Temp. sensor
AT32UC3B1256
3.1 Preprogrammed firmware
The Atmel ATxmega128A1 and AT32UC3B1256 that come with the Atmel XMEGAA1
Xplained kit are both preprogrammed.
The preprogrammed firmware in the XMEGA plays different sounds when the
mechanical button switches are pushed. Atmel AVR1924
3
8370C-AVR-12/11
The preprogrammed Atmel AT32UC3B1256 firmware offers features such as a boot
loader for self-programming and a UART-to-USB gateway.
3.2 Power supply
The kit is powered via the USB connector, which leaves two options to power it:
Connect the kit either to a PC through a USB cable, or to a 5V USB power supply
(AC/DC adapter).
3.3 Measuring the XMEGA power consumption
As part of an evaluation of the Atmel ATxmega128A1, it can be of interest to measure
its power consumption. The power jumper (J300) is connected between the 3.3V
regulated voltage from the regulator and the ATxmega128A1 supply. By replacing the
jumper with an ammeter, it is possible to measure the current consumption of the
ATxmega128A1. No other components are connected to the same supply as the
ATxmega128A1, and other components, therefore, do not affect the measurement of
the ATxmega128A1 current consumption (except the DC leakage in the decoupling
capacitors).
3.4 Programming the XMEGA through the UART-to-USB gateway
The ATxmega128A1 has a pre-programmed UART boot loader. How to program the
device through the UART-to-USB gateway is described in the Atmel application note
“AVR1927: XMEGA-A1 Xplained Getting started guide”.
3.5 Communication through the UART-to-USB gateway
The XMEGA UARTC0 is connected to a UART on the AT32UC3B1256. The
AT32UC3B1256 UART is communicating at 115200 baud, using one start bit, eight
data bits, one stop bit, and no parity.
When the AT32UC3B1256 device is enumerated (connected to a PC), the data
transmitted from the XMEGA is passed on to a (virtual) COM port. This means that it
is possible to use a terminal program to receive the transmitted data on a PC.
Similarly, data transmitted from the PC COM port is passed on to the XMEGA UART
through the gateway.
NOTE The AT32UC3B1256 is also connected to the shared SPI and TWI lines, and so it is
also possible to add TWI and SPI gateway functionality for these serial interfaces, if
desired. This gateway functionality is not available in the default firmware for the
AT32UC3B1256. Please refer to the schematics for more information about these
connections. 4 Atmel AVR1924
8370C-AVR-12/11
4 Connectors
The Atmel XMEGA-A1 Xplained kit has five 10-pin, 100mil headers. One header is
used for programming the Atmel ATxmega128A1, and the others are used to access
spare analog and digital pins on the XMEGA (expansion headers).
4.1 Programming headers
The XMEGA can be programmed and debugged by connecting an external
programming/debugging tool to the JTAG and PDI header (J201). The header has a
standard JTAG programmer pin-out (refer to online help in the Atmel AVR Studio),
and tools like the JTAGICE mkII or AVR ONE! can thus be connected directly to the
header. If it is desired to use PDI programming/debugging, an adapter must be used.
Due to physical differences of the JTAGICE mkII and AVR ONE! probes, the PCB has
an opening below the JTAG and PDI header. This is to make room for the orientation
tap on the JTAGICE mkII probe.
Because JTAG TDO and PDI DATA are connected on the PCB for this kit, JTAG
must be disabled on the device in order to use PDI. The reason for this is that when
JTAG is enabled it will enable a pull-up internally on TDO which interferes with the
PDI initialization sequence.
The connection of JTAG_TDO with PDI_DATA is also an issue when the application
on the device uses the JTAG_TDO pin e.g. by driving this pin actively or by using a
pull-up. This will interfere with ongoing PDI communication. Additionally, when JTAG
is disabled and the application is driving the JTAG_TDO pin it might even be not
possible to establish a PDI connection. A workaround for this is to add a ~1k resistor
from PDI_CLK/RESET to GND. This will keep the device in reset while PDI is
enabled. When a PDI connection is established the flash can be erased or JTAG can
be enabled in order to "unlock" the kit.
Table 4-1. XMEGA programming and debugging interface – JTAG and PDI.
J201 pin JTAG (1) PDI (2)
1 TCK -
2 GND GND (3)
3 TDO DATA
4 VCC VCC (3)
5 TMS -
6 nSRST CLK
7 - -
8 - -
9 TDI -
10 GND GND (3)
Notes: 1. Standard pin-out for JTAGICE mkII and other Atmel programming tools.
2. Requires adapter to connect a JTAGICE mkII (refer to AVR Studio help).
3. It is only required to connect on VCC/GND pin.
The Atmel AT32UC3B1256 can be programmed through its boot loader. The boot
loader is evoked by shorting the J600 jumper before applying power to the board. The Atmel AVR1924
5
8370C-AVR-12/11
programming is performed through the FLIP plug-in in AVR Studio (which can also be
started as a standalone application).
FLIP (Flexible In-system Programmer) is free Atmel proprietary software that runs on
Windows® 9x/Me/NT/2000/XP and Linux® x86. FLIP supports in-system programming
of flash devices through RS232, USB, or CAN.
Alternatively, the AT32UC3B1256 can be programmed by connecting a programming
tool, such as JTAGICE mkII, to test points TP600-607.
NOTE It is not recommended to program the AT32UC3B1256 using a programming tool, as
this will erase the boot loader.
4.2 I/O expansion headers
The XMEGA analog PORTA is available on the J2 header. This allows the user to
connect external signals to the analog-to-digital converter (ADC), digital-to-analog
converter (DAC), and analog comparators on PORTA.
The XMEGA digital PORTF and PORTC are available on the J1 and J4 headers,
respectively. These ports feature general-purpose I/O and various communication
modules (USART, SPI, and TWI). PORTD and PORTF are mixed on the J3 header.
NOTE The communication modules on PORTC and PORTF can be interconnected to test
various functions and features: The USART can loop back communication with a
jumper, or communicate between the two USARTs on the port. The native SPI and
the USART in SPI master mode can be connected, and the TWI module can be
enabled in both master and slave modes at the same time to get loop-back behavior.
(Pull-up resistors can be mounted on R101 and R102. These are not mounted from
the factory.) 6 Atmel AVR1924
8370C-AVR-12/11
5 Attached memories
The Atmel XMEGA-A1 Xplained kit demonstrates how to use the external bus
interface (EBI) module to connect a 4-bit SDRAM. An 8MB SDRAM (16Mb x 4) is
attached in three-port EBI mode (PORTH, PORTK, and PORTJ). Atmel AVR1924
7
8370C-AVR-12/11
6 Miscellaneous I/O
6.1 Mechanical button switches
Eight mechanical button switches are connected to XMEGA PORTD(PD0:PD5) and
PORTR(PR0:PR1). Internal pull-ups should be enabled to detect when the buttons
are pushed, as they short the respective line to GND.
NOTE Buttons share the pins with the J3 header: Pushing the buttons potentially affects
communication or other functionality on these pins.
6.2 LEDs
Eight yellow LEDs are connected to XMEGA PORTE. The LEDs are active low, and
thus light up when the respective lines are output low by the XMEGA.
One green and one red LED are inside the same package and therefore the colors
can be mixed to orange when both are activated. The red LED can be activated by
driving the connected I/O line to GND. The green LED is controlled via a FET and is
by default on when the board is powered. However this power indicator LED can also
be turned off by driving the gate of the FET to GND. Both LEDs are controlled by the
Atmel AT32UC3B1256. The default firmware will use the red LED to signal activity on
the UART to USB bridge by toggling the LED.
6.3 Analog I/O
An NTC temperature sensor and a light sensor are connected to PORTB on PB0 and
PB1, respectively. These analog references can be used as input to the ADC.
An audio amplifier (and mono speaker) is connected to PORTB on pin PB2. This pin
is connected to the XMEGA DAC, and thus offers a way to generate sound. 8 Atmel AVR1924
8370C-AVR-12/11
7 Included code example
The example application is based on the Atmel AVR Software Framework found
online at http://asf.atmel.no. For documentation, help, and examples on the drivers
used, please see the website.
For more information about the included code example, see the Atmel application
note “AVR1927: XMEGA-A1 Xplained Getting Started Guide”.
7.1 Compiling and running
The code examples to be found in ASF can be compiled by running make on the
makefile included in the project, or by opening the project in IAR™, and compiling the
project within IAR. Atmel AVR1924
9
8370C-AVR-12/11
8 Further code examples and drivers
Several Getting-Started trainings for the Atmel XMEGA-A1 Xplained kit can be
downloaded from the Atmel website. These trainings offer general introduction to
XMEGA peripherals. Please refer to AVR1500 through AVR1510.
Further information and drivers for XMEGA can be downloaded as application notes,
also distributed from the Atmel website. 10 Atmel AVR1924
8370C-AVR-12/11
9 Known issues
9.1 Light sensor
The output range of the light sensor is 0V – 3.3V. The ADC reference must therefore
be high enough to match the output range of the light sensor when performing
measurements.
9.2 USB test points
Touching the test points of the USB data lines on the reverse side of the board while
there is an ongoing communication, might interrupt the device and cause the device
to stop responding. The kit must be reconnected to start working properly again.
9.3 PDI initialization
Because JTAG_TDO and PDI_DATA are connected on the PCB for this kit, JTAG
must be disabled on the device in order to use PDI. The reason for this is that when
JTAG is enabled it will enable a pull-up internally on TDO which interferes with the
PDI initialization sequence.
The connection of JTAG_TDO with PDI_DATA is also an issue when the application
on the device uses the JTAG_TDO pin e.g. by driving this pin actively or by using a
pull-up. This will interfere with ongoing PDI communication. Additionally, when JTAG
is disabled and the application is driving the JTAG_TDO pin it might even not be
possible to establish a PDI connection. A workaround for this is to add a ~1k resistor
from PDI_CLK/RESET to GND. This will keep the device in reset while PDI is
enabled. When a PDI connection is established the flash can be erased or JTAG can
be enabled in order to "unlock" the kit. Atmel AVR1924
11
8370C-AVR-12/11
10 Revision history
The revision of the evaluation kit can be found on the sticker on the reverse side of
the PCB.
10.1 Revision 7
The Atmel XMEGA-A1 Xplained kit, revision 7, is the first released revision of the
XMEGA-A1 Xplained kit.
This kit replaces the Atmel Xplain evaluation kit. Information about the original Xplain
evaluation kit can be found in the Atmel application note AVR1907: Xplain Hardware
User’s Guide.
10.2 Revisions 1 to 6
Not released. 12 Atmel AVR1924
8370C-AVR-12/11
11 Table of contents
Features............................................................................................... 1
1 Introduction...................................................................................... 1
2 Related items.................................................................................... 2
3 General information......................................................................... 2
3.1 Preprogrammed firmware.................................................................................... 2
3.2 Power supply....................................................................................................... 3
3.3 Measuring the XMEGA power consumption ....................................................... 3
3.4 Programming the XMEGA through the UART-to-USB gateway ......................... 3
3.5 Communication through the UART-to-USB gateway.......................................... 3
4 Connectors....................................................................................... 4
4.1 Programming headers......................................................................................... 4
4.2 I/O expansion headers ........................................................................................ 5
5 Attached memories.......................................................................... 6
6 Miscellaneous I/O............................................................................. 7
6.1 Mechanical button switches ................................................................................ 7
6.2 LEDs.................................................................................................................... 7
6.3 Analog I/O............................................................................................................ 7
7 Included code example ................................................................... 8
7.1 Compiling and running ........................................................................................ 8
8 Further code examples and drivers ............................................... 9
9 Known issues................................................................................. 10
9.1 Light sensor....................................................................................................... 10
9.2 USB test points.................................................................................................. 10
9.3 PDI initialization................................................................................................. 10
10 Revision history ........................................................................... 11
10.1 Revision 7........................................................................................................ 11
10.2 Revisions 1 to 6............................................................................................... 11
11 Table of contents ......................................................................... 128370C-AVR-12/11
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: (+1)(408) 441-0311
Fax: (+1)(408) 487-2600
www.atmel.com
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JAPAN
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Fax: (+81) 3-6417-0370
© 2011 Atmel Corporation. All rights reserved.
Atmel®
, Atmel logo and combinations thereof, AVR®
, AVR Logo®
, AVR Studio®
, XMEGA®
and others are registered trademarks or
trademarks of Atmel Corporation or its subsidiaries. Windows®
and others are registered trademarks of Microsoft Corporation in U.S.
and or other countries. Other terms and product names may be trademarks of others.
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to
any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL
TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS
ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE
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warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and
product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically
provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or
warranted for use as components in applications intended to support or sustain life.
Features
• High-performance, Low-power Atmel®AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 130 Powerful Instructions – Most Single-clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments
– 8Kbytes of In-System Self-programmable Flash program memory
– 512Bytes EEPROM
– 1Kbyte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Three PWM Channels
– 8-channel ADC in TQFP and QFN/MLF package
Eight Channels 10-bit Accuracy
– 6-channel ADC in PDIP package
Six Channels 10-bit Accuracy
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
• I/O and Packages
– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF
• Operating Voltages
– 2.7V - 5.5V (ATmega8L)
– 4.5V - 5.5V (ATmega8)
• Speed Grades
– 0 - 8MHz (ATmega8L)
– 0 - 16MHz (ATmega8)
• Power Consumption at 4Mhz, 3V, 25C
– Active: 3.6mA
– Idle Mode: 1.0mA
– Power-down Mode: 0.5µA
8-bit Atmel with
8KBytes InSystem
Programmable
Flash
ATmega8
ATmega8L
Rev.2486AA–AVR–02/20132
2486AA–AVR–02/2013
ATmega8(L)
Pin
Configurations
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
(INT1) PD3
(XCK/T0) PD4
GND
VCC
GND
VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0
(OC1A) PB1
(SS/OC1B) PB2
(MOSI/OC2) PB3
(MISO) PB4
PD2 (INT0)
PD1 (TXD)
PD0 (RXD)
PC6 (RESET)
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
TQFP Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
(RESET) PC6
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(XCK/T0) PD4
VCC
GND
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
PC1 (ADC1)
PC0 (ADC0)
GND
AREF
AVCC
PB5 (SCK)
PB4 (MISO)
PB3 (MOSI/OC2)
PB2 (SS/OC1B)
PB1 (OC1A)
PDIP
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
MLF Top View
(INT1) PD3
(XCK/T0) PD4
GND
VCC
GND
VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0
(OC1A) PB1
(SS/OC1B) PB2
(MOSI/OC2) PB3
(MISO) PB4
PD2 (INT0)
PD1 (TXD)
PD0 (RXD)
PC6 (RESET)
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
NOTE:
The large center pad underneath the MLF
packages is made of metal and internally
connected to GND. It should be soldered
or glued to the PCB to ensure good
mechanical stability. If the center pad is
left unconneted, the package might
loosen from the PCB.3
2486AA–AVR–02/2013
ATmega8(L)
Overview The Atmel®AVR® ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves
throughputs approaching 1MIPS per MHz, allowing the system designer to optimize power consumption
versus processing speed.
Block Diagram Figure 1. Block Diagram
INTERNAL
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
MCU CTRL.
& TIMING
OSCILLATOR
TIMERS/
COUNTERS
INTERRUPT
UNIT
STACK
POINTER
EEPROM
SRAM
STATUS
REGISTER
USART
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
PROGRAMMING
LOGIC SPI
ADC
INTERFACE
COMP.
INTERFACE
PORTC DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
+
-
PORTB DRIVERS/BUFFERS
PORTB DIGITAL INTERFACE
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
XTAL1
XTAL2
CONTROL
LINES
VCC
GND
MUX &
ADC
AGND
AREF
PC0 - PC6 PB0 - PB7
PD0 - PD7
AVR CPU
TWI
RESET4
2486AA–AVR–02/2013
ATmega8(L)
The Atmel®AVR® core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The
resulting architecture is more code efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
The ATmega8 provides the following features: 8 Kbytes of In-System Programmable Flash with
Read-While-Write capabilities, 512 bytes of EEPROM, 1 Kbyte of SRAM, 23 general purpose
I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare
modes, internal and external interrupts, a serial programmable USART, a byte oriented Twowire
Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with
10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port,
and five software selectable power saving modes. The Idle mode stops the CPU while allowing
the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Powerdown
mode saves the register contents but freezes the Oscillator, disabling all other chip functions
until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer
continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.
The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous
timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the
crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very
fast start-up combined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a
conventional non-volatile memory programmer, or by an On-chip boot program running on the
AVR core. The boot program can use any interface to download the application program in the
Application Flash memory. Software in the Boot Flash Section will continue to run while the
Application Flash Section is updated, providing true Read-While-Write operation. By combining
an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution
to many embedded control applications.
The ATmega8 is supported with a full suite of program and system development tools, including
C compilers, macro assemblers, program simulators, and evaluation kits.
Disclaimer Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Minimum and Maximum
values will be available after the device is characterized.5
2486AA–AVR–02/2013
ATmega8(L)
Pin Descriptions
VCC Digital supply voltage.
GND Ground.
Port B (PB7..PB0)
XTAL1/XTAL2/TOSC1/
TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator
amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting
Oscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1
input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in “Alternate Functions of Port B” on page
58 and “System Clock and Clock Options” on page 25.
Port C (PC5..PC0) Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics
of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 15 on page 38. Shorter pulses are not guaranteed to
generate a Reset.
The various special features of Port C are elaborated on page 61.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega8 as listed on page
63.
RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page
38. Shorter pulses are not guaranteed to generate a reset.6
2486AA–AVR–02/2013
ATmega8(L)
AVCC AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It should be
externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected
to VCC through a low-pass filter. Note that Port C (5..4) use digital supply voltage, VCC.
AREF AREF is the analog reference pin for the A/D Converter.
ADC7..6 (TQFP and
QFN/MLF Package
Only)
In the TQFP and QFN/MLF package, ADC7..6 serve as analog inputs to the A/D converter.
These pins are powered from the analog supply and serve as 10-bit ADC channels.7
2486AA–AVR–02/2013
ATmega8(L)
Resources A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
Note: 1.
Data Retention Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.8
2486AA–AVR–02/2013
ATmega8(L)
About Code
Examples
This datasheet contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compilation.
Be aware that not all C compiler vendors include bit definitions in the header files and
interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation
for more details.9
2486AA–AVR–02/2013
ATmega8(L)
Atmel AVR CPU
Core
Introduction This section discusses the Atmel®AVR® core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to access
memories, perform calculations, control peripherals, and handle interrupts.
Architectural
Overview
Figure 2. Block Diagram of the AVR MCU Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the Program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction
is pre-fetched from the Program memory. This concept enables instructions to be executed
in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 × 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical
ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
i/O Module 2
i/O Module1
i/O Module n10
2486AA–AVR–02/2013
ATmega8(L)
can also be used as an address pointer for look up tables in Flash Program memory. These
added function registers are the 16-bit X-register, Y-register, and Z-register, described later in
this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic operation,
the Status Register is updated to reflect information about the result of the operation.
The Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word format.
Every Program memory address contains a 16-bit or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot program section and the
Application program section. Both sections have dedicated Lock Bits for write and read/write
protection. The SPM instruction that writes into the Application Flash memory section must
reside in the Boot program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack
Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global
interrupt enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position.
The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers,
SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F.11
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Arithmetic Logic
Unit – ALU
The high-performance Atmel®AVR® ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, arithmetic operations between general
purpose registers or between a register and an immediate are executed. The ALU operations
are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations
of the architecture also provide a powerful multiplier supporting both signed/unsigned
multiplication and fractional format. For a detailed description, see “Instruction Set Summary” on
page 311.
Status Register The Status Register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the Instruction Set Reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination
for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 012
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• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
General Purpose
Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 3 shows the structure of the 32 general purpose working registers in the CPU.
Figure 3. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 3, each register is also assigned a Data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented
as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-pointer, Y-pointer, and Z-pointer Registers can be set to index any register in
the file.
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte13
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The X-register, Yregister
and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers
are 16-bit address pointers for indirect addressing of the Data Space. The three indirect
address registers X, Y and Z are defined as described in Figure 4.
Figure 4. The X-register, Y-register and Z-Register
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the Instruction Set Reference for details).
Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations
to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when address is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations
of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
Instruction
Execution Timing
This section describes the general access timing concepts for instruction execution. The
Atmel®AVR® CPU is driven by the CPU clock clkCPU, directly generated from the selected clock
source for the chip. No internal clock division is used.
15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)
Bit 15 14 13 12 11 10 9 8
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
0000000014
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Figure 5 shows the parallel instruction fetches and instruction executions enabled by the Harvard
architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 5. The Parallel Instruction Fetches and Instruction Executions
Figure 6 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Figure 6. Single Cycle ALU Operation
Reset and
Interrupt Handling
The Atmel®AVR® provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate Program Vector in the Program memory space. All interrupts
are assigned individual enable bits which must be written logic one together with the
Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on
the Program Counter value, interrupts may be automatically disabled when Boot Lock Bits
BLB02 or BLB12 are programmed. This feature improves software security. See the section
“Memory Programming” on page 215 for details.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of Vectors is shown in “Interrupts” on page 46. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the boot Flash section by setting the Interrupt
Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to
“Interrupts” on page 46 for more information. The Reset Vector can also be moved to the start of
the boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – ReadWhile-Write
Self-Programming” on page 202.
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU15
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When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled.
The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector
in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt
enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
global interrupt enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE ; start EEPROM write
sbi EECR, EEWE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1< xxx
... ... ...
Table 19. Reset and Interrupt Vectors Placement
BOOTRST(1) IVSEL Reset Address Interrupt Vectors Start Address
1 0 0x000 0x001
1 1 0x000 Boot Reset Address + 0x001
0 0 Boot Reset Address 0x001
0 1 Boot Reset Address Boot Reset Address + 0x00148
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When the BOOTRST Fuse is unprogrammed, the boot section size set to 2Kbytes and the
IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and
general program setup for the Reset and Interrupt Vector Addresses is:
AddressLabels Code Comments
$000 rjmp RESET ; Reset handler
;
$001 RESET:ldi r16,high(RAMEND); Main program start
$002 out SPH,r16 ; Set Stack Pointer to top of RAM
$003 ldi r16,low(RAMEND)
$004 out SPL,r16
$005 sei ; Enable interrupts
$006 xxx
;
.org $c01
$c01 rjmp EXT_INT0 ; IRQ0 Handler
$c02 rjmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
$c12 rjmp SPM_RDY ; Store Program Memory Ready Handler
When the BOOTRST Fuse is programmed and the boot section size set to 2Kbytes, the most
typical and general program setup for the Reset and Interrupt Vector Addresses is:
AddressLabels Code Comments
.org $001
$001 rjmp EXT_INT0 ; IRQ0 Handler
$002 rjmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
$012 rjmp SPM_RDY ; Store Program Memory Ready Handler
;
.org $c00
$c00 rjmp RESET ; Reset handler
;
$c01 RESET:ldi r16,high(RAMEND); Main program start
$c02 out SPH,r16 ; Set Stack Pointer to top of RAM
$c03 ldi r16,low(RAMEND)
$c04 out SPL,r16
$c05 sei ; Enable interrupts
$c06 xxx49
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When the BOOTRST Fuse is programmed, the boot section size set to 2Kbytes, and the IVSEL
bit in the GICR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
AddressLabels Code Comments
;
.org $c00
$c00 rjmp RESET ; Reset handler
$c01 rjmp EXT_INT0 ; IRQ0 Handler
$c02 rjmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
$c12 rjmp SPM_RDY ; Store Program Memory Ready Handler
$c13 RESET: ldi r16,high(RAMEND); Main program start
$c14 out SPH,r16 ; Set Stack Pointer to top of RAM
$c15 ldi r16,low(RAMEND)
$c16 out SPL,r16
$c17 sei ; Enable interrupts
$c18 xxx
Moving Interrupts
Between Application
and Boot Space
The General Interrupt Control Register controls the placement of the Interrupt Vector table.
General Interrupt
Control Register –
GICR
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the boot Flash section is determined
by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write
Self-Programming” on page 202 for details. To avoid unintentional changes of Interrupt Vector
tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If Interrupt
Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts
are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader
Support – Read-While-Write Self-Programming” on page 202 for details on Boot Lock Bits.
Bit 7 6 5 4 3 2 1 0
INT1 INT0 – – – – IVSEL IVCE GICR
Read/Write R/W R/W R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 050
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• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by
hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable
interrupts, as explained in the IVSEL description above. See Code Example below.
Assembly Code Example
Move_interrupts:
; Enable change of Interrupt Vectors
ldi r16, (1< CSn2:0 > 1). The number of system clock
cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution.
However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization
logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 30
shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector
logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch
is transparent in the high period of the internal system clock.
The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative
(CSn2:0 = 6) edge it detects.
Figure 30. T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the system
clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses
Tn_sync
(To Clock
Select Logic)
Synchronization Edge Detector
D Q D Q
LE
Tn D Q
clkI/O74
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sampling, the maximum frequency of an external clock it can detect is half the sampling frequency
(Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 31. Prescaler for Timer/Counter0 and Timer/Counter1(1)
Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 30 on page 73
Special Function IO
Register – SFIOR
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be reset.
The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will
have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a
reset of this prescaler will affect both timers. This bit will always be read as zero.
PSR10
Clear
clkT1 clkT0
T1
T0
clkI/O
Synchronization
Synchronization
Bit 7 6 5 4 3 2 1 0
– – – – ACME PUD PSR2 PSR10 SFIOR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 075
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16-bit
Timer/Counter1
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. The main features are:
• True 16-bit Design (that is, allows 16-bit PWM)
• Two Independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• External Event Counter
• Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
Overview Most register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit
channel. However, when using the register or bit defines in a program, the precise form must be
used, that is, TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 32 on page 76. For the
actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers,
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit
locations are listed in the “16-bit Timer/Counter Register Description” on page 96.76
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Figure 32. 16-bit Timer/Counter Block Diagram(1)
Note: 1. Refer to “Pin Configurations” on page 2, Table 22 on page 58, and Table 28 on page 63 for
Timer/Counter1 pin placement and description
Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register
(ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-
bit registers. These procedures are described in the section “Accessing 16-bit Registers” on
page 77. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU
access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible
in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer
Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers
are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the clock select logic is referred to as the timer clock (clkT1).
The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter
value at all time. The result of the compare can be used by the waveform generator to
generate a PWM or variable frequency output on the Output Compare Pin (OC1A/B). See “Output
Compare Units” on page 83. The Compare Match event will also set the Compare Match
Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.
Clock Select
Timer/Counter
DATA BUS
OCRnA
OCRnB
ICRn
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
= 0
TOP BOTTOM
Count
Clear
Direction
TOVn
(Int. Req.)
OCFnA
(Int. Req.)
OCFnB
(Int.Req.)
ICFn (Int.Req.)
TCCRnA TCCRnB
( From Analog
Comparator Ouput )
Tn Edge
Detector
( From Prescaler )
clkTn77
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The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered)
event on either the Input Capture Pin (ICP1) or on the Analog Comparator pins (see
“Analog Comparator” on page 186). The Input Capture unit includes a digital filtering unit (Noise
Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined
by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using
OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a
PWM output. However, the TOP value will in this case be double buffered allowing the TOP
value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used
as an alternative, freeing the OCR1A to be used as PWM output.
Definitions The following definitions are used extensively throughout the document:
Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit
AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version
regarding:
• All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt
Registers
• Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers
• Interrupt Vectors
The following control bits have changed name, but have same functionality and register location:
• PWM10 is changed to WGM10
• PWM11 is changed to WGM11
• CTC1 is changed to WGM12
The following bits are added to the 16-bit Timer/Counter Control Registers:
• FOC1A and FOC1B are added to TCCR1A
• WGM13 is added to TCCR1B
The 16-bit Timer/Counter has improvements that will affect the compatibility in some special
cases.
Accessing 16-bit
Registers
The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via
the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations.
The 16-bit timer has a single 8-bit register for temporary storing of the High byte of the 16-bit
access. The same temporary register is shared between all 16-bit registers within the 16-bit
timer. Accessing the Low byte triggers the 16-bit read or write operation. When the Low byte of a
16-bit register is written by the CPU, the High byte stored in the temporary register, and the Low
byte written are both copied into the 16-bit register in the same clock cycle. When the Low byte
Table 35. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.
MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal
65535).
TOP The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be one
of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in
the OCR1A or ICR1 Register. The assignment is dependent of the mode
of operation.78
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of a 16-bit register is read by the CPU, the High byte of the 16-bit register is copied into the temporary
register in the same clock cycle as the Low byte is read.
Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCR1A/B 16-
bit registers does not involve using the temporary register.
To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the
Low byte must be read before the High byte.
The following code examples show how to access the 16-bit Timer Registers assuming that no
interrupts updates the temporary register. The same principle can be used directly for accessing
the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit
access.
Note: 1. See “About Code Examples” on page 8
The assembly code example returns the TCNT1 value in the r17:r16 Register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt
occurs between the two instructions accessing the 16-bit register, and the interrupt code
updates the temporary register by accessing the same or any other of the 16-bit Timer Registers,
then the result of the access outside the interrupt will be corrupted. Therefore, when both
the main code and the interrupt code update the temporary register, the main code must disable
the interrupts during the 16-bit access.
The following code examples show how to do an atomic read of the TCNT1 Register contents.
Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Assembly Code Example(1)
...
; Set TCNT1 to 0x01FF
ldi r17,0x01
ldi r16,0xFF
out TCNT1H,r17
out TCNT1L,r16
; Read TCNT1 into r17:r16
in r16,TCNT1L
in r17,TCNT1H
...
C Code Example(1)
unsigned int i;
...
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
...79
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ATmega8(L)
Note: 1. See “About Code Examples” on page 8
The assembly code example returns the TCNT1 value in the r17:r16 Register pair.
Assembly Code Example(1)
TIM16_ReadTCNT1:
; Save Global Interrupt Flag
in r18,SREG
; Disable interrupts
cli
; Read TCNT1 into r17:r16
in r16,TCNT1L
in r17,TCNT1H
; Restore Global Interrupt Flag
out SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
/* Save Global Interrupt Flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore Global Interrupt Flag */
SREG = sreg;
return i;
}80
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The following code examples show how to do an atomic write of the TCNT1 Register contents.
Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Note: 1. See “About Code Examples” on page 8
The assembly code example requires that the r17:r16 Register pair contains the value to be written
to TCNT1.
Reusing the
Temporary High Byte
Register
If writing to more than one 16-bit register where the High byte is the same for all registers written,
then the High byte only needs to be written once. However, note that the same rule of
atomic operation described previously also applies in this case.
Timer/Counter
Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the clock select logic which is controlled by the clock select (CS12:0) bits located
in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler,
see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 73.
Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 33 on page 81 shows a block diagram of the counter and its surroundings.
Assembly Code Example(1)
TIM16_WriteTCNT1:
; Save Global Interrupt Flag
in r18,SREG
; Disable interrupts
cli
; Set TCNT1 to r17:r16
out TCNT1H,r17
out TCNT1L,r16
; Restore Global Interrupt Flag
out SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNT1( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save Global Interrupt Flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore Global Interrupt Flag */
SREG = sreg;
}81
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Figure 33. Counter Unit Block Diagram
Signal description (internal signals):
count Increment or decrement TCNT1 by 1
direction Select between increment and decrement
clear Clear TCNT1 (set all bits to zero)
clkT1 Timer/Counter clock
TOP Signalize that TCNT1 has reached maximum value
BOTTOM Signalize that TCNT1 has reached minimum value (zero)
The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (TCNT1H) containing
the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight
bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNT1H I/O location, the CPU accesses the High byte temporary register
(TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read,
and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows
the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data
bus. It is important to notice that there are special cases of writing to the TCNT1 Register when
the counter is counting that will give unpredictable results. The special cases are described in
the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source,
selected by the clock select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the
timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of
whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare Outputs OC1x. For more details about advanced counting
sequences and waveform generation, see “Modes of Operation” on page 87.
The Timer/Counter Overflow (TOV1) fLag is set according to the mode of operation selected by
the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.
Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give
them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple
events, can be applied via the ICP1 pin or alternatively, via the Analog Comparator unit.
TEMP (8-bit)
DATA BUS (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit) Control Logic
count
clear
direction
TOVn
(Int. Req.)
Clock Select
TOP BOTTOM
Tn Edge
Detector
( From Prescaler )
clkTn82
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ATmega8(L)
The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the
signal applied. Alternatively the time-stamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 34. The elements of
the block diagram that are not directly a part of the Input Capture unit are gray shaded. The
small “n” in register and bit names indicates the Timer/Counter number.
Figure 34. Input Capture Unit Block Diagram
When a change of the logic level (an event) occurs on the Input Capture Pin (ICP1), alternatively
on the Analog Comparator Output (ACO), and this change confirms to the setting of the edge
detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter
(TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at
the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (TICIE1 =
1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically
cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software
by writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the Low
byte (ICR1L) and then the High byte (ICR1H). When the Low byte is read the High byte is copied
into the High byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will
access the TEMP Register.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes
the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation
mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1
Register. When writing the ICR1 Register the High byte must be written to the ICR1H I/O location
before the Low byte is written to ICR1L.
For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers”
on page 77.
Input Capture Pin
Source
The main trigger source for the Input Capture unit is the Input Capture Pin (ICP1). Timer/Counter
1 can alternatively use the Analog Comparator Output as trigger source for the Input Capture
ICFn (Int. Req.)
Analog
Comparator
WRITE ICRn (16-bit Register)
ICRnH (8-bit)
Noise
Canceler
ICPn
Edge
Detector
TEMP (8-bit)
DATA BUS (8-bit)
ICRnL (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
ACO* ACIC* ICNC ICES83
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unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator
Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be
aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore
be cleared after the change.
Both the Input Capture Pin (ICP1) and the Analog Comparator Output (ACO) inputs are sampled
using the same technique as for the T1 pin (Figure 30 on page 73). The edge detector is also
identical. However, when the noise canceler is enabled, additional logic is inserted before the
edge detector, which increases the delay by four system clock cycles. Note that the input of the
noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform
Generation mode that uses ICR1 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing the
output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in
Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces additional
four system clock cycles of delay from a change applied to the input, to the update of the
ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the
prescaler.
Using the Input
Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be
overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt
handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dependent on the maximum number of clock
cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is
actively changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after
each capture. Changing the edge sensing must be done as early as possible after the ICR1
Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be
cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,
the clearing of the ICF1 Flag is not required (if an interrupt handler is used).
Output Compare
Units
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register
(OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output
Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare
Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared
when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writing
a logical one to its I/O bit location. The waveform generator uses the match signal to
generate an output according to operating mode set by the Waveform Generation mode
(WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals
are used by the waveform generator for handling the special cases of the extreme values in
some modes of operation (see “Modes of Operation” on page 87).
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (that
is counter resolution). In addition to the counter resolution, the TOP value defines the period
time for waveforms generated by the waveform generator.84
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Figure 35 shows a block diagram of the Output Compare unit. The small “n” in the register and
bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output
Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output
Compare unit are gray shaded.
Figure 35. Output Compare Unit, Block Diagram
The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double
buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare
Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR1x Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled
the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare)
Register is only changed by a write operation (the Timer/Counter does not update this register
automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the High byte
temporary register (TEMP). However, it is a good practice to read the Low byte first as when
accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register
since the compare of all 16-bit is done continuously. The High byte (OCR1xH) has to be
written first. When the High byte I/O location is written by the CPU, the TEMP Register will be
updated by the value written. Then when the Low byte (OCR1xL) is written to the lower eight
bits, the High byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare
Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers”
on page 77.
OCFnx (Int.Req.)
= (16-bit Comparator )
OCRnx Buffer (16-bit Register)
OCRnxH Buf. (8-bit)
OCnx
TEMP (8-bit)
DATA BUS (8-bit)
OCRnxL Buf. (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
WGMn3:0 COMnx1:0
OCRnx (16-bit Register)
OCRnxH (8-bit) OCRnxL (8-bit)
Waveform Generator
TOP
BOTTOM85
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ATmega8(L)
Force Output
Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC1x) bit. Forcing Compare Match will not set the
OCF1x Flag or reload/clear the timer, but the OC1x pin will be updated as if a real Compare
Match had occurred (the COM1x1:0 bits settings define whether the OC1x pin is set, cleared or
toggled).
Compare Match
Blocking by TCNT1
Write
All CPU writes to the TCNT1 Register will block any Compare Match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the
same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled.
Using the Output
Compare Unit
Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT1 when using any of the Output Compare
channels, independent of whether the Timer/Counter is running or not. If the value written to
TCNT1 equals the OCR1x value, the Compare Match will be missed, resulting in incorrect waveform
generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP
values. The Compare Match for the TOP will be ignored and the counter will continue to
0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is
downcounting.
The setup of the OC1x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC1x value is to use the Force Output Compare
(FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COM1x1:0 bits are not double buffered together with the compare value.
Changing the COM1x1:0 bits will take effect immediately.
Compare Match
Output Unit
The Compare Output mode (COM1x1:0) bits have two functions. The waveform generator uses
the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare Match.
Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 36 on page 86 shows a
simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O
bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control
Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring
to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a System
Reset occur, the OC1x Register is reset to “0”.86
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ATmega8(L)
Figure 36. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC1x) from the waveform
generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output)
is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible
on the pin. The port override function is generally independent of the Waveform Generation
mode, but there are some exceptions. Refer to Table 36 on page 96, Table 37 on page 96 and
Table 38 on page 97 for details.
The design of the Output Compare Pin logic allows initialization of the OC1x state before the
output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation.
See “16-bit Timer/Counter Register Description” on page 96.
The COM1x1:0 bits have no effect on the Input Capture unit.
PORT
DDR
D Q
D Q
OCnx
OCnx Pin
D Q Waveform
Generator
COMnx1
COMnx0
0
1
DATABUS
FOCnx
clkI/O87
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Compare Output Mode
and Waveform
Generation
The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COM1x1:0 = 0 tells the waveform generator that no action on the
OC1x Register is to be performed on the next Compare Match. For compare output actions in
the non-PWM modes refer to Table 36 on page 96. For fast PWM mode refer to Table 37 on
page 96, and for phase correct and phase and frequency correct PWM refer to Table 38 on page
97.
A change of the COM1x1:0 bits state will have effect at the first Compare Match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC1x strobe bits.
Modes of
Operation
The mode of operation (that is, the behavior of the Timer/Counter and the Output Compare pins)
is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output
mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output
generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM1x1:0 bits control whether the output should be set, cleared or toggle at a Compare
Match. See “Compare Match Output Unit” on page 85.
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 94.
Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in
the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be
written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the interval
between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
Clear Timer on
Compare Match (CTC)
Mode
In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register
are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 =
12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This
mode allows greater control of the Compare Match output frequency. It also simplifies the operation
of counting external events.
The timing diagram for the CTC mode is shown in Figure 37 on page 88. The counter value
(TCNT1) increases until a Compare Match occurs with either OCR1A or ICR1, and then counter
(TCNT1) is cleared.88
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Figure 37. CTC Mode, Timing Diagram
An interrupt can be generated at each time the counter value reaches the TOP value by either
using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However,
changing the TOP to a value close to BOTTOM when the counter is running with none or a
low prescaler value must be done with care since the CTC mode does not have the double buffering
feature. If the new value written to OCR1A or ICR1 is lower than the current value of
TCNT1, the counter will miss the Compare Match. The counter will then have to count to its maximum
value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur.
In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode
using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical
level on each Compare Match by setting the Compare Output mode bits to toggle mode
(COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for
the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum frequency
of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is
defined by the following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x0000.
Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a
high frequency PWM waveform generation option. The fast PWM differs from the other PWM
options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts
from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared
on the Compare Match between TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare
Output mode output is set on Compare Match and cleared at BOTTOM. Due to the single-slope
operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct
and phase and frequency correct PWM modes that use dual-slope operation. This high
frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capacitors),
hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either ICR1
or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the
TCNTn
OCnA
(Toggle)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
Period 1 2 3 4
(COMnA1:0 = 1)
f
OCnA
f
clk_I/O
2 N 1 + OCRnA = --------------------------------------------------89
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maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be
calculated by using the following equation:
In fast PWM mode the counter is incremented until the counter value matches either one of the
fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 =
14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer
clock cycle. The timing diagram for the fast PWM mode is shown in Figure 38. The figure shows
fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing
diagram shown as a histogram for illustrating the single-slope operation. The diagram includes
non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes
represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set
when a Compare Match occurs.
Figure 38. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition
the OCF1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A
or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler
routine can be used for updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a Compare Match will never occur between the TCNT1 and the OCR1x.
Note that when using fixed TOP values the unused bits are masked to zero when any of the
OCR1x Registers are written.
The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP
value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low
value when the counter is running with none or a low prescaler value, there is a risk that the new
ICR1 value written is lower than the current value of TCNT1. The result will then be that the
counter will miss the Compare Match at the TOP value. The counter will then have to count to
the MAX value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can
occur. The OCR1A Register, however, is double buffered. This feature allows the OCR1A I/O
location to be written anytime. When the OCR1A I/O location is written the value written will be
put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with
the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The
update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set.
RFPWM
log TOP + 1
log 2 = -----------------------------------
TCNTn
OCRnx / TOP Update
and TOVn Interrupt Flag
Set and OCnA Interrupt
Flag Set or ICFn
Interrupt Flag Set
(Interrupt on TOP)
Period 1 2 3 4 5 6 7 8
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)90
2486AA–AVR–02/2013
ATmega8(L)
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A
as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM1x1:0 to 3. See Table 37 on page 96. The actual OC1x
value will only be visible on the port pin if the data direction for the port pin is set as output
(DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at
the Compare Match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at
the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output
will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP
will result in a constant high or low output (depending on the polarity of the output set by the
COM1x1:0 bits).
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting
OC1A to toggle its logical level on each Compare Match (COM1A1:0 = 1). This applies only
if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have
a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is
similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Compare
unit is enabled in the fast PWM mode.
Phase Correct PWM
Mode
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on